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ryujinx
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Ryujinx.Tests
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Cpu
gdkchan 219f63ff4e Fix CPU FCVTN instruction implementation (slow path) (#4159) 3 years ago
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CpuContext.cs 0c87bf9ea4 Refactor CPU interface to allow the implementation of other CPU emulators (#3362) 3 years ago
CpuTest.cs 905a191e28 Use upstream unicorn for Ryujinx.Tests.Unicorn (#3771) 3 years ago
CpuTest32.cs 905a191e28 Use upstream unicorn for Ryujinx.Tests.Unicorn (#3771) 3 years ago
CpuTestAlu.cs d87c5375f1 Implement a custom value generator for the Tests of the CLS and CLZ instructions (Base: 32, 64 bits. Simd: 8, 16, 32 bits). (#696) 6 years ago
CpuTestAlu32.cs 8e119a1e96 Implement PLD and SUB (imm16) on T32, plus UADD8, SADD8, USUB8 and SSUB8 on both A32 and T32 (#3693) 3 years ago
CpuTestAluBinary.cs d7044b10a2 Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328) 5 years ago
CpuTestAluBinary32.cs 951700fdd8 Removed unused usings. (#3593) 3 years ago
CpuTestAluImm.cs 1e7ea76f14 Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489) 7 years ago
CpuTestAluImm32.cs 951700fdd8 Removed unused usings. (#3593) 3 years ago
CpuTestAluRs.cs a731ab3a2a Add a new JIT compiler for CPU code (#693) 6 years ago
CpuTestAluRs32.cs b1b6f294f2 Add most of the A32 instruction set to ARMeilleure (#897) 6 years ago
CpuTestAluRx.cs 1e7ea76f14 Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489) 7 years ago
CpuTestBf32.cs b1b6f294f2 Add most of the A32 instruction set to ARMeilleure (#897) 6 years ago
CpuTestBfm.cs 1e7ea76f14 Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489) 7 years ago
CpuTestCcmpImm.cs 1e7ea76f14 Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489) 7 years ago
CpuTestCcmpReg.cs 1e7ea76f14 Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489) 7 years ago
CpuTestCsel.cs 1e7ea76f14 Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489) 7 years ago
CpuTestMisc.cs a804db6eed Add Fmax/minv_V & S/Ushl_S Inst.s with Tests. Fix Maxps/d & Minps/d d… (#1335) 5 years ago
CpuTestMisc32.cs e36e97c64d CPU: This PR fixes Fpscr, among other things. (#1433) 5 years ago
CpuTestMov.cs d87c5375f1 Implement a custom value generator for the Tests of the CLS and CLZ instructions (Base: 32, 64 bits. Simd: 8, 16, 32 bits). (#696) 6 years ago
CpuTestMul.cs 1e7ea76f14 Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489) 7 years ago
CpuTestMul32.cs 951700fdd8 Removed unused usings. (#3593) 3 years ago
CpuTestSimd.cs 219f63ff4e Fix CPU FCVTN instruction implementation (slow path) (#4159) 3 years ago
CpuTestSimd32.cs db45688aa8 Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677) 3 years ago
CpuTestSimdCrypto.cs a731ab3a2a Add a new JIT compiler for CPU code (#693) 6 years ago
CpuTestSimdCrypto32.cs dd433c1296 Implement AESMC, AESIMC, AESE, AESD and VEOR AArch32 instructions (#982) 6 years ago
CpuTestSimdCvt.cs 60f7cba30a Implement FCVTNS (Scalar GP) (#2953) 4 years ago
CpuTestSimdCvt32.cs 8d41402fa6 A32: Implement VCVTT, VCVTB (#3710) 3 years ago
CpuTestSimdExt.cs a731ab3a2a Add a new JIT compiler for CPU code (#693) 6 years ago
CpuTestSimdFcond.cs a731ab3a2a Add a new JIT compiler for CPU code (#693) 6 years ago
CpuTestSimdFmov.cs a731ab3a2a Add a new JIT compiler for CPU code (#693) 6 years ago
CpuTestSimdImm.cs a731ab3a2a Add a new JIT compiler for CPU code (#693) 6 years ago
CpuTestSimdIns.cs a731ab3a2a Add a new JIT compiler for CPU code (#693) 6 years ago
CpuTestSimdLogical32.cs 951700fdd8 Removed unused usings. (#3593) 3 years ago
CpuTestSimdMemory32.cs 729ff5337c Fix increment on Arm32 NEON VLDn/VSTn instructions with regs > 1 (#3695) 3 years ago
CpuTestSimdMov32.cs 951700fdd8 Removed unused usings. (#3593) 3 years ago
CpuTestSimdReg.cs 430ba6da65 CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817) 5 years ago
CpuTestSimdReg32.cs db45688aa8 Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677) 3 years ago
CpuTestSimdRegElem.cs 4bd1ad16f9 Add Sqdmulh_Ve & Sqrdmulh_Ve Inst.s with Tests. (#2139) 5 years ago
CpuTestSimdRegElem32.cs 951700fdd8 Removed unused usings. (#3593) 3 years ago
CpuTestSimdRegElemF.cs a731ab3a2a Add a new JIT compiler for CPU code (#693) 6 years ago
CpuTestSimdShImm.cs 2cb8bd7006 CPU (A64): Add Scvtf_S_Fixed & Ucvtf_S_Fixed with Tests. (#1492) 5 years ago
CpuTestSimdShImm32.cs db45688aa8 Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677) 3 years ago
CpuTestSimdTbl.cs 16869402bf Add Tbx Inst. (fast & slow paths), with Tests. (#782) 6 years ago
CpuTestSystem.cs 7c111a3567 Add Mrs & Msr (Nzcv) Inst., with Tests. (#819) 6 years ago
CpuTestT32Alu.cs 951700fdd8 Removed unused usings. (#3593) 3 years ago
CpuTestT32Flow.cs bd9ac0fdaa T32: Implement B, B.cond, BL, BLX (#3155) 4 years ago
CpuTestT32Mem.cs 951700fdd8 Removed unused usings. (#3593) 3 years ago
CpuTestThumb.cs 951700fdd8 Removed unused usings. (#3593) 3 years ago
PrecomputedMemoryThumbTestCase.cs 951700fdd8 Removed unused usings. (#3593) 3 years ago
PrecomputedThumbTestCase.cs 7b35ebc64a T32: Implement ALU (shifted register) instructions (#3135) 4 years ago