LDj3SNuD b956bbc32c Add SHA1C, SHA1H, SHA1M, SHA1P, SHA1SU0, SHA1SU1 and Isb instructions; add 6 Tests (closed box). (#483) 7 anni fa
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ACryptoHelper.cs d021d5dfa9 Add AESD, AESE, AESIMC, AESMC instructions; add 4 simple Tests (closed box). (#365) 7 anni fa
AInst.cs 9670c096e4 Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now) 8 anni fa
AInstEmitAlu.cs 894459fcd7 Add Fmls_Se, Fmulx_Se/Ve, Smov_S Inst.; Opt. Clz/Clz_V, Cnt_V, Shl_V, S/Ushr_V, S/Usra_V Inst.; Add 11 Tests. Some fixes. (#449) 7 anni fa
AInstEmitAluHelper.cs 708761963e Fix corner cases of ADCS and SBFM 8 anni fa
AInstEmitBfm.cs 708761963e Fix corner cases of ADCS and SBFM 8 anni fa
AInstEmitCcmp.cs 62b827f474 Split main project into core,graphics and chocolarm4 subproject (#29) 8 anni fa
AInstEmitCsel.cs 950011c90f Added initial support for function names from symbol table on the cpu with tracing, fix wrong ImageEnd on executables with MOD0, fix issue on the CPU on input elimination for instruction with more than one register store 8 anni fa
AInstEmitException.cs 65105c2a3b Implement SvcGetThreadContext3 8 anni fa
AInstEmitFlow.cs 6d65e53664 Remove cold methods from the CPU cache (#224) 7 anni fa
AInstEmitHash.cs 8f6387128a Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183) 8 anni fa
AInstEmitMemory.cs 4731c7545d Fix mistake on astc conversion, make some static methods that shouldn't be public private, remove old commmented out code 8 anni fa
AInstEmitMemoryEx.cs b8133c1997 Thread scheduler rewrite (#393) 7 anni fa
AInstEmitMemoryHelper.cs c393cdf8e3 More flexible memory manager (#307) 7 anni fa
AInstEmitMove.cs 62b827f474 Split main project into core,graphics and chocolarm4 subproject (#29) 8 anni fa
AInstEmitMul.cs 62b827f474 Split main project into core,graphics and chocolarm4 subproject (#29) 8 anni fa
AInstEmitSimdArithmetic.cs 00d4f44bbb Add Sse Opt. for S/Uaddl_V, S/Uhadd_V, S/Uhsub_V, S/Umlal_V, S/Umlsl_V, S/Urhadd_V, S/Usubl_V Inst.; and for S/Urshr_V, S/Ursra_V Inst.. (#480) 7 anni fa
AInstEmitSimdCmp.cs e674b37710 Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. (full FP emu.). Add 4 FP Tests. (#468) 7 anni fa
AInstEmitSimdCrypto.cs d021d5dfa9 Add AESD, AESE, AESIMC, AESMC instructions; add 4 simple Tests (closed box). (#365) 7 anni fa
AInstEmitSimdCvt.cs e674b37710 Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. (full FP emu.). Add 4 FP Tests. (#468) 7 anni fa
AInstEmitSimdHash.cs b956bbc32c Add SHA1C, SHA1H, SHA1M, SHA1P, SHA1SU0, SHA1SU1 and Isb instructions; add 6 Tests (closed box). (#483) 7 anni fa
AInstEmitSimdHelper.cs e674b37710 Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. (full FP emu.). Add 4 FP Tests. (#468) 7 anni fa
AInstEmitSimdLogical.cs 0b52ee6627 Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405) 7 anni fa
AInstEmitSimdMemory.cs 514218ab98 Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225) 7 anni fa
AInstEmitSimdMove.cs 894459fcd7 Add Fmls_Se, Fmulx_Se/Ve, Smov_S Inst.; Opt. Clz/Clz_V, Cnt_V, Shl_V, S/Ushr_V, S/Usra_V Inst.; Add 11 Tests. Some fixes. (#449) 7 anni fa
AInstEmitSimdShift.cs 00d4f44bbb Add Sse Opt. for S/Uaddl_V, S/Uhadd_V, S/Uhsub_V, S/Umlal_V, S/Umlsl_V, S/Urhadd_V, S/Usubl_V Inst.; and for S/Urshr_V, S/Ursra_V Inst.. (#480) 7 anni fa
AInstEmitSystem.cs b956bbc32c Add SHA1C, SHA1H, SHA1M, SHA1P, SHA1SU0, SHA1SU1 and Isb instructions; add 6 Tests (closed box). (#483) 7 anni fa
AInstEmitter.cs 62b827f474 Split main project into core,graphics and chocolarm4 subproject (#29) 8 anni fa
AInstInterpreter.cs 9670c096e4 Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now) 8 anni fa
ASoftFallback.cs b956bbc32c Add SHA1C, SHA1H, SHA1M, SHA1P, SHA1SU0, SHA1SU1 and Isb instructions; add 6 Tests (closed box). (#483) 7 anni fa
ASoftFloat.cs e674b37710 Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. (full FP emu.). Add 4 FP Tests. (#468) 7 anni fa
AVectorHelper.cs e674b37710 Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. (full FP emu.). Add 4 FP Tests. (#468) 7 anni fa