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CpuTest.cs
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c106ae9944
Add Tbl_V Sse opt. with Tests. (#651)
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7 lat temu |
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CpuTestAlu.cs
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d87c5375f1
Implement a custom value generator for the Tests of the CLS and CLZ instructions (Base: 32, 64 bits. Simd: 8, 16, 32 bits). (#696)
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6 lat temu |
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CpuTestAluImm.cs
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1e7ea76f14
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
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7 lat temu |
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CpuTestAluRs.cs
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1e7ea76f14
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
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7 lat temu |
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CpuTestAluRx.cs
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1e7ea76f14
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
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7 lat temu |
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CpuTestBfm.cs
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1e7ea76f14
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
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7 lat temu |
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CpuTestCcmpImm.cs
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1e7ea76f14
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
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7 lat temu |
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CpuTestCcmpReg.cs
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1e7ea76f14
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
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7 lat temu |
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CpuTestCsel.cs
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1e7ea76f14
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
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7 lat temu |
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CpuTestMisc.cs
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a3d46e4133
Add Tests for instructions Fcvtzs_Gp_Fixed & Fcvtzu_Gp_Fixed, Scvtf_Gp_Fixed & Ucvtf_Gp_Fixed. (#603)
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7 lat temu |
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CpuTestMov.cs
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d87c5375f1
Implement a custom value generator for the Tests of the CLS and CLZ instructions (Base: 32, 64 bits. Simd: 8, 16, 32 bits). (#696)
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6 lat temu |
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CpuTestMul.cs
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1e7ea76f14
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
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7 lat temu |
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CpuTestSimd.cs
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d87c5375f1
Implement a custom value generator for the Tests of the CLS and CLZ instructions (Base: 32, 64 bits. Simd: 8, 16, 32 bits). (#696)
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6 lat temu |
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CpuTestSimdCrypto.cs
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1e7ea76f14
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
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7 lat temu |
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CpuTestSimdCvt.cs
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74da8785a5
Sse optimized the 32-bit Vector & Scalar integer-to-fp conversion instructions (signed & unsigned); added the related Gp & V_Fixed Tests (signed & unsigned). (#662)
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7 lat temu |
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CpuTestSimdExt.cs
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1bef70c068
Add Rshrn_V & Shrn_V Sse opt.. Add Mla_V, Mls_V & Mul_V Sse opt.; add Tests. (#614)
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7 lat temu |
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CpuTestSimdFcond.cs
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e603b7afbc
Add Sse Opt. for S/Umax_V, S/Umin_V, S/Uaddw_V, S/Usubw_V, Fabs_S/V, Fneg_S/V Inst.; for Fcvtl_V, Fcvtn_V Inst.; and for Fcmp_S Inst.. Add/Improve other Sse Opt.. Add Tests. (#496)
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7 lat temu |
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CpuTestSimdImm.cs
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dbc105eafb
Create CpuTestSimdImm.cs (#608)
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7 lat temu |
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CpuTestSimdIns.cs
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1bef70c068
Add Rshrn_V & Shrn_V Sse opt.. Add Mla_V, Mls_V & Mul_V Sse opt.; add Tests. (#614)
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7 lat temu |
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CpuTestSimdReg.cs
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1bef70c068
Add Rshrn_V & Shrn_V Sse opt.. Add Mla_V, Mls_V & Mul_V Sse opt.; add Tests. (#614)
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7 lat temu |
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CpuTestSimdRegElem.cs
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8f7fcede7f
Add Smlal_Ve, Smlsl_Ve, Smull_Ve, Umlal_Ve, Umlsl_Ve, Umull_Ve Inst.; add Tests. Add Sse Opt. for Trn1/2_V and Uzp1/2_V Inst. Nits. (#566)
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7 lat temu |
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CpuTestSimdRegElemF.cs
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1e7ea76f14
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
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7 lat temu |
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CpuTestSimdShImm.cs
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74da8785a5
Sse optimized the 32-bit Vector & Scalar integer-to-fp conversion instructions (signed & unsigned); added the related Gp & V_Fixed Tests (signed & unsigned). (#662)
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7 lat temu |
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CpuTestSimdTbl.cs
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c106ae9944
Add Tbl_V Sse opt. with Tests. (#651)
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7 lat temu |
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d87c5375f1
Implement a custom value generator for the Tests of the CLS and CLZ instructions (Base: 32, 64 bits. Simd: 8, 16, 32 bits). (#696)