 mageven
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c19cfca183
Implement PRFM (register variant) as NOP (#1956)
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5 lat temu |
 LDj3SNuD
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c3e0c41da3
CPU (A64): Add Fmaxnmp & Fminnmp Scalar Inst.s, Fast & Slow Paths; with Tests. (#1894)
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5 lat temu |
|
LDj3SNuD
|
430ba6da65
CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)
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5 lat temu |
|
LDj3SNuD
|
8a33e884f8
Fix Vnmls_S fast path (F64: losing input d value). Fix Vnmla_S & Vnmls_S slow paths (using fused inst.s). Fix Vfma_V slow path not using StandardFPSCRValue(). (#1775)
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5 lat temu |
 sharmander
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e901b7850c
CPU: Implement VRINTX.F32 | VRINTX.F64 (#1776)
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5 lat temu |
|
sharmander
|
3332b29f01
CPU: Implement VFMA (Vector) (#1762)
|
5 lat temu |
|
sharmander
|
36f6bbf5b9
CPU: Implement VFNMA.F32 | F.64 (#1783)
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5 lat temu |
|
sharmander
|
b479a43939
CPU: Implement VFNMS.F32/64 (#1758)
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5 lat temu |
 gdkchan
|
2f16491712
Get rid of Reflection.Emit dependency on CPU and Shader projects (#1626)
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5 lat temu |
|
LDj3SNuD
|
04e330cc00
Add Umaal & Vabd_I, Vabdl_I, Vaddl_I, Vhadd, Vqshrn, Vshll inst.s (slow paths). (#1577)
|
5 lat temu |
|
gdkchan
|
6cc187da59
SIMD&FP load/store with scale > 4 should be undefined (#1522)
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5 lat temu |
|
LDj3SNuD
|
2cb8bd7006
CPU (A64): Add Scvtf_S_Fixed & Ucvtf_S_Fixed with Tests. (#1492)
|
5 lat temu |
|
LDj3SNuD
|
6938988427
Fix Vcvt_FI & Vcvt_RM; Add Vfma_S & Vfms_S. Add Tests. (#1471)
|
5 lat temu |
 Valentin PONS
|
3af2ce74ec
Implements some 32-bit instructions (VBIC, VTST, VSRA) (#1192)
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5 lat temu |
|
LDj3SNuD
|
56a61a5758
CPU: A32: Fix Vabs_V & Vneg_V (S8, S16, S32 & F32); add Tests. (#1394)
|
5 lat temu |
|
LDj3SNuD
|
88619d71b8
CPU: A32: Add Vadd & Vsub Wide (S/U_8/16/32) Inst.s with Test. (#1390)
|
5 lat temu |
|
LDj3SNuD
|
a804db6eed
Add Fmax/minv_V & S/Ushl_S Inst.s with Tests. Fix Maxps/d & Minps/d d… (#1335)
|
5 lat temu |
 riperiperi
|
d7044b10a2
Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328)
|
5 lat temu |
|
riperiperi
|
9a49f8aec9
Fix VMVN (immediate), Add VPMIN, VPMAX, VMVN (register) (#1303)
|
5 lat temu |
|
riperiperi
|
fa286d3535
VABS takes one input register, not two. (#1300)
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5 lat temu |
|
LDj3SNuD
|
83d94b21d0
Add FMaxNmV & FMinNmV Inst.s with Test. (#1279)
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5 lat temu |
|
LDj3SNuD
|
1de16f7653
Add Fcvtas_S/V & Fcvtau_S/V. (#1018)
|
6 lat temu |
 Chenj168
|
31b94f4641
Move the MakeOp to OpCodeTable class, for reduce the use of ConcurrentDictionary (#996)
|
6 lat temu |
|
riperiperi
|
dd433c1296
Implement AESMC, AESIMC, AESE, AESD and VEOR AArch32 instructions (#982)
|
6 lat temu |
|
gdkchan
|
c26f3774bd
Implement VMULL, VMLSL, VRSHR, VQRSHRN, VQRSHRUN AArch32 instructions + other fixes (#977)
|
6 lat temu |
|
gdkchan
|
89ccec197e
Implement VMOVL and VORR.I32 AArch32 SIMD instructions (#960)
|
6 lat temu |
|
gdkchan
|
ab3b6ea6d4
A64 SIMD LDP and STP with size = 0b11 is undefined (#971)
|
6 lat temu |
|
gdkchan
|
fb0939f9b6
Add SSAT, SSAT16, USAT and USAT16 ARM32 instructions (#954)
|
6 lat temu |
|
gdkchan
|
b8ee5b15ab
Implement FACGE and FACGT (Scalar and Vector) AArch64 SIMD instructions (#956)
|
6 lat temu |
|
riperiperi
|
b1b6f294f2
Add most of the A32 instruction set to ARMeilleure (#897)
|
6 lat temu |
