Get rid of Reflection.Emit dependency on CPU and Shader projects (#1626)

* Get rid of Reflection.Emit dependency on CPU and Shader projects

* Remove useless private sets

* Missed those due to the alignment

ARMeilleure/Decoders/Block.cs

@@ -14,7 +14,7 @@ namespace ARMeilleure.Decoders
         public bool TailCall { get; set; }
         public bool Exit     { get; set; }
 
-        public List<OpCode> OpCodes { get; private set; }
+        public List<OpCode> OpCodes { get; }
 
         public Block()
         {

ARMeilleure/Decoders/Decoder.cs

@@ -339,7 +339,7 @@ namespace ARMeilleure.Decoders
 
             if (makeOp != null)
             {
-                return (OpCode)makeOp(inst, address, opCode);
+                return makeOp(inst, address, opCode);
             }
             else
             {

ARMeilleure/Decoders/OpCode.cs

@@ -5,8 +5,8 @@ namespace ARMeilleure.Decoders
 {
     class OpCode : IOpCode
     {
-        public ulong Address   { get; private set; }
-        public int   RawOpCode { get; private set; }
+        public ulong Address   { get; }
+        public int   RawOpCode { get; }
 
         public int OpCodeSizeInBytes { get; protected set; } = 4;
 
@@ -14,6 +14,8 @@ namespace ARMeilleure.Decoders
 
         public RegisterSize RegisterSize { get; protected set; }
 
+        public static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode(inst, address, opCode);
+
         public OpCode(InstDescriptor inst, ulong address, int opCode)
         {
             Address   = address;

ARMeilleure/Decoders/OpCode32.cs

@@ -4,6 +4,8 @@ namespace ARMeilleure.Decoders
     {
         public Condition Cond { get; protected set; }
 
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32(inst, address, opCode);
+
         public OpCode32(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             RegisterSize = RegisterSize.Int32;

ARMeilleure/Decoders/OpCode32Alu.cs

@@ -2,10 +2,12 @@ namespace ARMeilleure.Decoders
 {
     class OpCode32Alu : OpCode32, IOpCode32Alu
     {
-        public int Rd { get; private set; }
-        public int Rn { get; private set; }
+        public int Rd { get; }
+        public int Rn { get; }
 
-        public bool SetFlags { get; private set; }
+        public bool SetFlags { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Alu(inst, address, opCode);
 
         public OpCode32Alu(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32AluBf.cs

@@ -2,16 +2,18 @@
 {
     class OpCode32AluBf : OpCode32, IOpCode32AluBf
     {
-        public int Rd { get; private set; }
-        public int Rn { get; private set; }
+        public int Rd { get; }
+        public int Rn { get; }
 
-        public int Msb { get; private set; }
+        public int Msb { get; }
 
-        public int Lsb { get; private set; }
+        public int Lsb { get; }
 
         public int SourceMask => (int)(0xFFFFFFFF >> (31 - Msb));
         public int DestMask => SourceMask & (int)(0xFFFFFFFF << Lsb);
 
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluBf(inst, address, opCode);
+
         public OpCode32AluBf(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Rd = (opCode >> 12) & 0xf;

ARMeilleure/Decoders/OpCode32AluImm.cs

@@ -4,9 +4,11 @@ namespace ARMeilleure.Decoders
 {
     class OpCode32AluImm : OpCode32Alu
     {
-        public int Immediate { get; private set; }
+        public int Immediate { get; }
 
-        public bool IsRotated { get; private set; }
+        public bool IsRotated { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluImm(inst, address, opCode);
 
         public OpCode32AluImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32AluImm16.cs

@@ -2,7 +2,9 @@
 {
     class OpCode32AluImm16 : OpCode32Alu
     {
-        public int Immediate { get; private set; }
+        public int Immediate { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluImm16(inst, address, opCode);
 
         public OpCode32AluImm16(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32AluMla.cs

@@ -2,15 +2,17 @@
 {
     class OpCode32AluMla : OpCode32, IOpCode32AluReg
     {
-        public int Rn { get; private set; }
-        public int Rm { get; private set; }
-        public int Ra { get; private set; }
-        public int Rd { get; private set; }
+        public int Rn { get; }
+        public int Rm { get; }
+        public int Ra { get; }
+        public int Rd { get; }
 
-        public bool NHigh { get; private set; }
-        public bool MHigh { get; private set; }
-        public bool R { get; private set; }
-        public bool SetFlags { get; private set; }
+        public bool NHigh { get; }
+        public bool MHigh { get; }
+        public bool R { get; }
+        public bool SetFlags { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluMla(inst, address, opCode);
 
         public OpCode32AluMla(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32AluReg.cs

@@ -2,7 +2,9 @@
 {
     class OpCode32AluReg : OpCode32Alu, IOpCode32AluReg
     {
-        public int Rm { get; private set; }
+        public int Rm { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluReg(inst, address, opCode);
 
         public OpCode32AluReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32AluRsImm.cs

@@ -2,10 +2,12 @@ namespace ARMeilleure.Decoders
 {
     class OpCode32AluRsImm : OpCode32Alu
     {
-        public int Rm        { get; private set; }
-        public int Immediate { get; private set; }
+        public int Rm        { get; }
+        public int Immediate { get; }
 
-        public ShiftType ShiftType { get; private set; }
+        public ShiftType ShiftType { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluRsImm(inst, address, opCode);
 
         public OpCode32AluRsImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32AluRsReg.cs

@@ -2,10 +2,12 @@
 {
     class OpCode32AluRsReg : OpCode32Alu
     {
-        public int Rm { get; private set; }
-        public int Rs { get; private set; }
+        public int Rm { get; }
+        public int Rs { get; }
 
-        public ShiftType ShiftType { get; private set; }
+        public ShiftType ShiftType { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluRsReg(inst, address, opCode);
 
         public OpCode32AluRsReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32AluUmull.cs

@@ -2,16 +2,18 @@
 {
     class OpCode32AluUmull : OpCode32
     {
-        public int RdLo { get; private set; }
-        public int RdHi { get; private set; }
-        public int Rn { get; private set; }
-        public int Rm { get; private set; }
+        public int RdLo { get; }
+        public int RdHi { get; }
+        public int Rn { get; }
+        public int Rm { get; }
 
-        public bool NHigh { get; private set; }
-        public bool MHigh { get; private set; }
+        public bool NHigh { get; }
+        public bool MHigh { get; }
 
-        public bool SetFlags { get; private set; }
-        public DataOp DataOp { get; private set; }
+        public bool SetFlags { get; }
+        public DataOp DataOp { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluUmull(inst, address, opCode);
 
         public OpCode32AluUmull(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32AluUx.cs

@@ -4,10 +4,12 @@ namespace ARMeilleure.Decoders
 {
     class OpCode32AluUx : OpCode32AluReg, IOpCode32AluUx
     {
-        public int Rotate { get; private set; }
+        public int Rotate { get; }
         public int RotateBits => Rotate * 8;
         public bool Add => Rn != RegisterAlias.Aarch32Pc;
 
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluUx(inst, address, opCode);
+
         public OpCode32AluUx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Rotate = (opCode >> 10) & 0x3;

ARMeilleure/Decoders/OpCode32BImm.cs

@@ -2,7 +2,9 @@ namespace ARMeilleure.Decoders
 {
     class OpCode32BImm : OpCode32, IOpCode32BImm
     {
-        public long Immediate { get; private set; }
+        public long Immediate { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32BImm(inst, address, opCode);
 
         public OpCode32BImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32BReg.cs

@@ -2,7 +2,9 @@ namespace ARMeilleure.Decoders
 {
     class OpCode32BReg : OpCode32, IOpCode32BReg
     {
-        public int Rm { get; private set; }
+        public int Rm { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32BReg(inst, address, opCode);
 
         public OpCode32BReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32Exception.cs

@@ -2,7 +2,9 @@
 {
     class OpCode32Exception : OpCode32
     {
-        public int Id { get; private set; }
+        public int Id { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Exception(inst, address, opCode);
 
         public OpCode32Exception(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32Mem.cs

@@ -5,16 +5,18 @@ namespace ARMeilleure.Decoders
     class OpCode32Mem : OpCode32, IOpCode32Mem
     {
         public int Rt { get; protected set; }
-        public int Rn { get; private set; }
+        public int Rn { get; }
 
         public int Immediate { get; protected set; }
 
-        public bool Index        { get; private set; }
-        public bool Add          { get; private set; }
-        public bool WBack        { get; private set; }
-        public bool Unprivileged { get; private set; }
+        public bool Index        { get; }
+        public bool Add          { get; }
+        public bool WBack        { get; }
+        public bool Unprivileged { get; }
 
-        public bool IsLoad { get; private set; }
+        public bool IsLoad { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Mem(inst, address, opCode);
 
         public OpCode32Mem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32MemImm.cs

@@ -2,6 +2,8 @@ namespace ARMeilleure.Decoders
 {
     class OpCode32MemImm : OpCode32Mem
     {
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemImm(inst, address, opCode);
+
         public OpCode32MemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Immediate = opCode & 0xfff;

ARMeilleure/Decoders/OpCode32MemImm8.cs

@@ -2,6 +2,8 @@ namespace ARMeilleure.Decoders
 {
     class OpCode32MemImm8 : OpCode32Mem
     {
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemImm8(inst, address, opCode);
+
         public OpCode32MemImm8(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             int imm4L = (opCode >> 0) & 0xf;

ARMeilleure/Decoders/OpCode32MemLdEx.cs

@@ -2,7 +2,9 @@
 {
     class OpCode32MemLdEx : OpCode32Mem, IOpCode32MemEx
     {
-        public int Rd { get; private set; }
+        public int Rd { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemLdEx(inst, address, opCode);
 
         public OpCode32MemLdEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32MemMult.cs

@@ -2,13 +2,15 @@ namespace ARMeilleure.Decoders
 {
     class OpCode32MemMult : OpCode32, IOpCode32MemMult
     {
-        public int Rn { get; private set; }
+        public int Rn { get; }
 
-        public int RegisterMask { get; private set; }
-        public int Offset       { get; private set; }
-        public int PostOffset   { get; private set; }
+        public int RegisterMask { get; }
+        public int Offset       { get; }
+        public int PostOffset   { get; }
 
-        public bool IsLoad { get; private set; }
+        public bool IsLoad { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemMult(inst, address, opCode);
 
         public OpCode32MemMult(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32MemReg.cs

@@ -2,7 +2,9 @@
 {
     class OpCode32MemReg : OpCode32Mem
     {
-        public int Rm { get; private set; }
+        public int Rm { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemReg(inst, address, opCode);
 
         public OpCode32MemReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32MemRsImm.cs

@@ -2,8 +2,10 @@
 {
     class OpCode32MemRsImm : OpCode32Mem
     {
-        public int Rm { get; private set; }
-        public ShiftType ShiftType { get; private set; }
+        public int Rm { get; }
+        public ShiftType ShiftType { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemRsImm(inst, address, opCode);
 
         public OpCode32MemRsImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32MemStEx.cs

@@ -2,7 +2,9 @@
 {
     class OpCode32MemStEx : OpCode32Mem, IOpCode32MemEx
     {
-        public int Rd { get; private set; }
+        public int Rd { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemStEx(inst, address, opCode);
 
         public OpCode32MemStEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32Sat.cs

@@ -2,12 +2,14 @@ namespace ARMeilleure.Decoders
 {
     class OpCode32Sat : OpCode32
     {
-        public int Rn { get; private set; }
-        public int Imm5 { get; private set; }
-        public int Rd { get; private set; }
-        public int SatImm { get; private set; }
+        public int Rn { get; }
+        public int Imm5 { get; }
+        public int Rd { get; }
+        public int SatImm { get; }
 
-        public ShiftType ShiftType { get; private set; }
+        public ShiftType ShiftType { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Sat(inst, address, opCode);
 
         public OpCode32Sat(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32Sat16.cs

@@ -2,9 +2,11 @@ namespace ARMeilleure.Decoders
 {
     class OpCode32Sat16 : OpCode32
     {
-        public int Rn { get; private set; }
-        public int Rd { get; private set; }
-        public int SatImm { get; private set; }
+        public int Rn { get; }
+        public int Rd { get; }
+        public int SatImm { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Sat16(inst, address, opCode);
 
         public OpCode32Sat16(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32Simd.cs

@@ -5,7 +5,9 @@
         public int Opc { get; protected set; }
         public bool Q { get; protected set; }
         public bool F { get; protected set; }
-        public bool U { get; private set; }
+        public bool U { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Simd(inst, address, opCode);
 
         public OpCode32Simd(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32SimdBase.cs

@@ -10,7 +10,7 @@ namespace ARMeilleure.Decoders
 
         // Helpers to index doublewords within quad words. Essentially, looping over the vector starts at quadword Q and index Fx or Ix within it,
         // depending on instruction type.
-        // 
+        //
         // Qx: The quadword register that the target vector is contained in.
         // Ix: The starting index of the target vector within the quadword, with size treated as integer.
         // Fx: The starting index of the target vector within the quadword, with size treated as floating point. (16 or 32)

ARMeilleure/Decoders/OpCode32SimdBinary.cs

@@ -5,6 +5,8 @@
     /// </summary>
     class OpCode32SimdBinary : OpCode32SimdReg
     {
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdBinary(inst, address, opCode);
+
         public OpCode32SimdBinary(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Size = 3;

ARMeilleure/Decoders/OpCode32SimdCmpZ.cs

@@ -2,6 +2,8 @@
 {
     class OpCode32SimdCmpZ : OpCode32Simd
     {
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCmpZ(inst, address, opCode);
+
         public OpCode32SimdCmpZ(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Size = (opCode >> 18) & 0x3;

ARMeilleure/Decoders/OpCode32SimdCvtFI.cs

@@ -2,6 +2,8 @@
 {
     class OpCode32SimdCvtFI : OpCode32SimdS
     {
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCvtFI(inst, address, opCode);
+
         public OpCode32SimdCvtFI(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Opc = (opCode >> 7) & 0x1;

ARMeilleure/Decoders/OpCode32SimdDupElem.cs

@@ -2,7 +2,9 @@
 {
     class OpCode32SimdDupElem : OpCode32Simd
     {
-        public int Index { get; private set; }
+        public int Index { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdDupElem(inst, address, opCode);
 
         public OpCode32SimdDupElem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32SimdDupGP.cs

@@ -2,10 +2,12 @@
 {
     class OpCode32SimdDupGP : OpCode32, IOpCode32Simd
     {
-        public int Size { get; private set; }
-        public int Vd { get; private set; }
-        public int Rt { get; private set; }
-        public bool Q { get; private set; }
+        public int Size { get; }
+        public int Vd { get; }
+        public int Rt { get; }
+        public bool Q { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdDupGP(inst, address, opCode);
 
         public OpCode32SimdDupGP(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32SimdExt.cs

@@ -2,7 +2,9 @@
 {
     class OpCode32SimdExt : OpCode32SimdReg
     {
-        public int Immediate { get; private set; }
+        public int Immediate { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdExt(inst, address, opCode);
 
         public OpCode32SimdExt(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32SimdImm.cs

@@ -2,15 +2,17 @@
 {
     class OpCode32SimdImm : OpCode32SimdBase, IOpCode32SimdImm
     {
-        public bool Q { get; private set; }
-        public long Immediate { get; private set; }
+        public bool Q { get; }
+        public long Immediate { get; }
         public int Elems => GetBytesCount() >> Size;
 
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdImm(inst, address, opCode);
+
         public OpCode32SimdImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Vd = (opCode >> 12) & 0xf;
             Vd |= (opCode >> 18) & 0x10;
-            
+
             Q = ((opCode >> 6) & 0x1) > 0;
 
             int cMode = (opCode >> 8) & 0xf;

ARMeilleure/Decoders/OpCode32SimdImm44.cs

@@ -2,17 +2,19 @@
 {
     class OpCode32SimdImm44 : OpCode32, IOpCode32SimdImm
     {
-        public int Vd { get; private set; }
-        public long Immediate { get; private set; }
-        public int Size { get; private set; }
-        public int Elems { get; private set; }
+        public int Vd { get; }
+        public long Immediate { get; }
+        public int Size { get; }
+        public int Elems { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdImm44(inst, address, opCode);
 
         public OpCode32SimdImm44(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Size = (opCode >> 8) & 0x3;
 
             bool single = Size != 3;
-            
+
             if (single)
             {
                 Vd = ((opCode >> 22) & 0x1) | ((opCode >> 11) & 0x1e);

ARMeilleure/Decoders/OpCode32SimdLong.cs

@@ -2,7 +2,9 @@
 {
     class OpCode32SimdLong : OpCode32SimdBase
     {
-        public bool U { get; private set; }
+        public bool U { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdLong(inst, address, opCode);
 
         public OpCode32SimdLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32SimdMemImm.cs

@@ -2,11 +2,13 @@
 {
     class OpCode32SimdMemImm : OpCode32, IOpCode32Simd
     {
-        public int Vd { get; private set; }
-        public int Rn { get; private set; }
-        public int Size { get; private set; }
-        public bool Add { get; private set; }
-        public int Immediate { get; private set; }
+        public int Vd { get; }
+        public int Rn { get; }
+        public int Size { get; }
+        public bool Add { get; }
+        public int Immediate { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemImm(inst, address, opCode);
 
         public OpCode32SimdMemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32SimdMemMult.cs

@@ -2,15 +2,17 @@
 {
     class OpCode32SimdMemMult : OpCode32
     {
-        public int Rn { get; private set; }
-        public int Vd { get; private set; }
+        public int Rn { get; }
+        public int Vd { get; }
 
-        public int RegisterRange { get; private set; }
-        public int Offset { get; private set; }
-        public int PostOffset { get; private set; }
-        public bool IsLoad { get; private set; }
-        public bool DoubleWidth { get; private set; }
-        public bool Add { get; private set; }
+        public int RegisterRange { get; }
+        public int Offset { get; }
+        public int PostOffset { get; }
+        public bool IsLoad { get; }
+        public bool DoubleWidth { get; }
+        public bool Add { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemMult(inst, address, opCode);
 
         public OpCode32SimdMemMult(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32SimdMemPair.cs

@@ -10,19 +10,21 @@ namespace ARMeilleure.Decoders
             1, 1, 4, 2,
             1, 1, 3, 1,
             1, 1, 2, 1,
-            1, 1, 1, 1 
+            1, 1, 1, 1
         };
 
-        public int Vd { get; private set; }
-        public int Rn { get; private set; }
-        public int Rm { get; private set; }
-        public int Align { get; private set; }
-        public bool WBack { get; private set; }
-        public bool RegisterIndex { get; private set; }
-        public int Size { get; private set; }
+        public int Vd { get; }
+        public int Rn { get; }
+        public int Rm { get; }
+        public int Align { get; }
+        public bool WBack { get; }
+        public bool RegisterIndex { get; }
+        public int Size { get; }
         public int Elems => 8 >> Size;
-        public int Regs { get; private set; }
-        public int Increment { get; private set; }
+        public int Regs { get; }
+        public int Increment { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemPair(inst, address, opCode);
 
         public OpCode32SimdMemPair(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32SimdMemSingle.cs

@@ -4,16 +4,18 @@ namespace ARMeilleure.Decoders
 {
     class OpCode32SimdMemSingle : OpCode32, IOpCode32Simd
     {
-        public int Vd { get; private set; }
-        public int Rn { get; private set; }
-        public int Rm { get; private set; }
-        public int IndexAlign { get; private set; }
-        public int Index { get; private set; }
-        public bool WBack { get; private set; }
-        public bool RegisterIndex { get; private set; }
-        public int Size { get; private set; }
-        public bool Replicate { get; private set; }
-        public int Increment { get; private set; }
+        public int Vd { get; }
+        public int Rn { get; }
+        public int Rm { get; }
+        public int IndexAlign { get; }
+        public int Index { get; }
+        public bool WBack { get; }
+        public bool RegisterIndex { get; }
+        public int Size { get; }
+        public bool Replicate { get; }
+        public int Increment { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemSingle(inst, address, opCode);
 
         public OpCode32SimdMemSingle(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
@@ -29,8 +31,8 @@ namespace ARMeilleure.Decoders
                 Size = (opCode >> 6) & 0x3;
                 Increment = ((opCode >> 5) & 1) + 1;
                 Index = 0;
-            } 
-            else 
+            }
+            else
             {
                 Increment = (((IndexAlign >> Size) & 1) == 0) ? 1 : 2;
                 Index = IndexAlign >> (1 + Size);

ARMeilleure/Decoders/OpCode32SimdMovGp.cs

@@ -4,12 +4,14 @@
     {
         public int Size => 2;
 
-        public int Vn { get; private set; }
-        public int Rt { get; private set; }
-        public int Op { get; private set; }
+        public int Vn { get; }
+        public int Rt { get; }
+        public int Op { get; }
 
-        public int Opc1 { get; private set; }
-        public int Opc2 { get; private set; }
+        public int Opc1 { get; }
+        public int Opc2 { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGp(inst, address, opCode);
 
         public OpCode32SimdMovGp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32SimdMovGpDouble.cs

@@ -4,16 +4,18 @@
     {
         public int Size => 3;
 
-        public int Vm { get; private set; }
-        public int Rt { get; private set; }
-        public int Rt2 { get; private set; }
-        public int Op { get; private set; }
+        public int Vm { get; }
+        public int Rt { get; }
+        public int Rt2 { get; }
+        public int Op { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGpDouble(inst, address, opCode);
 
         public OpCode32SimdMovGpDouble(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             // Which one is used is instruction dependant.
             Op = (opCode >> 20) & 0x1;
-            
+
             Rt = (opCode >> 12) & 0xf;
             Rt2 = (opCode >> 16) & 0xf;
 
@@ -21,7 +23,7 @@
             if (single)
             {
                 Vm = ((opCode >> 5) & 0x1) | ((opCode << 1) & 0x1e);
-            } 
+            }
             else
             {
                 Vm = ((opCode >> 1) & 0x10) | ((opCode >> 0) & 0xf);

ARMeilleure/Decoders/OpCode32SimdMovGpElem.cs

@@ -2,14 +2,16 @@
 {
     class OpCode32SimdMovGpElem : OpCode32, IOpCode32Simd
     {
-        public int Size { get; private set; }
+        public int Size { get; }
 
-        public int Vd { get; private set; }
-        public int Rt { get; private set; }
-        public int Op { get; private set; }
-        public bool U { get; private set; }
+        public int Vd { get; }
+        public int Rt { get; }
+        public int Op { get; }
+        public bool U { get; }
 
-        public int Index { get; private set; }
+        public int Index { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGpElem(inst, address, opCode);
 
         public OpCode32SimdMovGpElem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
@@ -22,7 +24,7 @@
             {
                 Size = 0;
                 Index = opc & 0x7;
-            } 
+            }
             else if ((opc & 0b01001) == 0b00001)
             {
                 Size = 1;
@@ -32,7 +34,7 @@
             {
                 Size = 2;
                 Index = (opc >> 2) & 0x1;
-            } 
+            }
             else
             {
                 Instruction = InstDescriptor.Undefined;

ARMeilleure/Decoders/OpCode32SimdReg.cs

@@ -2,12 +2,14 @@
 {
     class OpCode32SimdReg : OpCode32Simd
     {
-        public int Vn { get; private set; }
+        public int Vn { get; }
 
         public int Qn => GetQuadwordIndex(Vn);
         public int In => GetQuadwordSubindex(Vn) << (3 - Size);
         public int Fn => GetQuadwordSubindex(Vn) << (1 - (Size & 1));
 
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdReg(inst, address, opCode);
+
         public OpCode32SimdReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Vn = ((opCode >> 3) & 0x10) | ((opCode >> 16) & 0xf);

ARMeilleure/Decoders/OpCode32SimdRegElem.cs

@@ -2,6 +2,8 @@
 {
     class OpCode32SimdRegElem : OpCode32SimdReg
     {
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegElem(inst, address, opCode);
+
         public OpCode32SimdRegElem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Q = ((opCode >> 24) & 0x1) != 0;

ARMeilleure/Decoders/OpCode32SimdRegElemLong.cs

@@ -2,6 +2,8 @@
 {
     class OpCode32SimdRegElemLong : OpCode32SimdRegElem
     {
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegElemLong(inst, address, opCode);
+
         public OpCode32SimdRegElemLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Q = false;

ARMeilleure/Decoders/OpCode32SimdRegLong.cs

@@ -2,7 +2,9 @@
 {
     class OpCode32SimdRegLong : OpCode32SimdReg
     {
-        public bool Polynomial { get; private set; }
+        public bool Polynomial { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegLong(inst, address, opCode);
 
         public OpCode32SimdRegLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32SimdRegS.cs

@@ -2,7 +2,9 @@
 {
     class OpCode32SimdRegS : OpCode32SimdS
     {
-        public int Vn { get; private set; }
+        public int Vn { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegS(inst, address, opCode);
 
         public OpCode32SimdRegS(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
@@ -10,7 +12,7 @@
             if (single)
             {
                 Vn = ((opCode >> 7) & 0x1) | ((opCode >> 15) & 0x1e);
-            } 
+            }
             else
             {
                 Vn = ((opCode >> 3) & 0x10) | ((opCode >> 16) & 0xf);

ARMeilleure/Decoders/OpCode32SimdRegWide.cs

@@ -2,6 +2,8 @@
 {
     class OpCode32SimdRegWide : OpCode32SimdReg
     {
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegWide(inst, address, opCode);
+
         public OpCode32SimdRegWide(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Q = false;

ARMeilleure/Decoders/OpCode32SimdRev.cs

@@ -2,6 +2,8 @@
 {
     class OpCode32SimdRev : OpCode32SimdCmpZ
     {
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRev(inst, address, opCode);
+
         public OpCode32SimdRev(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             if (Opc + Size >= 3)

ARMeilleure/Decoders/OpCode32SimdS.cs

@@ -5,9 +5,11 @@
         public int Vd { get; protected set; }
         public int Vm { get; protected set; }
         public int Opc { get; protected set; } // "with_zero" (Opc<1>) [Vcmp, Vcmpe].
-        public int Opc2 { get; private set; } // opc2 or RM (opc2<1:0>) [Vcvt, Vrint].
+        public int Opc2 { get; } // opc2 or RM (opc2<1:0>) [Vcvt, Vrint].
         public int Size { get; protected set; }
 
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdS(inst, address, opCode);
+
         public OpCode32SimdS(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Opc = (opCode >> 15) & 0x3;

ARMeilleure/Decoders/OpCode32SimdSel.cs

@@ -2,7 +2,9 @@
 {
     class OpCode32SimdSel : OpCode32SimdRegS
     {
-        public OpCode32SimdSelMode Cc { get; private set; }
+        public OpCode32SimdSelMode Cc { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSel(inst, address, opCode);
 
         public OpCode32SimdSel(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32SimdShImm.cs

@@ -2,7 +2,9 @@
 {
     class OpCode32SimdShImm : OpCode32Simd
     {
-        public int Shift { get; private set; }
+        public int Shift { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImm(inst, address, opCode);
 
         public OpCode32SimdShImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32SimdShImmLong.cs

@@ -2,7 +2,9 @@
 {
     class OpCode32SimdShImmLong : OpCode32Simd
     {
-        public int Shift { get; private set; }
+        public int Shift { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImmLong(inst, address, opCode);
 
         public OpCode32SimdShImmLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32SimdShImmNarrow.cs

@@ -2,6 +2,8 @@
 {
     class OpCode32SimdShImmNarrow : OpCode32SimdShImm
     {
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImmNarrow(inst, address, opCode);
+
         public OpCode32SimdShImmNarrow(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
     }
 }

ARMeilleure/Decoders/OpCode32SimdSpecial.cs

@@ -2,8 +2,10 @@
 {
     class OpCode32SimdSpecial : OpCode32
     {
-        public int Rt { get; private set; }
-        public int Sreg { get; private set; }
+        public int Rt { get; }
+        public int Sreg { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSpecial(inst, address, opCode);
 
         public OpCode32SimdSpecial(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32SimdSqrte.cs

@@ -2,6 +2,8 @@
 {
     class OpCode32SimdSqrte : OpCode32Simd
     {
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSqrte(inst, address, opCode);
+
         public OpCode32SimdSqrte(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Size = (opCode >> 18) & 0x1;

ARMeilleure/Decoders/OpCode32SimdTbl.cs

@@ -2,7 +2,9 @@
 {
     class OpCode32SimdTbl : OpCode32SimdReg
     {
-        public int Length { get; private set; }
+        public int Length { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdTbl(inst, address, opCode);
 
         public OpCode32SimdTbl(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCode32System.cs

@@ -2,14 +2,16 @@
 {
     class OpCode32System : OpCode32
     {
-        public int Opc1 { get; private set; }
-        public int CRn { get; private set; }
-        public int Rt { get; private set; }
-        public int Opc2 { get; private set; }
-        public int CRm { get; private set; }
-        public int MrrcOp { get; private set; }
+        public int Opc1 { get; }
+        public int CRn { get; }
+        public int Rt { get; }
+        public int Opc2 { get; }
+        public int CRm { get; }
+        public int MrrcOp { get; }
 
-        public int Coproc { get; private set; }
+        public int Coproc { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32System(inst, address, opCode);
 
         public OpCode32System(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCodeAdr.cs

@@ -2,11 +2,13 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeAdr : OpCode
     {
-        public int Rd { get; private set; }
+        public int Rd { get; }
 
-        public long Immediate { get; private set; }
+        public long Immediate { get; }
 
-         public OpCodeAdr(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+         public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAdr(inst, address, opCode);
+
+        public OpCodeAdr(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Rd = opCode & 0x1f;
 

ARMeilleure/Decoders/OpCodeAlu.cs

@@ -3,9 +3,11 @@ namespace ARMeilleure.Decoders
     class OpCodeAlu : OpCode, IOpCodeAlu
     {
         public int Rd { get; protected set; }
-        public int Rn { get; private   set; }
+        public int Rn { get; }
 
-        public DataOp DataOp { get; private set; }
+        public DataOp DataOp { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAlu(inst, address, opCode);
 
         public OpCodeAlu(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCodeAluBinary.cs

@@ -2,7 +2,9 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeAluBinary : OpCodeAlu
     {
-        public int Rm { get; private set; }
+        public int Rm { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAluBinary(inst, address, opCode);
 
         public OpCodeAluBinary(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCodeAluImm.cs

@@ -4,7 +4,9 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeAluImm : OpCodeAlu, IOpCodeAluImm
     {
-        public long Immediate { get; private set; }
+        public long Immediate { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAluImm(inst, address, opCode);
 
         public OpCodeAluImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCodeAluRs.cs

@@ -2,10 +2,12 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeAluRs : OpCodeAlu, IOpCodeAluRs
     {
-        public int Shift { get; private set; }
-        public int Rm    { get; private set; }
+        public int Shift { get; }
+        public int Rm    { get; }
 
-        public ShiftType ShiftType { get; private set; }
+        public ShiftType ShiftType { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAluRs(inst, address, opCode);
 
         public OpCodeAluRs(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCodeAluRx.cs

@@ -2,10 +2,12 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeAluRx : OpCodeAlu, IOpCodeAluRx
     {
-        public int Shift { get; private set; }
-        public int Rm    { get; private set; }
+        public int Shift { get; }
+        public int Rm    { get; }
 
-        public IntType IntType { get; private set; }
+        public IntType IntType { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAluRx(inst, address, opCode);
 
         public OpCodeAluRx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCodeBImm.cs

@@ -4,6 +4,8 @@ namespace ARMeilleure.Decoders
     {
         public long Immediate { get; protected set; }
 
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImm(inst, address, opCode);
+
         public OpCodeBImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
     }
 }

ARMeilleure/Decoders/OpCodeBImmAl.cs

@@ -2,6 +2,8 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeBImmAl : OpCodeBImm
     {
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImmAl(inst, address, opCode);
+
         public OpCodeBImmAl(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Immediate = (long)address + DecoderHelper.DecodeImm26_2(opCode);

ARMeilleure/Decoders/OpCodeBImmCmp.cs

@@ -2,7 +2,9 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeBImmCmp : OpCodeBImm
     {
-        public int Rt { get; private set; }
+        public int Rt { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImmCmp(inst, address, opCode);
 
         public OpCodeBImmCmp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCodeBImmCond.cs

@@ -2,7 +2,9 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeBImmCond : OpCodeBImm, IOpCodeCond
     {
-        public Condition Cond { get; private set; }
+        public Condition Cond { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImmCond(inst, address, opCode);
 
         public OpCodeBImmCond(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCodeBImmTest.cs

@@ -2,8 +2,10 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeBImmTest : OpCodeBImm
     {
-        public int Rt  { get; private set; }
-        public int Bit { get; private set; }
+        public int Rt  { get; }
+        public int Bit { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImmTest(inst, address, opCode);
 
         public OpCodeBImmTest(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCodeBReg.cs

@@ -2,7 +2,9 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeBReg : OpCode
     {
-        public int Rn { get; private set; }
+        public int Rn { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBReg(inst, address, opCode);
 
         public OpCodeBReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCodeBfm.cs

@@ -2,10 +2,12 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeBfm : OpCodeAlu
     {
-        public long WMask { get; private set; }
-        public long TMask { get; private set; }
-        public int  Pos   { get; private set; }
-        public int  Shift { get; private set; }
+        public long WMask { get; }
+        public long TMask { get; }
+        public int  Pos   { get; }
+        public int  Shift { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBfm(inst, address, opCode);
 
         public OpCodeBfm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCodeCcmp.cs

@@ -4,10 +4,12 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeCcmp : OpCodeAlu, IOpCodeCond
     {
-        public    int Nzcv { get; private set; }
+        public    int Nzcv { get; }
         protected int RmImm;
 
-        public Condition Cond { get; private set; }
+        public Condition Cond { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeCcmp(inst, address, opCode);
 
         public OpCodeCcmp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCodeCcmpImm.cs

@@ -4,6 +4,8 @@ namespace ARMeilleure.Decoders
     {
         public long Immediate => RmImm;
 
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeCcmpImm(inst, address, opCode);
+
         public OpCodeCcmpImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
     }
 }

ARMeilleure/Decoders/OpCodeCcmpReg.cs

@@ -8,6 +8,8 @@ namespace ARMeilleure.Decoders
 
         public ShiftType ShiftType => ShiftType.Lsl;
 
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeCcmpReg(inst, address, opCode);
+
         public OpCodeCcmpReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
     }
 }

ARMeilleure/Decoders/OpCodeCsel.cs

@@ -2,9 +2,11 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeCsel : OpCodeAlu, IOpCodeCond
     {
-        public int Rm { get; private set; }
+        public int Rm { get; }
 
-        public Condition Cond { get; private set; }
+        public Condition Cond { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeCsel(inst, address, opCode);
 
         public OpCodeCsel(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCodeException.cs

@@ -2,7 +2,9 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeException : OpCode
     {
-        public int Id { get; private set; }
+        public int Id { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeException(inst, address, opCode);
 
         public OpCodeException(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCodeMem.cs

@@ -7,6 +7,8 @@ namespace ARMeilleure.Decoders
         public int  Size     { get; protected set; }
         public bool Extend64 { get; protected set; }
 
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMem(inst, address, opCode);
+
         public OpCodeMem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Rt   = (opCode >>  0) & 0x1f;

ARMeilleure/Decoders/OpCodeMemEx.cs

@@ -2,8 +2,10 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeMemEx : OpCodeMem
     {
-        public int Rt2 { get; private set; }
-        public int Rs  { get; private set; }
+        public int Rt2 { get; }
+        public int Rs  { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemEx(inst, address, opCode);
 
         public OpCodeMemEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCodeMemImm.cs

@@ -5,7 +5,7 @@ namespace ARMeilleure.Decoders
         public    long Immediate { get; protected set; }
         public    bool WBack     { get; protected set; }
         public    bool PostIdx   { get; protected set; }
-        protected bool Unscaled  { get; private   set; }
+        protected bool Unscaled  { get; }
 
         private enum MemOp
         {
@@ -16,6 +16,8 @@ namespace ARMeilleure.Decoders
             Unsigned
         }
 
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemImm(inst, address, opCode);
+
         public OpCodeMemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Extend64 = ((opCode >> 22) & 3) == 2;

ARMeilleure/Decoders/OpCodeMemLit.cs

@@ -2,11 +2,13 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeMemLit : OpCode, IOpCodeLit
     {
-        public int  Rt        { get; private set; }
-        public long Immediate { get; private set; }
-        public int  Size      { get; private set; }
-        public bool Signed    { get; private set; }
-        public bool Prefetch  { get; private set; }
+        public int  Rt        { get; }
+        public long Immediate { get; }
+        public int  Size      { get; }
+        public bool Signed    { get; }
+        public bool Prefetch  { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemLit(inst, address, opCode);
 
         public OpCodeMemLit(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCodeMemPair.cs

@@ -2,7 +2,9 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeMemPair : OpCodeMemImm
     {
-        public int Rt2 { get; private set; }
+        public int Rt2 { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemPair(inst, address, opCode);
 
         public OpCodeMemPair(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCodeMemReg.cs

@@ -2,10 +2,12 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeMemReg : OpCodeMem
     {
-        public bool Shift { get; private set; }
-        public int  Rm    { get; private set; }
+        public bool Shift { get; }
+        public int  Rm    { get; }
 
-        public IntType IntType { get; private set; }
+        public IntType IntType { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemReg(inst, address, opCode);
 
         public OpCodeMemReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCodeMov.cs

@@ -2,11 +2,13 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeMov : OpCode
     {
-        public int Rd { get; private set; }
+        public int Rd { get; }
 
-        public long Immediate { get; private set; }
+        public long Immediate { get; }
 
-        public int Bit { get; private set; }
+        public int Bit { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMov(inst, address, opCode);
 
         public OpCodeMov(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCodeMul.cs

@@ -2,8 +2,10 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeMul : OpCodeAlu
     {
-        public int Rm { get; private set; }
-        public int Ra { get; private set; }
+        public int Rm { get; }
+        public int Ra { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMul(inst, address, opCode);
 
         public OpCodeMul(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCodeSimd.cs

@@ -2,11 +2,13 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeSimd : OpCode, IOpCodeSimd
     {
-        public int Rd   { get; private   set; }
-        public int Rn   { get; private   set; }
-        public int Opc  { get; private   set; }
+        public int Rd   { get; }
+        public int Rn   { get; }
+        public int Opc  { get; }
         public int Size { get; protected set; }
 
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimd(inst, address, opCode);
+
         public OpCodeSimd(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Rd   = (opCode >>  0) & 0x1f;

ARMeilleure/Decoders/OpCodeSimdCvt.cs

@@ -2,7 +2,9 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeSimdCvt : OpCodeSimd
     {
-        public int FBits { get; private set; }
+        public int FBits { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdCvt(inst, address, opCode);
 
         public OpCodeSimdCvt(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCodeSimdExt.cs

@@ -2,7 +2,9 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeSimdExt : OpCodeSimdReg
     {
-        public int Imm4 { get; private set; }
+        public int Imm4 { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdExt(inst, address, opCode);
 
         public OpCodeSimdExt(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCodeSimdFcond.cs

@@ -2,9 +2,11 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeSimdFcond : OpCodeSimdReg, IOpCodeCond
     {
-        public int Nzcv { get; private set; }
+        public int Nzcv { get; }
 
-        public Condition Cond { get; private set; }
+        public Condition Cond { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdFcond(inst, address, opCode);
 
         public OpCodeSimdFcond(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCodeSimdFmov.cs

@@ -2,9 +2,11 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeSimdFmov : OpCode, IOpCodeSimd
     {
-        public int  Rd        { get; private set; }
-        public long Immediate { get; private set; }
-        public int  Size      { get; private set; }
+        public int  Rd        { get; }
+        public long Immediate { get; }
+        public int  Size      { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdFmov(inst, address, opCode);
 
         public OpCodeSimdFmov(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCodeSimdImm.cs

@@ -2,9 +2,11 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeSimdImm : OpCode, IOpCodeSimd
     {
-        public int  Rd        { get; private set; }
-        public long Immediate { get; private set; }
-        public int  Size      { get; private set; }
+        public int  Rd        { get; }
+        public long Immediate { get; }
+        public int  Size      { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdImm(inst, address, opCode);
 
         public OpCodeSimdImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCodeSimdIns.cs

@@ -2,8 +2,10 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeSimdIns : OpCodeSimd
     {
-        public int SrcIndex { get; private set; }
-        public int DstIndex { get; private set; }
+        public int SrcIndex { get; }
+        public int DstIndex { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdIns(inst, address, opCode);
 
         public OpCodeSimdIns(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCodeSimdMemImm.cs

@@ -2,6 +2,8 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeSimdMemImm : OpCodeMemImm, IOpCodeSimd
     {
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemImm(inst, address, opCode);
+
         public OpCodeSimdMemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Size |= (opCode >> 21) & 4;

ARMeilleure/Decoders/OpCodeSimdMemLit.cs

@@ -2,12 +2,14 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeSimdMemLit : OpCode, IOpCodeSimd, IOpCodeLit
     {
-        public int  Rt        { get; private set; }
-        public long Immediate { get; private set; }
-        public int  Size      { get; private set; }
+        public int  Rt        { get; }
+        public long Immediate { get; }
+        public int  Size      { get; }
         public bool Signed   => false;
         public bool Prefetch => false;
 
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemLit(inst, address, opCode);
+
         public OpCodeSimdMemLit(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             int opc = (opCode >> 30) & 3;

ARMeilleure/Decoders/OpCodeSimdMemMs.cs

@@ -2,10 +2,12 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeSimdMemMs : OpCodeMemReg, IOpCodeSimd
     {
-        public int  Reps   { get; private set; }
-        public int  SElems { get; private set; }
-        public int  Elems  { get; private set; }
-        public bool WBack  { get; private set; }
+        public int  Reps   { get; }
+        public int  SElems { get; }
+        public int  Elems  { get; }
+        public bool WBack  { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemMs(inst, address, opCode);
 
         public OpCodeSimdMemMs(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {

ARMeilleure/Decoders/OpCodeSimdMemPair.cs

@@ -2,6 +2,8 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeSimdMemPair : OpCodeMemPair, IOpCodeSimd
     {
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemPair(inst, address, opCode);
+
         public OpCodeSimdMemPair(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Size = ((opCode >> 30) & 3) + 2;

ARMeilleure/Decoders/OpCodeSimdMemReg.cs

@@ -2,6 +2,8 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeSimdMemReg : OpCodeMemReg, IOpCodeSimd
     {
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemReg(inst, address, opCode);
+
         public OpCodeSimdMemReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Size |= (opCode >> 21) & 4;

ARMeilleure/Decoders/OpCodeSimdMemSs.cs

@@ -2,10 +2,12 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeSimdMemSs : OpCodeMemReg, IOpCodeSimd
     {
-        public int  SElems    { get; private set; }
-        public int  Index     { get; private set; }
-        public bool Replicate { get; private set; }
-        public bool WBack     { get; private set; }
+        public int  SElems    { get; }
+        public int  Index     { get; }
+        public bool Replicate { get; }
+        public bool WBack     { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemSs(inst, address, opCode);
 
         public OpCodeSimdMemSs(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {