LDj3SNuD dc0adb533d PPTC & Pool Enhancements. (#1968) %!s(int64=5) %!d(string=hai) anos
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Aarch32Mode.cs a731ab3a2a Add a new JIT compiler for CPU code (#693) %!s(int64=6) %!d(string=hai) anos
ExecutionContext.cs cf6cd71488 IPC refactor part 2: Use ReplyAndReceive on HLE services and remove special handling from kernel (#1458) %!s(int64=5) %!d(string=hai) anos
ExecutionMode.cs dc0adb533d PPTC & Pool Enhancements. (#1968) %!s(int64=5) %!d(string=hai) anos
FPCR.cs e36e97c64d CPU: This PR fixes Fpscr, among other things. (#1433) %!s(int64=5) %!d(string=hai) anos
FPException.cs a731ab3a2a Add a new JIT compiler for CPU code (#693) %!s(int64=6) %!d(string=hai) anos
FPRoundingMode.cs a731ab3a2a Add a new JIT compiler for CPU code (#693) %!s(int64=6) %!d(string=hai) anos
FPSR.cs e36e97c64d CPU: This PR fixes Fpscr, among other things. (#1433) %!s(int64=5) %!d(string=hai) anos
FPState.cs e36e97c64d CPU: This PR fixes Fpscr, among other things. (#1433) %!s(int64=5) %!d(string=hai) anos
FPType.cs a731ab3a2a Add a new JIT compiler for CPU code (#693) %!s(int64=6) %!d(string=hai) anos
InstExceptionEventArgs.cs a731ab3a2a Add a new JIT compiler for CPU code (#693) %!s(int64=6) %!d(string=hai) anos
InstUndefinedEventArgs.cs a731ab3a2a Add a new JIT compiler for CPU code (#693) %!s(int64=6) %!d(string=hai) anos
NativeContext.cs 9878fc2d3c Implement inline memory load/store exclusive and ordered (#1413) %!s(int64=5) %!d(string=hai) anos
PState.cs e36e97c64d CPU: This PR fixes Fpscr, among other things. (#1433) %!s(int64=5) %!d(string=hai) anos
RegisterAlias.cs b1b6f294f2 Add most of the A32 instruction set to ARMeilleure (#897) %!s(int64=6) %!d(string=hai) anos
RegisterConsts.cs b1b6f294f2 Add most of the A32 instruction set to ARMeilleure (#897) %!s(int64=6) %!d(string=hai) anos
V128.cs 430ba6da65 CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817) %!s(int64=5) %!d(string=hai) anos