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Cache
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b5c215111d
PPTC Follow-up. (#1712)
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5 år sedan |
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PTC
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dcce407071
Lower precision of estimate instruction results to match Arm behavior (#1943)
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5 år sedan |
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ArmEmitterContext.cs
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61634dd415
Clear JIT cache on exit (#1518)
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5 år sedan |
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Compiler.cs
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61634dd415
Clear JIT cache on exit (#1518)
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5 år sedan |
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CompilerContext.cs
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a731ab3a2a
Add a new JIT compiler for CPU code (#693)
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6 år sedan |
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CompilerOptions.cs
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a731ab3a2a
Add a new JIT compiler for CPU code (#693)
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6 år sedan |
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ControlFlowGraph.cs
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f60033e0aa
Implement block placement (#1549)
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5 år sedan |
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DelegateHelper.cs
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5e724cf24e
Add Profiled Persistent Translation Cache. (#769)
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5 år sedan |
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DelegateInfo.cs
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b5c215111d
PPTC Follow-up. (#1712)
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5 år sedan |
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Delegates.cs
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430ba6da65
CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)
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5 år sedan |
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DirectCallStubs.cs
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68f6b79fd3
Add a simple Pools Limiter. (#1830)
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5 år sedan |
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Dominance.cs
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e5f78fb1d4
Replace LinkedList by IntrusiveList to avoid allocations on JIT (#931)
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6 år sedan |
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EmitterContext.cs
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567ea726e1
Add support for guest Fz (Fpcr) mode through host Ftz and Daz (Mxcsr) modes (fast paths). (#1630)
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5 år sedan |
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GuestFunction.cs
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a731ab3a2a
Add a new JIT compiler for CPU code (#693)
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6 år sedan |
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JumpTableEntryAllocator.cs
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b5c215111d
PPTC Follow-up. (#1712)
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5 år sedan |
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RegisterToLocal.cs
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e5f78fb1d4
Replace LinkedList by IntrusiveList to avoid allocations on JIT (#931)
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6 år sedan |
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RegisterUsage.cs
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f2b12c9749
Remove old, unused CPU optimization (#1586)
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5 år sedan |
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RejitRequest.cs
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5e724cf24e
Add Profiled Persistent Translation Cache. (#769)
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5 år sedan |
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SsaConstruction.cs
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b1b6f294f2
Add most of the A32 instruction set to ARMeilleure (#897)
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6 år sedan |
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SsaDeconstruction.cs
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b5c215111d
PPTC Follow-up. (#1712)
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5 år sedan |
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TranslatedFunction.cs
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61634dd415
Clear JIT cache on exit (#1518)
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5 år sedan |
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Translator.cs
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68f6b79fd3
Add a simple Pools Limiter. (#1830)
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5 år sedan |
gdkchan
dcce407071
Lower precision of estimate instruction results to match Arm behavior (#1943)