InstEmitSimdCvt.cs 57 KB

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  1. using ARMeilleure.Decoders;
  2. using ARMeilleure.IntermediateRepresentation;
  3. using ARMeilleure.State;
  4. using ARMeilleure.Translation;
  5. using System;
  6. using System.Diagnostics;
  7. using System.Reflection;
  8. using static ARMeilleure.Instructions.InstEmitHelper;
  9. using static ARMeilleure.Instructions.InstEmitSimdHelper;
  10. using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
  11. namespace ARMeilleure.Instructions
  12. {
  13. using Func1I = Func<Operand, Operand>;
  14. static partial class InstEmit
  15. {
  16. public static void Fcvt_S(ArmEmitterContext context)
  17. {
  18. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  19. if (op.Size == 0 && op.Opc == 1) // Single -> Double.
  20. {
  21. if (Optimizations.UseSse2)
  22. {
  23. Operand n = GetVec(op.Rn);
  24. Operand res = context.AddIntrinsic(Intrinsic.X86Cvtss2sd, context.VectorZero(), n);
  25. context.Copy(GetVec(op.Rd), res);
  26. }
  27. else
  28. {
  29. Operand ne = context.VectorExtract(OperandType.FP32, GetVec(op.Rn), 0);
  30. Operand res = context.ConvertToFP(OperandType.FP64, ne);
  31. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  32. }
  33. }
  34. else if (op.Size == 1 && op.Opc == 0) // Double -> Single.
  35. {
  36. if (Optimizations.UseSse2)
  37. {
  38. Operand n = GetVec(op.Rn);
  39. Operand res = context.AddIntrinsic(Intrinsic.X86Cvtsd2ss, context.VectorZero(), n);
  40. context.Copy(GetVec(op.Rd), res);
  41. }
  42. else
  43. {
  44. Operand ne = context.VectorExtract(OperandType.FP64, GetVec(op.Rn), 0);
  45. Operand res = context.ConvertToFP(OperandType.FP32, ne);
  46. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  47. }
  48. }
  49. else if (op.Size == 0 && op.Opc == 3) // Single -> Half.
  50. {
  51. if (Optimizations.UseF16c)
  52. {
  53. Debug.Assert(!Optimizations.ForceLegacySse);
  54. Operand n = GetVec(op.Rn);
  55. Operand res = context.AddIntrinsic(Intrinsic.X86Vcvtps2ph, n, Const(X86GetRoundControl(FPRoundingMode.ToNearest)));
  56. res = context.AddIntrinsic(Intrinsic.X86Pslldq, res, Const(14)); // VectorZeroUpper112()
  57. res = context.AddIntrinsic(Intrinsic.X86Psrldq, res, Const(14));
  58. context.Copy(GetVec(op.Rd), res);
  59. }
  60. else
  61. {
  62. Operand ne = context.VectorExtract(OperandType.FP32, GetVec(op.Rn), 0);
  63. Operand res = context.Call(typeof(SoftFloat32_16).GetMethod(nameof(SoftFloat32_16.FPConvert)), ne);
  64. res = context.ZeroExtend16(OperandType.I64, res);
  65. context.Copy(GetVec(op.Rd), EmitVectorInsert(context, context.VectorZero(), res, 0, 1));
  66. }
  67. }
  68. else if (op.Size == 3 && op.Opc == 0) // Half -> Single.
  69. {
  70. if (Optimizations.UseF16c)
  71. {
  72. Debug.Assert(!Optimizations.ForceLegacySse);
  73. Operand res = context.AddIntrinsic(Intrinsic.X86Vcvtph2ps, GetVec(op.Rn));
  74. res = context.VectorZeroUpper96(res);
  75. context.Copy(GetVec(op.Rd), res);
  76. }
  77. else
  78. {
  79. Operand ne = EmitVectorExtractZx(context, op.Rn, 0, 1);
  80. Operand res = context.Call(typeof(SoftFloat16_32).GetMethod(nameof(SoftFloat16_32.FPConvert)), ne);
  81. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  82. }
  83. }
  84. else if (op.Size == 1 && op.Opc == 3) // Double -> Half.
  85. {
  86. throw new NotImplementedException("Double-precision to half-precision.");
  87. }
  88. else if (op.Size == 3 && op.Opc == 1) // Double -> Half.
  89. {
  90. throw new NotImplementedException("Half-precision to double-precision.");
  91. }
  92. else // Invalid encoding.
  93. {
  94. Debug.Assert(false, $"type == {op.Size} && opc == {op.Opc}");
  95. }
  96. }
  97. public static void Fcvtas_Gp(ArmEmitterContext context)
  98. {
  99. EmitFcvt_s_Gp(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1));
  100. }
  101. public static void Fcvtas_S(ArmEmitterContext context)
  102. {
  103. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1), signed: true, scalar: true);
  104. }
  105. public static void Fcvtas_V(ArmEmitterContext context)
  106. {
  107. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1), signed: true, scalar: false);
  108. }
  109. public static void Fcvtau_Gp(ArmEmitterContext context)
  110. {
  111. EmitFcvt_u_Gp(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1));
  112. }
  113. public static void Fcvtau_S(ArmEmitterContext context)
  114. {
  115. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1), signed: false, scalar: true);
  116. }
  117. public static void Fcvtau_V(ArmEmitterContext context)
  118. {
  119. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1), signed: false, scalar: false);
  120. }
  121. public static void Fcvtl_V(ArmEmitterContext context)
  122. {
  123. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  124. int sizeF = op.Size & 1;
  125. if (Optimizations.UseSse2 && sizeF == 1)
  126. {
  127. Operand n = GetVec(op.Rn);
  128. Operand res = op.RegisterSize == RegisterSize.Simd128 ? context.AddIntrinsic(Intrinsic.X86Movhlps, n, n) : n;
  129. res = context.AddIntrinsic(Intrinsic.X86Cvtps2pd, res);
  130. context.Copy(GetVec(op.Rd), res);
  131. }
  132. else if (Optimizations.UseF16c && sizeF == 0)
  133. {
  134. Debug.Assert(!Optimizations.ForceLegacySse);
  135. Operand n = GetVec(op.Rn);
  136. Operand res = op.RegisterSize == RegisterSize.Simd128 ? context.AddIntrinsic(Intrinsic.X86Movhlps, n, n) : n;
  137. res = context.AddIntrinsic(Intrinsic.X86Vcvtph2ps, res);
  138. context.Copy(GetVec(op.Rd), res);
  139. }
  140. else
  141. {
  142. Operand res = context.VectorZero();
  143. int elems = 4 >> sizeF;
  144. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  145. for (int index = 0; index < elems; index++)
  146. {
  147. if (sizeF == 0)
  148. {
  149. Operand ne = EmitVectorExtractZx(context, op.Rn, part + index, 1);
  150. Operand e = context.Call(typeof(SoftFloat16_32).GetMethod(nameof(SoftFloat16_32.FPConvert)), ne);
  151. res = context.VectorInsert(res, e, index);
  152. }
  153. else /* if (sizeF == 1) */
  154. {
  155. Operand ne = context.VectorExtract(OperandType.FP32, GetVec(op.Rn), part + index);
  156. Operand e = context.ConvertToFP(OperandType.FP64, ne);
  157. res = context.VectorInsert(res, e, index);
  158. }
  159. }
  160. context.Copy(GetVec(op.Rd), res);
  161. }
  162. }
  163. public static void Fcvtms_Gp(ArmEmitterContext context)
  164. {
  165. if (Optimizations.UseSse41)
  166. {
  167. EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsMinusInfinity, isFixed: false);
  168. }
  169. else
  170. {
  171. EmitFcvt_s_Gp(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Floor), op1));
  172. }
  173. }
  174. public static void Fcvtms_V(ArmEmitterContext context)
  175. {
  176. if (Optimizations.UseSse41)
  177. {
  178. EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsMinusInfinity, scalar: false);
  179. }
  180. else
  181. {
  182. EmitFcvt(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Floor), op1), signed: true, scalar: false);
  183. }
  184. }
  185. public static void Fcvtmu_Gp(ArmEmitterContext context)
  186. {
  187. if (Optimizations.UseSse41)
  188. {
  189. EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsMinusInfinity, isFixed: false);
  190. }
  191. else
  192. {
  193. EmitFcvt_u_Gp(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Floor), op1));
  194. }
  195. }
  196. public static void Fcvtn_V(ArmEmitterContext context)
  197. {
  198. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  199. int sizeF = op.Size & 1;
  200. if (Optimizations.UseSse2 && sizeF == 1)
  201. {
  202. Operand d = GetVec(op.Rd);
  203. Intrinsic movInst = op.RegisterSize == RegisterSize.Simd128 ? Intrinsic.X86Movlhps : Intrinsic.X86Movhlps;
  204. Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtpd2ps, GetVec(op.Rn));
  205. nInt = context.AddIntrinsic(Intrinsic.X86Movlhps, nInt, nInt);
  206. Operand res = context.VectorZeroUpper64(d);
  207. res = context.AddIntrinsic(movInst, res, nInt);
  208. context.Copy(d, res);
  209. }
  210. else if (Optimizations.UseF16c && sizeF == 0)
  211. {
  212. Debug.Assert(!Optimizations.ForceLegacySse);
  213. Operand d = GetVec(op.Rd);
  214. Operand n = GetVec(op.Rn);
  215. Intrinsic movInst = op.RegisterSize == RegisterSize.Simd128 ? Intrinsic.X86Movlhps : Intrinsic.X86Movhlps;
  216. Operand nInt = context.AddIntrinsic(Intrinsic.X86Vcvtps2ph, n, Const(X86GetRoundControl(FPRoundingMode.ToNearest)));
  217. nInt = context.AddIntrinsic(Intrinsic.X86Movlhps, nInt, nInt);
  218. Operand res = context.VectorZeroUpper64(d);
  219. res = context.AddIntrinsic(movInst, res, nInt);
  220. context.Copy(d, res);
  221. }
  222. else
  223. {
  224. OperandType type = sizeF == 0 ? OperandType.FP32 : OperandType.FP64;
  225. int elems = 4 >> sizeF;
  226. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  227. Operand d = GetVec(op.Rd);
  228. Operand res = part == 0 ? context.VectorZero() : context.Copy(d);
  229. for (int index = 0; index < elems; index++)
  230. {
  231. Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
  232. if (sizeF == 0)
  233. {
  234. Operand e = context.Call(typeof(SoftFloat32_16).GetMethod(nameof(SoftFloat32_16.FPConvert)), ne);
  235. e = context.ZeroExtend16(OperandType.I64, e);
  236. res = EmitVectorInsert(context, res, e, part + index, 1);
  237. }
  238. else /* if (sizeF == 1) */
  239. {
  240. Operand e = context.ConvertToFP(OperandType.FP32, ne);
  241. res = context.VectorInsert(res, e, part + index);
  242. }
  243. }
  244. context.Copy(d, res);
  245. }
  246. }
  247. public static void Fcvtns_S(ArmEmitterContext context)
  248. {
  249. if (Optimizations.UseSse41)
  250. {
  251. EmitSse41FcvtsOpF(context, FPRoundingMode.ToNearest, scalar: true);
  252. }
  253. else
  254. {
  255. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1), signed: true, scalar: true);
  256. }
  257. }
  258. public static void Fcvtns_V(ArmEmitterContext context)
  259. {
  260. if (Optimizations.UseSse41)
  261. {
  262. EmitSse41FcvtsOpF(context, FPRoundingMode.ToNearest, scalar: false);
  263. }
  264. else
  265. {
  266. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1), signed: true, scalar: false);
  267. }
  268. }
  269. public static void Fcvtnu_S(ArmEmitterContext context)
  270. {
  271. if (Optimizations.UseSse41)
  272. {
  273. EmitSse41FcvtuOpF(context, FPRoundingMode.ToNearest, scalar: true);
  274. }
  275. else
  276. {
  277. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1), signed: false, scalar: true);
  278. }
  279. }
  280. public static void Fcvtnu_V(ArmEmitterContext context)
  281. {
  282. if (Optimizations.UseSse41)
  283. {
  284. EmitSse41FcvtuOpF(context, FPRoundingMode.ToNearest, scalar: false);
  285. }
  286. else
  287. {
  288. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1), signed: false, scalar: false);
  289. }
  290. }
  291. public static void Fcvtps_Gp(ArmEmitterContext context)
  292. {
  293. if (Optimizations.UseSse41)
  294. {
  295. EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsPlusInfinity, isFixed: false);
  296. }
  297. else
  298. {
  299. EmitFcvt_s_Gp(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Ceiling), op1));
  300. }
  301. }
  302. public static void Fcvtpu_Gp(ArmEmitterContext context)
  303. {
  304. if (Optimizations.UseSse41)
  305. {
  306. EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsPlusInfinity, isFixed: false);
  307. }
  308. else
  309. {
  310. EmitFcvt_u_Gp(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Ceiling), op1));
  311. }
  312. }
  313. public static void Fcvtzs_Gp(ArmEmitterContext context)
  314. {
  315. if (Optimizations.UseSse41)
  316. {
  317. EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsZero, isFixed: false);
  318. }
  319. else
  320. {
  321. EmitFcvt_s_Gp(context, (op1) => op1);
  322. }
  323. }
  324. public static void Fcvtzs_Gp_Fixed(ArmEmitterContext context)
  325. {
  326. if (Optimizations.UseSse41)
  327. {
  328. EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsZero, isFixed: true);
  329. }
  330. else
  331. {
  332. EmitFcvtzs_Gp_Fixed(context);
  333. }
  334. }
  335. public static void Fcvtzs_S(ArmEmitterContext context)
  336. {
  337. if (Optimizations.UseSse41)
  338. {
  339. EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsZero, scalar: true);
  340. }
  341. else
  342. {
  343. EmitFcvtz(context, signed: true, scalar: true);
  344. }
  345. }
  346. public static void Fcvtzs_V(ArmEmitterContext context)
  347. {
  348. if (Optimizations.UseSse41)
  349. {
  350. EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsZero, scalar: false);
  351. }
  352. else
  353. {
  354. EmitFcvtz(context, signed: true, scalar: false);
  355. }
  356. }
  357. public static void Fcvtzs_V_Fixed(ArmEmitterContext context)
  358. {
  359. if (Optimizations.UseSse41)
  360. {
  361. EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsZero, scalar: false);
  362. }
  363. else
  364. {
  365. EmitFcvtz(context, signed: true, scalar: false);
  366. }
  367. }
  368. public static void Fcvtzu_Gp(ArmEmitterContext context)
  369. {
  370. if (Optimizations.UseSse41)
  371. {
  372. EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsZero, isFixed: false);
  373. }
  374. else
  375. {
  376. EmitFcvt_u_Gp(context, (op1) => op1);
  377. }
  378. }
  379. public static void Fcvtzu_Gp_Fixed(ArmEmitterContext context)
  380. {
  381. if (Optimizations.UseSse41)
  382. {
  383. EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsZero, isFixed: true);
  384. }
  385. else
  386. {
  387. EmitFcvtzu_Gp_Fixed(context);
  388. }
  389. }
  390. public static void Fcvtzu_S(ArmEmitterContext context)
  391. {
  392. if (Optimizations.UseSse41)
  393. {
  394. EmitSse41FcvtuOpF(context, FPRoundingMode.TowardsZero, scalar: true);
  395. }
  396. else
  397. {
  398. EmitFcvtz(context, signed: false, scalar: true);
  399. }
  400. }
  401. public static void Fcvtzu_V(ArmEmitterContext context)
  402. {
  403. if (Optimizations.UseSse41)
  404. {
  405. EmitSse41FcvtuOpF(context, FPRoundingMode.TowardsZero, scalar: false);
  406. }
  407. else
  408. {
  409. EmitFcvtz(context, signed: false, scalar: false);
  410. }
  411. }
  412. public static void Fcvtzu_V_Fixed(ArmEmitterContext context)
  413. {
  414. if (Optimizations.UseSse41)
  415. {
  416. EmitSse41FcvtuOpF(context, FPRoundingMode.TowardsZero, scalar: false);
  417. }
  418. else
  419. {
  420. EmitFcvtz(context, signed: false, scalar: false);
  421. }
  422. }
  423. public static void Scvtf_Gp(ArmEmitterContext context)
  424. {
  425. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  426. Operand res = GetIntOrZR(context, op.Rn);
  427. if (op.RegisterSize == RegisterSize.Int32)
  428. {
  429. res = context.SignExtend32(OperandType.I64, res);
  430. }
  431. res = EmitFPConvert(context, res, op.Size, signed: true);
  432. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  433. }
  434. public static void Scvtf_Gp_Fixed(ArmEmitterContext context)
  435. {
  436. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  437. Operand res = GetIntOrZR(context, op.Rn);
  438. if (op.RegisterSize == RegisterSize.Int32)
  439. {
  440. res = context.SignExtend32(OperandType.I64, res);
  441. }
  442. res = EmitFPConvert(context, res, op.Size, signed: true);
  443. res = EmitI2fFBitsMul(context, res, op.FBits);
  444. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  445. }
  446. public static void Scvtf_S(ArmEmitterContext context)
  447. {
  448. if (Optimizations.UseSse2)
  449. {
  450. EmitSse2ScvtfOp(context, scalar: true);
  451. }
  452. else
  453. {
  454. EmitCvtf(context, signed: true, scalar: true);
  455. }
  456. }
  457. public static void Scvtf_S_Fixed(ArmEmitterContext context)
  458. {
  459. if (Optimizations.UseSse2)
  460. {
  461. EmitSse2ScvtfOp(context, scalar: true);
  462. }
  463. else
  464. {
  465. EmitCvtf(context, signed: true, scalar: true);
  466. }
  467. }
  468. public static void Scvtf_V(ArmEmitterContext context)
  469. {
  470. if (Optimizations.UseSse2)
  471. {
  472. EmitSse2ScvtfOp(context, scalar: false);
  473. }
  474. else
  475. {
  476. EmitCvtf(context, signed: true, scalar: false);
  477. }
  478. }
  479. public static void Scvtf_V_Fixed(ArmEmitterContext context)
  480. {
  481. if (Optimizations.UseSse2)
  482. {
  483. EmitSse2ScvtfOp(context, scalar: false);
  484. }
  485. else
  486. {
  487. EmitCvtf(context, signed: true, scalar: false);
  488. }
  489. }
  490. public static void Ucvtf_Gp(ArmEmitterContext context)
  491. {
  492. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  493. Operand res = GetIntOrZR(context, op.Rn);
  494. res = EmitFPConvert(context, res, op.Size, signed: false);
  495. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  496. }
  497. public static void Ucvtf_Gp_Fixed(ArmEmitterContext context)
  498. {
  499. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  500. Operand res = GetIntOrZR(context, op.Rn);
  501. res = EmitFPConvert(context, res, op.Size, signed: false);
  502. res = EmitI2fFBitsMul(context, res, op.FBits);
  503. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  504. }
  505. public static void Ucvtf_S(ArmEmitterContext context)
  506. {
  507. if (Optimizations.UseSse2)
  508. {
  509. EmitSse2UcvtfOp(context, scalar: true);
  510. }
  511. else
  512. {
  513. EmitCvtf(context, signed: false, scalar: true);
  514. }
  515. }
  516. public static void Ucvtf_S_Fixed(ArmEmitterContext context)
  517. {
  518. if (Optimizations.UseSse2)
  519. {
  520. EmitSse2UcvtfOp(context, scalar: true);
  521. }
  522. else
  523. {
  524. EmitCvtf(context, signed: false, scalar: true);
  525. }
  526. }
  527. public static void Ucvtf_V(ArmEmitterContext context)
  528. {
  529. if (Optimizations.UseSse2)
  530. {
  531. EmitSse2UcvtfOp(context, scalar: false);
  532. }
  533. else
  534. {
  535. EmitCvtf(context, signed: false, scalar: false);
  536. }
  537. }
  538. public static void Ucvtf_V_Fixed(ArmEmitterContext context)
  539. {
  540. if (Optimizations.UseSse2)
  541. {
  542. EmitSse2UcvtfOp(context, scalar: false);
  543. }
  544. else
  545. {
  546. EmitCvtf(context, signed: false, scalar: false);
  547. }
  548. }
  549. private static void EmitFcvt(ArmEmitterContext context, Func1I emit, bool signed, bool scalar)
  550. {
  551. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  552. Operand res = context.VectorZero();
  553. Operand n = GetVec(op.Rn);
  554. int sizeF = op.Size & 1;
  555. int sizeI = sizeF + 2;
  556. OperandType type = sizeF == 0 ? OperandType.FP32 : OperandType.FP64;
  557. int elems = !scalar ? op.GetBytesCount() >> sizeI : 1;
  558. for (int index = 0; index < elems; index++)
  559. {
  560. Operand ne = context.VectorExtract(type, n, index);
  561. Operand e = emit(ne);
  562. if (sizeF == 0)
  563. {
  564. MethodInfo info = signed
  565. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS32))
  566. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU32));
  567. e = context.Call(info, e);
  568. e = context.ZeroExtend32(OperandType.I64, e);
  569. }
  570. else /* if (sizeF == 1) */
  571. {
  572. MethodInfo info = signed
  573. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS64))
  574. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU64));
  575. e = context.Call(info, e);
  576. }
  577. res = EmitVectorInsert(context, res, e, index, sizeI);
  578. }
  579. context.Copy(GetVec(op.Rd), res);
  580. }
  581. private static void EmitFcvtz(ArmEmitterContext context, bool signed, bool scalar)
  582. {
  583. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  584. Operand res = context.VectorZero();
  585. Operand n = GetVec(op.Rn);
  586. int sizeF = op.Size & 1;
  587. int sizeI = sizeF + 2;
  588. OperandType type = sizeF == 0 ? OperandType.FP32 : OperandType.FP64;
  589. int fBits = GetFBits(context);
  590. int elems = !scalar ? op.GetBytesCount() >> sizeI : 1;
  591. for (int index = 0; index < elems; index++)
  592. {
  593. Operand ne = context.VectorExtract(type, n, index);
  594. Operand e = EmitF2iFBitsMul(context, ne, fBits);
  595. if (sizeF == 0)
  596. {
  597. MethodInfo info = signed
  598. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS32))
  599. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU32));
  600. e = context.Call(info, e);
  601. e = context.ZeroExtend32(OperandType.I64, e);
  602. }
  603. else /* if (sizeF == 1) */
  604. {
  605. MethodInfo info = signed
  606. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS64))
  607. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU64));
  608. e = context.Call(info, e);
  609. }
  610. res = EmitVectorInsert(context, res, e, index, sizeI);
  611. }
  612. context.Copy(GetVec(op.Rd), res);
  613. }
  614. private static void EmitFcvt_s_Gp(ArmEmitterContext context, Func1I emit)
  615. {
  616. EmitFcvt___Gp(context, emit, signed: true);
  617. }
  618. private static void EmitFcvt_u_Gp(ArmEmitterContext context, Func1I emit)
  619. {
  620. EmitFcvt___Gp(context, emit, signed: false);
  621. }
  622. private static void EmitFcvt___Gp(ArmEmitterContext context, Func1I emit, bool signed)
  623. {
  624. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  625. OperandType type = op.Size == 0 ? OperandType.FP32 : OperandType.FP64;
  626. Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
  627. Operand res = signed
  628. ? EmitScalarFcvts(context, emit(ne), 0)
  629. : EmitScalarFcvtu(context, emit(ne), 0);
  630. SetIntOrZR(context, op.Rd, res);
  631. }
  632. private static void EmitFcvtzs_Gp_Fixed(ArmEmitterContext context)
  633. {
  634. EmitFcvtz__Gp_Fixed(context, signed: true);
  635. }
  636. private static void EmitFcvtzu_Gp_Fixed(ArmEmitterContext context)
  637. {
  638. EmitFcvtz__Gp_Fixed(context, signed: false);
  639. }
  640. private static void EmitFcvtz__Gp_Fixed(ArmEmitterContext context, bool signed)
  641. {
  642. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  643. OperandType type = op.Size == 0 ? OperandType.FP32 : OperandType.FP64;
  644. Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
  645. Operand res = signed
  646. ? EmitScalarFcvts(context, ne, op.FBits)
  647. : EmitScalarFcvtu(context, ne, op.FBits);
  648. SetIntOrZR(context, op.Rd, res);
  649. }
  650. private static void EmitCvtf(ArmEmitterContext context, bool signed, bool scalar)
  651. {
  652. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  653. Operand res = context.VectorZero();
  654. int sizeF = op.Size & 1;
  655. int sizeI = sizeF + 2;
  656. int fBits = GetFBits(context);
  657. int elems = !scalar ? op.GetBytesCount() >> sizeI : 1;
  658. for (int index = 0; index < elems; index++)
  659. {
  660. Operand ne = EmitVectorLongExtract(context, op.Rn, index, sizeI);
  661. Operand e = EmitFPConvert(context, ne, sizeF, signed);
  662. e = EmitI2fFBitsMul(context, e, fBits);
  663. res = context.VectorInsert(res, e, index);
  664. }
  665. context.Copy(GetVec(op.Rd), res);
  666. }
  667. private static int GetFBits(ArmEmitterContext context)
  668. {
  669. if (context.CurrOp is OpCodeSimdShImm op)
  670. {
  671. return GetImmShr(op);
  672. }
  673. return 0;
  674. }
  675. private static Operand EmitFPConvert(ArmEmitterContext context, Operand value, int size, bool signed)
  676. {
  677. Debug.Assert(value.Type == OperandType.I32 || value.Type == OperandType.I64);
  678. Debug.Assert((uint)size < 2);
  679. OperandType type = size == 0 ? OperandType.FP32 : OperandType.FP64;
  680. if (signed)
  681. {
  682. return context.ConvertToFP(type, value);
  683. }
  684. else
  685. {
  686. return context.ConvertToFPUI(type, value);
  687. }
  688. }
  689. private static Operand EmitScalarFcvts(ArmEmitterContext context, Operand value, int fBits)
  690. {
  691. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  692. value = EmitF2iFBitsMul(context, value, fBits);
  693. MethodInfo info;
  694. if (context.CurrOp.RegisterSize == RegisterSize.Int32)
  695. {
  696. info = value.Type == OperandType.FP32
  697. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS32))
  698. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS32));
  699. }
  700. else
  701. {
  702. info = value.Type == OperandType.FP32
  703. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS64))
  704. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS64));
  705. }
  706. return context.Call(info, value);
  707. }
  708. private static Operand EmitScalarFcvtu(ArmEmitterContext context, Operand value, int fBits)
  709. {
  710. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  711. value = EmitF2iFBitsMul(context, value, fBits);
  712. MethodInfo info;
  713. if (context.CurrOp.RegisterSize == RegisterSize.Int32)
  714. {
  715. info = value.Type == OperandType.FP32
  716. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU32))
  717. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU32));
  718. }
  719. else
  720. {
  721. info = value.Type == OperandType.FP32
  722. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU64))
  723. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU64));
  724. }
  725. return context.Call(info, value);
  726. }
  727. private static Operand EmitF2iFBitsMul(ArmEmitterContext context, Operand value, int fBits)
  728. {
  729. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  730. if (fBits == 0)
  731. {
  732. return value;
  733. }
  734. if (value.Type == OperandType.FP32)
  735. {
  736. return context.Multiply(value, ConstF(MathF.Pow(2f, fBits)));
  737. }
  738. else /* if (value.Type == OperandType.FP64) */
  739. {
  740. return context.Multiply(value, ConstF(Math.Pow(2d, fBits)));
  741. }
  742. }
  743. private static Operand EmitI2fFBitsMul(ArmEmitterContext context, Operand value, int fBits)
  744. {
  745. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  746. if (fBits == 0)
  747. {
  748. return value;
  749. }
  750. if (value.Type == OperandType.FP32)
  751. {
  752. return context.Multiply(value, ConstF(1f / MathF.Pow(2f, fBits)));
  753. }
  754. else /* if (value.Type == OperandType.FP64) */
  755. {
  756. return context.Multiply(value, ConstF(1d / Math.Pow(2d, fBits)));
  757. }
  758. }
  759. public static Operand EmitSse2CvtDoubleToInt64OpF(ArmEmitterContext context, Operand opF, bool scalar)
  760. {
  761. Debug.Assert(opF.Type == OperandType.V128);
  762. Operand longL = context.AddIntrinsicLong (Intrinsic.X86Cvtsd2si, opF); // opFL
  763. Operand res = context.VectorCreateScalar(longL);
  764. if (!scalar)
  765. {
  766. Operand opFH = context.AddIntrinsic (Intrinsic.X86Movhlps, res, opF); // res doesn't matter.
  767. Operand longH = context.AddIntrinsicLong (Intrinsic.X86Cvtsd2si, opFH);
  768. Operand resH = context.VectorCreateScalar(longH);
  769. res = context.AddIntrinsic (Intrinsic.X86Movlhps, res, resH);
  770. }
  771. return res;
  772. }
  773. private static Operand EmitSse2CvtInt64ToDoubleOp(ArmEmitterContext context, Operand op, bool scalar)
  774. {
  775. Debug.Assert(op.Type == OperandType.V128);
  776. Operand longL = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, op); // opL
  777. Operand res = context.AddIntrinsic (Intrinsic.X86Cvtsi2sd, context.VectorZero(), longL);
  778. if (!scalar)
  779. {
  780. Operand opH = context.AddIntrinsic (Intrinsic.X86Movhlps, res, op); // res doesn't matter.
  781. Operand longH = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, opH);
  782. Operand resH = context.AddIntrinsic (Intrinsic.X86Cvtsi2sd, res, longH); // res doesn't matter.
  783. res = context.AddIntrinsic (Intrinsic.X86Movlhps, res, resH);
  784. }
  785. return res;
  786. }
  787. private static void EmitSse2ScvtfOp(ArmEmitterContext context, bool scalar)
  788. {
  789. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  790. Operand n = GetVec(op.Rn);
  791. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  792. int sizeF = op.Size & 1;
  793. if (sizeF == 0)
  794. {
  795. Operand res = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, n);
  796. if (op is OpCodeSimdShImm fixedOp)
  797. {
  798. int fBits = GetImmShr(fixedOp);
  799. // BitConverter.Int32BitsToSingle(fpScaled) == 1f / MathF.Pow(2f, fBits)
  800. int fpScaled = 0x3F800000 - fBits * 0x800000;
  801. Operand fpScaledMask = scalar
  802. ? X86GetScalar (context, fpScaled)
  803. : X86GetAllElements(context, fpScaled);
  804. res = context.AddIntrinsic(Intrinsic.X86Mulps, res, fpScaledMask);
  805. }
  806. if (scalar)
  807. {
  808. res = context.VectorZeroUpper96(res);
  809. }
  810. else if (op.RegisterSize == RegisterSize.Simd64)
  811. {
  812. res = context.VectorZeroUpper64(res);
  813. }
  814. context.Copy(GetVec(op.Rd), res);
  815. }
  816. else /* if (sizeF == 1) */
  817. {
  818. Operand res = EmitSse2CvtInt64ToDoubleOp(context, n, scalar);
  819. if (op is OpCodeSimdShImm fixedOp)
  820. {
  821. int fBits = GetImmShr(fixedOp);
  822. // BitConverter.Int64BitsToDouble(fpScaled) == 1d / Math.Pow(2d, fBits)
  823. long fpScaled = 0x3FF0000000000000L - fBits * 0x10000000000000L;
  824. Operand fpScaledMask = scalar
  825. ? X86GetScalar (context, fpScaled)
  826. : X86GetAllElements(context, fpScaled);
  827. res = context.AddIntrinsic(Intrinsic.X86Mulpd, res, fpScaledMask);
  828. }
  829. if (scalar)
  830. {
  831. res = context.VectorZeroUpper64(res);
  832. }
  833. context.Copy(GetVec(op.Rd), res);
  834. }
  835. }
  836. private static void EmitSse2UcvtfOp(ArmEmitterContext context, bool scalar)
  837. {
  838. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  839. Operand n = GetVec(op.Rn);
  840. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  841. int sizeF = op.Size & 1;
  842. if (sizeF == 0)
  843. {
  844. Operand mask = scalar // 65536.000f (1 << 16)
  845. ? X86GetScalar (context, 0x47800000)
  846. : X86GetAllElements(context, 0x47800000);
  847. Operand res = context.AddIntrinsic(Intrinsic.X86Psrld, n, Const(16));
  848. res = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res);
  849. res = context.AddIntrinsic(Intrinsic.X86Mulps, res, mask);
  850. Operand res2 = context.AddIntrinsic(Intrinsic.X86Pslld, n, Const(16));
  851. res2 = context.AddIntrinsic(Intrinsic.X86Psrld, res2, Const(16));
  852. res2 = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res2);
  853. res = context.AddIntrinsic(Intrinsic.X86Addps, res, res2);
  854. if (op is OpCodeSimdShImm fixedOp)
  855. {
  856. int fBits = GetImmShr(fixedOp);
  857. // BitConverter.Int32BitsToSingle(fpScaled) == 1f / MathF.Pow(2f, fBits)
  858. int fpScaled = 0x3F800000 - fBits * 0x800000;
  859. Operand fpScaledMask = scalar
  860. ? X86GetScalar (context, fpScaled)
  861. : X86GetAllElements(context, fpScaled);
  862. res = context.AddIntrinsic(Intrinsic.X86Mulps, res, fpScaledMask);
  863. }
  864. if (scalar)
  865. {
  866. res = context.VectorZeroUpper96(res);
  867. }
  868. else if (op.RegisterSize == RegisterSize.Simd64)
  869. {
  870. res = context.VectorZeroUpper64(res);
  871. }
  872. context.Copy(GetVec(op.Rd), res);
  873. }
  874. else /* if (sizeF == 1) */
  875. {
  876. Operand mask = scalar // 4294967296.0000000d (1L << 32)
  877. ? X86GetScalar (context, 0x41F0000000000000L)
  878. : X86GetAllElements(context, 0x41F0000000000000L);
  879. Operand res = context.AddIntrinsic (Intrinsic.X86Psrlq, n, Const(32));
  880. res = EmitSse2CvtInt64ToDoubleOp(context, res, scalar);
  881. res = context.AddIntrinsic (Intrinsic.X86Mulpd, res, mask);
  882. Operand res2 = context.AddIntrinsic (Intrinsic.X86Psllq, n, Const(32));
  883. res2 = context.AddIntrinsic (Intrinsic.X86Psrlq, res2, Const(32));
  884. res2 = EmitSse2CvtInt64ToDoubleOp(context, res2, scalar);
  885. res = context.AddIntrinsic(Intrinsic.X86Addpd, res, res2);
  886. if (op is OpCodeSimdShImm fixedOp)
  887. {
  888. int fBits = GetImmShr(fixedOp);
  889. // BitConverter.Int64BitsToDouble(fpScaled) == 1d / Math.Pow(2d, fBits)
  890. long fpScaled = 0x3FF0000000000000L - fBits * 0x10000000000000L;
  891. Operand fpScaledMask = scalar
  892. ? X86GetScalar (context, fpScaled)
  893. : X86GetAllElements(context, fpScaled);
  894. res = context.AddIntrinsic(Intrinsic.X86Mulpd, res, fpScaledMask);
  895. }
  896. if (scalar)
  897. {
  898. res = context.VectorZeroUpper64(res);
  899. }
  900. context.Copy(GetVec(op.Rd), res);
  901. }
  902. }
  903. private static void EmitSse41FcvtsOpF(ArmEmitterContext context, FPRoundingMode roundMode, bool scalar)
  904. {
  905. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  906. Operand n = GetVec(op.Rn);
  907. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  908. int sizeF = op.Size & 1;
  909. if (sizeF == 0)
  910. {
  911. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, n, n, Const((int)CmpCondition.OrderedQ));
  912. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  913. if (op is OpCodeSimdShImm fixedOp)
  914. {
  915. int fBits = GetImmShr(fixedOp);
  916. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, fBits)
  917. int fpScaled = 0x3F800000 + fBits * 0x800000;
  918. Operand fpScaledMask = scalar
  919. ? X86GetScalar (context, fpScaled)
  920. : X86GetAllElements(context, fpScaled);
  921. nRes = context.AddIntrinsic(Intrinsic.X86Mulps, nRes, fpScaledMask);
  922. }
  923. nRes = context.AddIntrinsic(Intrinsic.X86Roundps, nRes, Const(X86GetRoundControl(roundMode)));
  924. Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes);
  925. Operand fpMaxValMask = scalar // 2.14748365E9f (2147483648)
  926. ? X86GetScalar (context, 0x4F000000)
  927. : X86GetAllElements(context, 0x4F000000);
  928. nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  929. Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nInt, nRes);
  930. if (scalar)
  931. {
  932. dRes = context.VectorZeroUpper96(dRes);
  933. }
  934. else if (op.RegisterSize == RegisterSize.Simd64)
  935. {
  936. dRes = context.VectorZeroUpper64(dRes);
  937. }
  938. context.Copy(GetVec(op.Rd), dRes);
  939. }
  940. else /* if (sizeF == 1) */
  941. {
  942. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, n, n, Const((int)CmpCondition.OrderedQ));
  943. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  944. if (op is OpCodeSimdShImm fixedOp)
  945. {
  946. int fBits = GetImmShr(fixedOp);
  947. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, fBits)
  948. long fpScaled = 0x3FF0000000000000L + fBits * 0x10000000000000L;
  949. Operand fpScaledMask = scalar
  950. ? X86GetScalar (context, fpScaled)
  951. : X86GetAllElements(context, fpScaled);
  952. nRes = context.AddIntrinsic(Intrinsic.X86Mulpd, nRes, fpScaledMask);
  953. }
  954. nRes = context.AddIntrinsic(Intrinsic.X86Roundpd, nRes, Const(X86GetRoundControl(roundMode)));
  955. Operand nLong = EmitSse2CvtDoubleToInt64OpF(context, nRes, scalar);
  956. Operand fpMaxValMask = scalar // 9.2233720368547760E18d (9223372036854775808)
  957. ? X86GetScalar (context, 0x43E0000000000000L)
  958. : X86GetAllElements(context, 0x43E0000000000000L);
  959. nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  960. Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nLong, nRes);
  961. if (scalar)
  962. {
  963. dRes = context.VectorZeroUpper64(dRes);
  964. }
  965. context.Copy(GetVec(op.Rd), dRes);
  966. }
  967. }
  968. private static void EmitSse41FcvtuOpF(ArmEmitterContext context, FPRoundingMode roundMode, bool scalar)
  969. {
  970. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  971. Operand n = GetVec(op.Rn);
  972. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  973. int sizeF = op.Size & 1;
  974. if (sizeF == 0)
  975. {
  976. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, n, n, Const((int)CmpCondition.OrderedQ));
  977. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  978. if (op is OpCodeSimdShImm fixedOp)
  979. {
  980. int fBits = GetImmShr(fixedOp);
  981. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, fBits)
  982. int fpScaled = 0x3F800000 + fBits * 0x800000;
  983. Operand fpScaledMask = scalar
  984. ? X86GetScalar (context, fpScaled)
  985. : X86GetAllElements(context, fpScaled);
  986. nRes = context.AddIntrinsic(Intrinsic.X86Mulps, nRes, fpScaledMask);
  987. }
  988. nRes = context.AddIntrinsic(Intrinsic.X86Roundps, nRes, Const(X86GetRoundControl(roundMode)));
  989. Operand zero = context.VectorZero();
  990. Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  991. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  992. Operand fpMaxValMask = scalar // 2.14748365E9f (2147483648)
  993. ? X86GetScalar (context, 0x4F000000)
  994. : X86GetAllElements(context, 0x4F000000);
  995. Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes);
  996. nRes = context.AddIntrinsic(Intrinsic.X86Subps, nRes, fpMaxValMask);
  997. nCmp = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  998. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  999. Operand nInt2 = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes);
  1000. nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1001. Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nInt2, nRes);
  1002. dRes = context.AddIntrinsic(Intrinsic.X86Paddd, dRes, nInt);
  1003. if (scalar)
  1004. {
  1005. dRes = context.VectorZeroUpper96(dRes);
  1006. }
  1007. else if (op.RegisterSize == RegisterSize.Simd64)
  1008. {
  1009. dRes = context.VectorZeroUpper64(dRes);
  1010. }
  1011. context.Copy(GetVec(op.Rd), dRes);
  1012. }
  1013. else /* if (sizeF == 1) */
  1014. {
  1015. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, n, n, Const((int)CmpCondition.OrderedQ));
  1016. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1017. if (op is OpCodeSimdShImm fixedOp)
  1018. {
  1019. int fBits = GetImmShr(fixedOp);
  1020. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, fBits)
  1021. long fpScaled = 0x3FF0000000000000L + fBits * 0x10000000000000L;
  1022. Operand fpScaledMask = scalar
  1023. ? X86GetScalar (context, fpScaled)
  1024. : X86GetAllElements(context, fpScaled);
  1025. nRes = context.AddIntrinsic(Intrinsic.X86Mulpd, nRes, fpScaledMask);
  1026. }
  1027. nRes = context.AddIntrinsic(Intrinsic.X86Roundpd, nRes, Const(X86GetRoundControl(roundMode)));
  1028. Operand zero = context.VectorZero();
  1029. Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1030. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1031. Operand fpMaxValMask = scalar // 9.2233720368547760E18d (9223372036854775808)
  1032. ? X86GetScalar (context, 0x43E0000000000000L)
  1033. : X86GetAllElements(context, 0x43E0000000000000L);
  1034. Operand nLong = EmitSse2CvtDoubleToInt64OpF(context, nRes, scalar);
  1035. nRes = context.AddIntrinsic(Intrinsic.X86Subpd, nRes, fpMaxValMask);
  1036. nCmp = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1037. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1038. Operand nLong2 = EmitSse2CvtDoubleToInt64OpF(context, nRes, scalar);
  1039. nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1040. Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nLong2, nRes);
  1041. dRes = context.AddIntrinsic(Intrinsic.X86Paddq, dRes, nLong);
  1042. if (scalar)
  1043. {
  1044. dRes = context.VectorZeroUpper64(dRes);
  1045. }
  1046. context.Copy(GetVec(op.Rd), dRes);
  1047. }
  1048. }
  1049. private static void EmitSse41Fcvts_Gp(ArmEmitterContext context, FPRoundingMode roundMode, bool isFixed)
  1050. {
  1051. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  1052. Operand n = GetVec(op.Rn);
  1053. if (op.Size == 0)
  1054. {
  1055. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, n, n, Const((int)CmpCondition.OrderedQ));
  1056. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1057. if (isFixed)
  1058. {
  1059. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, op.FBits)
  1060. int fpScaled = 0x3F800000 + op.FBits * 0x800000;
  1061. Operand fpScaledMask = X86GetScalar(context, fpScaled);
  1062. nRes = context.AddIntrinsic(Intrinsic.X86Mulss, nRes, fpScaledMask);
  1063. }
  1064. nRes = context.AddIntrinsic(Intrinsic.X86Roundss, nRes, Const(X86GetRoundControl(roundMode)));
  1065. Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
  1066. ? context.AddIntrinsicInt (Intrinsic.X86Cvtss2si, nRes)
  1067. : context.AddIntrinsicLong(Intrinsic.X86Cvtss2si, nRes);
  1068. int fpMaxVal = op.RegisterSize == RegisterSize.Int32
  1069. ? 0x4F000000 // 2.14748365E9f (2147483648)
  1070. : 0x5F000000; // 9.223372E18f (9223372036854775808)
  1071. Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
  1072. nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1073. Operand nInt = context.AddIntrinsicInt(Intrinsic.X86Cvtsi2si, nRes);
  1074. if (op.RegisterSize == RegisterSize.Int64)
  1075. {
  1076. nInt = context.SignExtend32(OperandType.I64, nInt);
  1077. }
  1078. Operand dRes = context.BitwiseExclusiveOr(nIntOrLong, nInt);
  1079. SetIntOrZR(context, op.Rd, dRes);
  1080. }
  1081. else /* if (op.Size == 1) */
  1082. {
  1083. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, n, n, Const((int)CmpCondition.OrderedQ));
  1084. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1085. if (isFixed)
  1086. {
  1087. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, op.FBits)
  1088. long fpScaled = 0x3FF0000000000000L + op.FBits * 0x10000000000000L;
  1089. Operand fpScaledMask = X86GetScalar(context, fpScaled);
  1090. nRes = context.AddIntrinsic(Intrinsic.X86Mulsd, nRes, fpScaledMask);
  1091. }
  1092. nRes = context.AddIntrinsic(Intrinsic.X86Roundsd, nRes, Const(X86GetRoundControl(roundMode)));
  1093. Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
  1094. ? context.AddIntrinsicInt (Intrinsic.X86Cvtsd2si, nRes)
  1095. : context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRes);
  1096. long fpMaxVal = op.RegisterSize == RegisterSize.Int32
  1097. ? 0x41E0000000000000L // 2147483648.0000000d (2147483648)
  1098. : 0x43E0000000000000L; // 9.2233720368547760E18d (9223372036854775808)
  1099. Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
  1100. nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1101. Operand nLong = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, nRes);
  1102. if (op.RegisterSize == RegisterSize.Int32)
  1103. {
  1104. nLong = context.ConvertI64ToI32(nLong);
  1105. }
  1106. Operand dRes = context.BitwiseExclusiveOr(nIntOrLong, nLong);
  1107. SetIntOrZR(context, op.Rd, dRes);
  1108. }
  1109. }
  1110. private static void EmitSse41Fcvtu_Gp(ArmEmitterContext context, FPRoundingMode roundMode, bool isFixed)
  1111. {
  1112. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  1113. Operand n = GetVec(op.Rn);
  1114. if (op.Size == 0)
  1115. {
  1116. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, n, n, Const((int)CmpCondition.OrderedQ));
  1117. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1118. if (isFixed)
  1119. {
  1120. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, op.FBits)
  1121. int fpScaled = 0x3F800000 + op.FBits * 0x800000;
  1122. Operand fpScaledMask = X86GetScalar(context, fpScaled);
  1123. nRes = context.AddIntrinsic(Intrinsic.X86Mulss, nRes, fpScaledMask);
  1124. }
  1125. nRes = context.AddIntrinsic(Intrinsic.X86Roundss, nRes, Const(X86GetRoundControl(roundMode)));
  1126. Operand zero = context.VectorZero();
  1127. Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1128. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1129. int fpMaxVal = op.RegisterSize == RegisterSize.Int32
  1130. ? 0x4F000000 // 2.14748365E9f (2147483648)
  1131. : 0x5F000000; // 9.223372E18f (9223372036854775808)
  1132. Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
  1133. Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
  1134. ? context.AddIntrinsicInt (Intrinsic.X86Cvtss2si, nRes)
  1135. : context.AddIntrinsicLong(Intrinsic.X86Cvtss2si, nRes);
  1136. nRes = context.AddIntrinsic(Intrinsic.X86Subss, nRes, fpMaxValMask);
  1137. nCmp = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1138. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1139. Operand nIntOrLong2 = op.RegisterSize == RegisterSize.Int32
  1140. ? context.AddIntrinsicInt (Intrinsic.X86Cvtss2si, nRes)
  1141. : context.AddIntrinsicLong(Intrinsic.X86Cvtss2si, nRes);
  1142. nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1143. Operand nInt = context.AddIntrinsicInt(Intrinsic.X86Cvtsi2si, nRes);
  1144. if (op.RegisterSize == RegisterSize.Int64)
  1145. {
  1146. nInt = context.SignExtend32(OperandType.I64, nInt);
  1147. }
  1148. Operand dRes = context.BitwiseExclusiveOr(nIntOrLong2, nInt);
  1149. dRes = context.Add(dRes, nIntOrLong);
  1150. SetIntOrZR(context, op.Rd, dRes);
  1151. }
  1152. else /* if (op.Size == 1) */
  1153. {
  1154. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, n, n, Const((int)CmpCondition.OrderedQ));
  1155. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1156. if (isFixed)
  1157. {
  1158. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, op.FBits)
  1159. long fpScaled = 0x3FF0000000000000L + op.FBits * 0x10000000000000L;
  1160. Operand fpScaledMask = X86GetScalar(context, fpScaled);
  1161. nRes = context.AddIntrinsic(Intrinsic.X86Mulsd, nRes, fpScaledMask);
  1162. }
  1163. nRes = context.AddIntrinsic(Intrinsic.X86Roundsd, nRes, Const(X86GetRoundControl(roundMode)));
  1164. Operand zero = context.VectorZero();
  1165. Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1166. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1167. long fpMaxVal = op.RegisterSize == RegisterSize.Int32
  1168. ? 0x41E0000000000000L // 2147483648.0000000d (2147483648)
  1169. : 0x43E0000000000000L; // 9.2233720368547760E18d (9223372036854775808)
  1170. Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
  1171. Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
  1172. ? context.AddIntrinsicInt (Intrinsic.X86Cvtsd2si, nRes)
  1173. : context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRes);
  1174. nRes = context.AddIntrinsic(Intrinsic.X86Subsd, nRes, fpMaxValMask);
  1175. nCmp = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1176. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1177. Operand nIntOrLong2 = op.RegisterSize == RegisterSize.Int32
  1178. ? context.AddIntrinsicInt (Intrinsic.X86Cvtsd2si, nRes)
  1179. : context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRes);
  1180. nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1181. Operand nLong = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, nRes);
  1182. if (op.RegisterSize == RegisterSize.Int32)
  1183. {
  1184. nLong = context.ConvertI64ToI32(nLong);
  1185. }
  1186. Operand dRes = context.BitwiseExclusiveOr(nIntOrLong2, nLong);
  1187. dRes = context.Add(dRes, nIntOrLong);
  1188. SetIntOrZR(context, op.Rd, dRes);
  1189. }
  1190. }
  1191. private static Operand EmitVectorLongExtract(ArmEmitterContext context, int reg, int index, int size)
  1192. {
  1193. OperandType type = size == 3 ? OperandType.I64 : OperandType.I32;
  1194. return context.VectorExtract(type, GetVec(reg), index);
  1195. }
  1196. }
  1197. }