LDj3SNuD 1bef70c068 Add Rshrn_V & Shrn_V Sse opt.. Add Mla_V, Mls_V & Mul_V Sse opt.; add Tests. (#614) 7 anni fa
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Decoders 9679896b94 Implement fixed-point variant of the UCVTF and SCVTF instructions (#578) 7 anni fa
Events 5001f78b1d Optimize address translation and write tracking on the MMU (#571) 7 anni fa
Instructions 1bef70c068 Add Rshrn_V & Shrn_V Sse opt.. Add Mla_V, Mls_V & Mul_V Sse opt.; add Tests. (#614) 7 anni fa
Memory 5001f78b1d Optimize address translation and write tracking on the MMU (#571) 7 anni fa
State 932224f051 ARM exclusive monitor and multicore fixes (#589) 7 anni fa
Translation 1bef70c068 Add Rshrn_V & Shrn_V Sse opt.. Add Mla_V, Mls_V & Mul_V Sse opt.; add Tests. (#614) 7 anni fa
ChocolArm64.csproj 932224f051 ARM exclusive monitor and multicore fixes (#589) 7 anni fa
CpuThread.cs 932224f051 ARM exclusive monitor and multicore fixes (#589) 7 anni fa
OpCodeTable.cs 9679896b94 Implement fixed-point variant of the UCVTF and SCVTF instructions (#578) 7 anni fa
Optimizations.cs e21ebbf666 Misc. CPU optimizations (#575) 7 anni fa