InstEmitSimdHelper.cs 51 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492
  1. using ARMeilleure.Decoders;
  2. using ARMeilleure.IntermediateRepresentation;
  3. using ARMeilleure.State;
  4. using ARMeilleure.Translation;
  5. using System;
  6. using System.Diagnostics;
  7. using static ARMeilleure.Instructions.InstEmitHelper;
  8. using static ARMeilleure.IntermediateRepresentation.OperandHelper;
  9. namespace ARMeilleure.Instructions
  10. {
  11. using Func1I = Func<Operand, Operand>;
  12. using Func2I = Func<Operand, Operand, Operand>;
  13. using Func3I = Func<Operand, Operand, Operand, Operand>;
  14. static class InstEmitSimdHelper
  15. {
  16. #region "X86 SSE Intrinsics"
  17. public static readonly Intrinsic[] X86PaddInstruction = new Intrinsic[]
  18. {
  19. Intrinsic.X86Paddb,
  20. Intrinsic.X86Paddw,
  21. Intrinsic.X86Paddd,
  22. Intrinsic.X86Paddq
  23. };
  24. public static readonly Intrinsic[] X86PcmpeqInstruction = new Intrinsic[]
  25. {
  26. Intrinsic.X86Pcmpeqb,
  27. Intrinsic.X86Pcmpeqw,
  28. Intrinsic.X86Pcmpeqd,
  29. Intrinsic.X86Pcmpeqq
  30. };
  31. public static readonly Intrinsic[] X86PcmpgtInstruction = new Intrinsic[]
  32. {
  33. Intrinsic.X86Pcmpgtb,
  34. Intrinsic.X86Pcmpgtw,
  35. Intrinsic.X86Pcmpgtd,
  36. Intrinsic.X86Pcmpgtq
  37. };
  38. public static readonly Intrinsic[] X86PmaxsInstruction = new Intrinsic[]
  39. {
  40. Intrinsic.X86Pmaxsb,
  41. Intrinsic.X86Pmaxsw,
  42. Intrinsic.X86Pmaxsd
  43. };
  44. public static readonly Intrinsic[] X86PmaxuInstruction = new Intrinsic[]
  45. {
  46. Intrinsic.X86Pmaxub,
  47. Intrinsic.X86Pmaxuw,
  48. Intrinsic.X86Pmaxud
  49. };
  50. public static readonly Intrinsic[] X86PminsInstruction = new Intrinsic[]
  51. {
  52. Intrinsic.X86Pminsb,
  53. Intrinsic.X86Pminsw,
  54. Intrinsic.X86Pminsd
  55. };
  56. public static readonly Intrinsic[] X86PminuInstruction = new Intrinsic[]
  57. {
  58. Intrinsic.X86Pminub,
  59. Intrinsic.X86Pminuw,
  60. Intrinsic.X86Pminud
  61. };
  62. public static readonly Intrinsic[] X86PmovsxInstruction = new Intrinsic[]
  63. {
  64. Intrinsic.X86Pmovsxbw,
  65. Intrinsic.X86Pmovsxwd,
  66. Intrinsic.X86Pmovsxdq
  67. };
  68. public static readonly Intrinsic[] X86PmovzxInstruction = new Intrinsic[]
  69. {
  70. Intrinsic.X86Pmovzxbw,
  71. Intrinsic.X86Pmovzxwd,
  72. Intrinsic.X86Pmovzxdq
  73. };
  74. public static readonly Intrinsic[] X86PsllInstruction = new Intrinsic[]
  75. {
  76. 0,
  77. Intrinsic.X86Psllw,
  78. Intrinsic.X86Pslld,
  79. Intrinsic.X86Psllq
  80. };
  81. public static readonly Intrinsic[] X86PsraInstruction = new Intrinsic[]
  82. {
  83. 0,
  84. Intrinsic.X86Psraw,
  85. Intrinsic.X86Psrad
  86. };
  87. public static readonly Intrinsic[] X86PsrlInstruction = new Intrinsic[]
  88. {
  89. 0,
  90. Intrinsic.X86Psrlw,
  91. Intrinsic.X86Psrld,
  92. Intrinsic.X86Psrlq
  93. };
  94. public static readonly Intrinsic[] X86PsubInstruction = new Intrinsic[]
  95. {
  96. Intrinsic.X86Psubb,
  97. Intrinsic.X86Psubw,
  98. Intrinsic.X86Psubd,
  99. Intrinsic.X86Psubq
  100. };
  101. public static readonly Intrinsic[] X86PunpckhInstruction = new Intrinsic[]
  102. {
  103. Intrinsic.X86Punpckhbw,
  104. Intrinsic.X86Punpckhwd,
  105. Intrinsic.X86Punpckhdq,
  106. Intrinsic.X86Punpckhqdq
  107. };
  108. public static readonly Intrinsic[] X86PunpcklInstruction = new Intrinsic[]
  109. {
  110. Intrinsic.X86Punpcklbw,
  111. Intrinsic.X86Punpcklwd,
  112. Intrinsic.X86Punpckldq,
  113. Intrinsic.X86Punpcklqdq
  114. };
  115. #endregion
  116. public static int GetImmShl(OpCodeSimdShImm op)
  117. {
  118. return op.Imm - (8 << op.Size);
  119. }
  120. public static int GetImmShr(OpCodeSimdShImm op)
  121. {
  122. return (8 << (op.Size + 1)) - op.Imm;
  123. }
  124. public static Operand X86GetScalar(ArmEmitterContext context, float value)
  125. {
  126. return X86GetScalar(context, BitConverter.SingleToInt32Bits(value));
  127. }
  128. public static Operand X86GetScalar(ArmEmitterContext context, double value)
  129. {
  130. return X86GetScalar(context, BitConverter.DoubleToInt64Bits(value));
  131. }
  132. public static Operand X86GetScalar(ArmEmitterContext context, int value)
  133. {
  134. return context.VectorCreateScalar(Const(value));
  135. }
  136. public static Operand X86GetScalar(ArmEmitterContext context, long value)
  137. {
  138. return context.VectorCreateScalar(Const(value));
  139. }
  140. public static Operand X86GetAllElements(ArmEmitterContext context, float value)
  141. {
  142. return X86GetAllElements(context, BitConverter.SingleToInt32Bits(value));
  143. }
  144. public static Operand X86GetAllElements(ArmEmitterContext context, double value)
  145. {
  146. return X86GetAllElements(context, BitConverter.DoubleToInt64Bits(value));
  147. }
  148. public static Operand X86GetAllElements(ArmEmitterContext context, int value)
  149. {
  150. Operand vector = context.VectorCreateScalar(Const(value));
  151. vector = context.AddIntrinsic(Intrinsic.X86Shufps, vector, vector, Const(0));
  152. return vector;
  153. }
  154. public static Operand X86GetAllElements(ArmEmitterContext context, long value)
  155. {
  156. Operand vector = context.VectorCreateScalar(Const(value));
  157. vector = context.AddIntrinsic(Intrinsic.X86Movlhps, vector, vector);
  158. return vector;
  159. }
  160. public static int X86GetRoundControl(FPRoundingMode roundMode)
  161. {
  162. switch (roundMode)
  163. {
  164. case FPRoundingMode.ToNearest: return 8 | 0;
  165. case FPRoundingMode.TowardsPlusInfinity: return 8 | 2;
  166. case FPRoundingMode.TowardsMinusInfinity: return 8 | 1;
  167. case FPRoundingMode.TowardsZero: return 8 | 3;
  168. }
  169. throw new ArgumentException($"Invalid rounding mode \"{roundMode}\".");
  170. }
  171. public static void EmitScalarUnaryOpF(ArmEmitterContext context, Intrinsic inst32, Intrinsic inst64)
  172. {
  173. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  174. Operand n = GetVec(op.Rn);
  175. Intrinsic inst = (op.Size & 1) != 0 ? inst64 : inst32;
  176. Operand res = context.AddIntrinsic(inst, n);
  177. if ((op.Size & 1) != 0)
  178. {
  179. res = context.VectorZeroUpper64(res);
  180. }
  181. else
  182. {
  183. res = context.VectorZeroUpper96(res);
  184. }
  185. context.Copy(GetVec(op.Rd), res);
  186. }
  187. public static void EmitScalarBinaryOpF(ArmEmitterContext context, Intrinsic inst32, Intrinsic inst64)
  188. {
  189. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  190. Operand n = GetVec(op.Rn);
  191. Operand m = GetVec(op.Rm);
  192. Intrinsic inst = (op.Size & 1) != 0 ? inst64 : inst32;
  193. Operand res = context.AddIntrinsic(inst, n, m);
  194. if ((op.Size & 1) != 0)
  195. {
  196. res = context.VectorZeroUpper64(res);
  197. }
  198. else
  199. {
  200. res = context.VectorZeroUpper96(res);
  201. }
  202. context.Copy(GetVec(op.Rd), res);
  203. }
  204. public static void EmitVectorUnaryOpF(ArmEmitterContext context, Intrinsic inst32, Intrinsic inst64)
  205. {
  206. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  207. Operand n = GetVec(op.Rn);
  208. Intrinsic inst = (op.Size & 1) != 0 ? inst64 : inst32;
  209. Operand res = context.AddIntrinsic(inst, n);
  210. if (op.RegisterSize == RegisterSize.Simd64)
  211. {
  212. res = context.VectorZeroUpper64(res);
  213. }
  214. context.Copy(GetVec(op.Rd), res);
  215. }
  216. public static void EmitVectorBinaryOpF(ArmEmitterContext context, Intrinsic inst32, Intrinsic inst64)
  217. {
  218. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  219. Operand n = GetVec(op.Rn);
  220. Operand m = GetVec(op.Rm);
  221. Intrinsic inst = (op.Size & 1) != 0 ? inst64 : inst32;
  222. Operand res = context.AddIntrinsic(inst, n, m);
  223. if (op.RegisterSize == RegisterSize.Simd64)
  224. {
  225. res = context.VectorZeroUpper64(res);
  226. }
  227. context.Copy(GetVec(op.Rd), res);
  228. }
  229. public static Operand EmitUnaryMathCall(ArmEmitterContext context, _F32_F32 f32, _F64_F64 f64, Operand n)
  230. {
  231. IOpCodeSimd op = (IOpCodeSimd)context.CurrOp;
  232. return (op.Size & 1) == 0 ? context.Call(f32, n) : context.Call(f64, n);
  233. }
  234. public static Operand EmitRoundMathCall(ArmEmitterContext context, MidpointRounding roundMode, Operand n)
  235. {
  236. IOpCodeSimd op = (IOpCodeSimd)context.CurrOp;
  237. Delegate dlg;
  238. if ((op.Size & 1) == 0)
  239. {
  240. dlg = new _F32_F32_MidpointRounding(MathF.Round);
  241. }
  242. else /* if ((op.Size & 1) == 1) */
  243. {
  244. dlg = new _F64_F64_MidpointRounding(Math.Round);
  245. }
  246. return context.Call(dlg, n, Const((int)roundMode));
  247. }
  248. public static Operand EmitSoftFloatCall(
  249. ArmEmitterContext context,
  250. _F32_F32 f32,
  251. _F64_F64 f64,
  252. params Operand[] callArgs)
  253. {
  254. IOpCodeSimd op = (IOpCodeSimd)context.CurrOp;
  255. Delegate dlg = (op.Size & 1) == 0 ? (Delegate)f32 : (Delegate)f64;
  256. return context.Call(dlg, callArgs);
  257. }
  258. public static Operand EmitSoftFloatCall(
  259. ArmEmitterContext context,
  260. _F32_F32_F32 f32,
  261. _F64_F64_F64 f64,
  262. params Operand[] callArgs)
  263. {
  264. IOpCodeSimd op = (IOpCodeSimd)context.CurrOp;
  265. Delegate dlg = (op.Size & 1) == 0 ? (Delegate)f32 : (Delegate)f64;
  266. return context.Call(dlg, callArgs);
  267. }
  268. public static Operand EmitSoftFloatCall(
  269. ArmEmitterContext context,
  270. _F32_F32_F32_F32 f32,
  271. _F64_F64_F64_F64 f64,
  272. params Operand[] callArgs)
  273. {
  274. IOpCodeSimd op = (IOpCodeSimd)context.CurrOp;
  275. Delegate dlg = (op.Size & 1) == 0 ? (Delegate)f32 : (Delegate)f64;
  276. return context.Call(dlg, callArgs);
  277. }
  278. public static void EmitScalarBinaryOpByElemF(ArmEmitterContext context, Func2I emit)
  279. {
  280. OpCodeSimdRegElemF op = (OpCodeSimdRegElemF)context.CurrOp;
  281. OperandType type = (op.Size & 1) != 0 ? OperandType.FP64 : OperandType.FP32;
  282. Operand n = context.VectorExtract(type, GetVec(op.Rn), 0);
  283. Operand m = context.VectorExtract(type, GetVec(op.Rm), op.Index);
  284. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), emit(n, m), 0));
  285. }
  286. public static void EmitScalarTernaryOpByElemF(ArmEmitterContext context, Func3I emit)
  287. {
  288. OpCodeSimdRegElemF op = (OpCodeSimdRegElemF)context.CurrOp;
  289. OperandType type = (op.Size & 1) != 0 ? OperandType.FP64 : OperandType.FP32;
  290. Operand d = context.VectorExtract(type, GetVec(op.Rd), 0);
  291. Operand n = context.VectorExtract(type, GetVec(op.Rn), 0);
  292. Operand m = context.VectorExtract(type, GetVec(op.Rm), op.Index);
  293. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), emit(d, n, m), 0));
  294. }
  295. public static void EmitScalarUnaryOpSx(ArmEmitterContext context, Func1I emit)
  296. {
  297. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  298. Operand n = EmitVectorExtractSx(context, op.Rn, 0, op.Size);
  299. Operand d = EmitVectorInsert(context, context.VectorZero(), emit(n), 0, op.Size);
  300. context.Copy(GetVec(op.Rd), d);
  301. }
  302. public static void EmitScalarBinaryOpSx(ArmEmitterContext context, Func2I emit)
  303. {
  304. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  305. Operand n = EmitVectorExtractSx(context, op.Rn, 0, op.Size);
  306. Operand m = EmitVectorExtractSx(context, op.Rm, 0, op.Size);
  307. Operand d = EmitVectorInsert(context, context.VectorZero(), emit(n, m), 0, op.Size);
  308. context.Copy(GetVec(op.Rd), d);
  309. }
  310. public static void EmitScalarUnaryOpZx(ArmEmitterContext context, Func1I emit)
  311. {
  312. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  313. Operand n = EmitVectorExtractZx(context, op.Rn, 0, op.Size);
  314. Operand d = EmitVectorInsert(context, context.VectorZero(), emit(n), 0, op.Size);
  315. context.Copy(GetVec(op.Rd), d);
  316. }
  317. public static void EmitScalarBinaryOpZx(ArmEmitterContext context, Func2I emit)
  318. {
  319. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  320. Operand n = EmitVectorExtractZx(context, op.Rn, 0, op.Size);
  321. Operand m = EmitVectorExtractZx(context, op.Rm, 0, op.Size);
  322. Operand d = EmitVectorInsert(context, context.VectorZero(), emit(n, m), 0, op.Size);
  323. context.Copy(GetVec(op.Rd), d);
  324. }
  325. public static void EmitScalarTernaryOpZx(ArmEmitterContext context, Func3I emit)
  326. {
  327. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  328. Operand d = EmitVectorExtractZx(context, op.Rd, 0, op.Size);
  329. Operand n = EmitVectorExtractZx(context, op.Rn, 0, op.Size);
  330. Operand m = EmitVectorExtractZx(context, op.Rm, 0, op.Size);
  331. d = EmitVectorInsert(context, context.VectorZero(), emit(d, n, m), 0, op.Size);
  332. context.Copy(GetVec(op.Rd), d);
  333. }
  334. public static void EmitScalarUnaryOpF(ArmEmitterContext context, Func1I emit)
  335. {
  336. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  337. OperandType type = (op.Size & 1) != 0 ? OperandType.FP64 : OperandType.FP32;
  338. Operand n = context.VectorExtract(type, GetVec(op.Rn), 0);
  339. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), emit(n), 0));
  340. }
  341. public static void EmitScalarBinaryOpF(ArmEmitterContext context, Func2I emit)
  342. {
  343. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  344. OperandType type = (op.Size & 1) != 0 ? OperandType.FP64 : OperandType.FP32;
  345. Operand n = context.VectorExtract(type, GetVec(op.Rn), 0);
  346. Operand m = context.VectorExtract(type, GetVec(op.Rm), 0);
  347. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), emit(n, m), 0));
  348. }
  349. public static void EmitScalarTernaryRaOpF(ArmEmitterContext context, Func3I emit)
  350. {
  351. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  352. OperandType type = (op.Size & 1) != 0 ? OperandType.FP64 : OperandType.FP32;
  353. Operand a = context.VectorExtract(type, GetVec(op.Ra), 0);
  354. Operand n = context.VectorExtract(type, GetVec(op.Rn), 0);
  355. Operand m = context.VectorExtract(type, GetVec(op.Rm), 0);
  356. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), emit(a, n, m), 0));
  357. }
  358. public static void EmitVectorUnaryOpF(ArmEmitterContext context, Func1I emit)
  359. {
  360. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  361. Operand res = context.VectorZero();
  362. int sizeF = op.Size & 1;
  363. OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
  364. int elems = op.GetBytesCount() >> sizeF + 2;
  365. for (int index = 0; index < elems; index++)
  366. {
  367. Operand ne = context.VectorExtract(type, GetVec(op.Rn), index);
  368. res = context.VectorInsert(res, emit(ne), index);
  369. }
  370. context.Copy(GetVec(op.Rd), res);
  371. }
  372. public static void EmitVectorBinaryOpF(ArmEmitterContext context, Func2I emit)
  373. {
  374. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  375. Operand res = context.VectorZero();
  376. int sizeF = op.Size & 1;
  377. OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
  378. int elems = op.GetBytesCount() >> sizeF + 2;
  379. for (int index = 0; index < elems; index++)
  380. {
  381. Operand ne = context.VectorExtract(type, GetVec(op.Rn), index);
  382. Operand me = context.VectorExtract(type, GetVec(op.Rm), index);
  383. res = context.VectorInsert(res, emit(ne, me), index);
  384. }
  385. context.Copy(GetVec(op.Rd), res);
  386. }
  387. public static void EmitVectorTernaryOpF(ArmEmitterContext context, Func3I emit)
  388. {
  389. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  390. Operand res = context.VectorZero();
  391. int sizeF = op.Size & 1;
  392. OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
  393. int elems = op.GetBytesCount() >> sizeF + 2;
  394. for (int index = 0; index < elems; index++)
  395. {
  396. Operand de = context.VectorExtract(type, GetVec(op.Rd), index);
  397. Operand ne = context.VectorExtract(type, GetVec(op.Rn), index);
  398. Operand me = context.VectorExtract(type, GetVec(op.Rm), index);
  399. res = context.VectorInsert(res, emit(de, ne, me), index);
  400. }
  401. context.Copy(GetVec(op.Rd), res);
  402. }
  403. public static void EmitVectorBinaryOpByElemF(ArmEmitterContext context, Func2I emit)
  404. {
  405. OpCodeSimdRegElemF op = (OpCodeSimdRegElemF)context.CurrOp;
  406. Operand res = context.VectorZero();
  407. int sizeF = op.Size & 1;
  408. OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
  409. int elems = op.GetBytesCount() >> sizeF + 2;
  410. for (int index = 0; index < elems; index++)
  411. {
  412. Operand ne = context.VectorExtract(type, GetVec(op.Rn), index);
  413. Operand me = context.VectorExtract(type, GetVec(op.Rm), op.Index);
  414. res = context.VectorInsert(res, emit(ne, me), index);
  415. }
  416. context.Copy(GetVec(op.Rd), res);
  417. }
  418. public static void EmitVectorTernaryOpByElemF(ArmEmitterContext context, Func3I emit)
  419. {
  420. OpCodeSimdRegElemF op = (OpCodeSimdRegElemF)context.CurrOp;
  421. Operand res = context.VectorZero();
  422. int sizeF = op.Size & 1;
  423. OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
  424. int elems = op.GetBytesCount() >> sizeF + 2;
  425. for (int index = 0; index < elems; index++)
  426. {
  427. Operand de = context.VectorExtract(type, GetVec(op.Rd), index);
  428. Operand ne = context.VectorExtract(type, GetVec(op.Rn), index);
  429. Operand me = context.VectorExtract(type, GetVec(op.Rm), op.Index);
  430. res = context.VectorInsert(res, emit(de, ne, me), index);
  431. }
  432. context.Copy(GetVec(op.Rd), res);
  433. }
  434. public static void EmitVectorUnaryOpSx(ArmEmitterContext context, Func1I emit)
  435. {
  436. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  437. Operand res = context.VectorZero();
  438. int elems = op.GetBytesCount() >> op.Size;
  439. for (int index = 0; index < elems; index++)
  440. {
  441. Operand ne = EmitVectorExtractSx(context, op.Rn, index, op.Size);
  442. res = EmitVectorInsert(context, res, emit(ne), index, op.Size);
  443. }
  444. context.Copy(GetVec(op.Rd), res);
  445. }
  446. public static void EmitVectorBinaryOpSx(ArmEmitterContext context, Func2I emit)
  447. {
  448. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  449. Operand res = context.VectorZero();
  450. int elems = op.GetBytesCount() >> op.Size;
  451. for (int index = 0; index < elems; index++)
  452. {
  453. Operand ne = EmitVectorExtractSx(context, op.Rn, index, op.Size);
  454. Operand me = EmitVectorExtractSx(context, op.Rm, index, op.Size);
  455. res = EmitVectorInsert(context, res, emit(ne, me), index, op.Size);
  456. }
  457. context.Copy(GetVec(op.Rd), res);
  458. }
  459. public static void EmitVectorTernaryOpSx(ArmEmitterContext context, Func3I emit)
  460. {
  461. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  462. Operand res = context.VectorZero();
  463. int elems = op.GetBytesCount() >> op.Size;
  464. for (int index = 0; index < elems; index++)
  465. {
  466. Operand de = EmitVectorExtractSx(context, op.Rd, index, op.Size);
  467. Operand ne = EmitVectorExtractSx(context, op.Rn, index, op.Size);
  468. Operand me = EmitVectorExtractSx(context, op.Rm, index, op.Size);
  469. res = EmitVectorInsert(context, res, emit(de, ne, me), index, op.Size);
  470. }
  471. context.Copy(GetVec(op.Rd), res);
  472. }
  473. public static void EmitVectorUnaryOpZx(ArmEmitterContext context, Func1I emit)
  474. {
  475. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  476. Operand res = context.VectorZero();
  477. int elems = op.GetBytesCount() >> op.Size;
  478. for (int index = 0; index < elems; index++)
  479. {
  480. Operand ne = EmitVectorExtractZx(context, op.Rn, index, op.Size);
  481. res = EmitVectorInsert(context, res, emit(ne), index, op.Size);
  482. }
  483. context.Copy(GetVec(op.Rd), res);
  484. }
  485. public static void EmitVectorBinaryOpZx(ArmEmitterContext context, Func2I emit)
  486. {
  487. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  488. Operand res = context.VectorZero();
  489. int elems = op.GetBytesCount() >> op.Size;
  490. for (int index = 0; index < elems; index++)
  491. {
  492. Operand ne = EmitVectorExtractZx(context, op.Rn, index, op.Size);
  493. Operand me = EmitVectorExtractZx(context, op.Rm, index, op.Size);
  494. res = EmitVectorInsert(context, res, emit(ne, me), index, op.Size);
  495. }
  496. context.Copy(GetVec(op.Rd), res);
  497. }
  498. public static void EmitVectorTernaryOpZx(ArmEmitterContext context, Func3I emit)
  499. {
  500. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  501. Operand res = context.VectorZero();
  502. int elems = op.GetBytesCount() >> op.Size;
  503. for (int index = 0; index < elems; index++)
  504. {
  505. Operand de = EmitVectorExtractZx(context, op.Rd, index, op.Size);
  506. Operand ne = EmitVectorExtractZx(context, op.Rn, index, op.Size);
  507. Operand me = EmitVectorExtractZx(context, op.Rm, index, op.Size);
  508. res = EmitVectorInsert(context, res, emit(de, ne, me), index, op.Size);
  509. }
  510. context.Copy(GetVec(op.Rd), res);
  511. }
  512. public static void EmitVectorBinaryOpByElemSx(ArmEmitterContext context, Func2I emit)
  513. {
  514. OpCodeSimdRegElem op = (OpCodeSimdRegElem)context.CurrOp;
  515. Operand res = context.VectorZero();
  516. Operand me = EmitVectorExtractSx(context, op.Rm, op.Index, op.Size);
  517. int elems = op.GetBytesCount() >> op.Size;
  518. for (int index = 0; index < elems; index++)
  519. {
  520. Operand ne = EmitVectorExtractSx(context, op.Rn, index, op.Size);
  521. res = EmitVectorInsert(context, res, emit(ne, me), index, op.Size);
  522. }
  523. context.Copy(GetVec(op.Rd), res);
  524. }
  525. public static void EmitVectorBinaryOpByElemZx(ArmEmitterContext context, Func2I emit)
  526. {
  527. OpCodeSimdRegElem op = (OpCodeSimdRegElem)context.CurrOp;
  528. Operand res = context.VectorZero();
  529. Operand me = EmitVectorExtractZx(context, op.Rm, op.Index, op.Size);
  530. int elems = op.GetBytesCount() >> op.Size;
  531. for (int index = 0; index < elems; index++)
  532. {
  533. Operand ne = EmitVectorExtractZx(context, op.Rn, index, op.Size);
  534. res = EmitVectorInsert(context, res, emit(ne, me), index, op.Size);
  535. }
  536. context.Copy(GetVec(op.Rd), res);
  537. }
  538. public static void EmitVectorTernaryOpByElemZx(ArmEmitterContext context, Func3I emit)
  539. {
  540. OpCodeSimdRegElem op = (OpCodeSimdRegElem)context.CurrOp;
  541. Operand res = context.VectorZero();
  542. Operand me = EmitVectorExtractZx(context, op.Rm, op.Index, op.Size);
  543. int elems = op.GetBytesCount() >> op.Size;
  544. for (int index = 0; index < elems; index++)
  545. {
  546. Operand de = EmitVectorExtractZx(context, op.Rd, index, op.Size);
  547. Operand ne = EmitVectorExtractZx(context, op.Rn, index, op.Size);
  548. res = EmitVectorInsert(context, res, emit(de, ne, me), index, op.Size);
  549. }
  550. context.Copy(GetVec(op.Rd), res);
  551. }
  552. public static void EmitVectorImmUnaryOp(ArmEmitterContext context, Func1I emit)
  553. {
  554. OpCodeSimdImm op = (OpCodeSimdImm)context.CurrOp;
  555. Operand imm = Const(op.Immediate);
  556. Operand res = context.VectorZero();
  557. int elems = op.GetBytesCount() >> op.Size;
  558. for (int index = 0; index < elems; index++)
  559. {
  560. res = EmitVectorInsert(context, res, emit(imm), index, op.Size);
  561. }
  562. context.Copy(GetVec(op.Rd), res);
  563. }
  564. public static void EmitVectorImmBinaryOp(ArmEmitterContext context, Func2I emit)
  565. {
  566. OpCodeSimdImm op = (OpCodeSimdImm)context.CurrOp;
  567. Operand imm = Const(op.Immediate);
  568. Operand res = context.VectorZero();
  569. int elems = op.GetBytesCount() >> op.Size;
  570. for (int index = 0; index < elems; index++)
  571. {
  572. Operand de = EmitVectorExtractZx(context, op.Rd, index, op.Size);
  573. res = EmitVectorInsert(context, res, emit(de, imm), index, op.Size);
  574. }
  575. context.Copy(GetVec(op.Rd), res);
  576. }
  577. public static void EmitVectorWidenRmBinaryOpSx(ArmEmitterContext context, Func2I emit)
  578. {
  579. EmitVectorWidenRmBinaryOp(context, emit, signed: true);
  580. }
  581. public static void EmitVectorWidenRmBinaryOpZx(ArmEmitterContext context, Func2I emit)
  582. {
  583. EmitVectorWidenRmBinaryOp(context, emit, signed: false);
  584. }
  585. private static void EmitVectorWidenRmBinaryOp(ArmEmitterContext context, Func2I emit, bool signed)
  586. {
  587. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  588. Operand res = context.VectorZero();
  589. int elems = 8 >> op.Size;
  590. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  591. for (int index = 0; index < elems; index++)
  592. {
  593. Operand ne = EmitVectorExtract(context, op.Rn, index, op.Size + 1, signed);
  594. Operand me = EmitVectorExtract(context, op.Rm, part + index, op.Size, signed);
  595. res = EmitVectorInsert(context, res, emit(ne, me), index, op.Size + 1);
  596. }
  597. context.Copy(GetVec(op.Rd), res);
  598. }
  599. public static void EmitVectorWidenRnRmBinaryOpSx(ArmEmitterContext context, Func2I emit)
  600. {
  601. EmitVectorWidenRnRmBinaryOp(context, emit, signed: true);
  602. }
  603. public static void EmitVectorWidenRnRmBinaryOpZx(ArmEmitterContext context, Func2I emit)
  604. {
  605. EmitVectorWidenRnRmBinaryOp(context, emit, signed: false);
  606. }
  607. private static void EmitVectorWidenRnRmBinaryOp(ArmEmitterContext context, Func2I emit, bool signed)
  608. {
  609. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  610. Operand res = context.VectorZero();
  611. int elems = 8 >> op.Size;
  612. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  613. for (int index = 0; index < elems; index++)
  614. {
  615. Operand ne = EmitVectorExtract(context, op.Rn, part + index, op.Size, signed);
  616. Operand me = EmitVectorExtract(context, op.Rm, part + index, op.Size, signed);
  617. res = EmitVectorInsert(context, res, emit(ne, me), index, op.Size + 1);
  618. }
  619. context.Copy(GetVec(op.Rd), res);
  620. }
  621. public static void EmitVectorWidenRnRmTernaryOpSx(ArmEmitterContext context, Func3I emit)
  622. {
  623. EmitVectorWidenRnRmTernaryOp(context, emit, signed: true);
  624. }
  625. public static void EmitVectorWidenRnRmTernaryOpZx(ArmEmitterContext context, Func3I emit)
  626. {
  627. EmitVectorWidenRnRmTernaryOp(context, emit, signed: false);
  628. }
  629. private static void EmitVectorWidenRnRmTernaryOp(ArmEmitterContext context, Func3I emit, bool signed)
  630. {
  631. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  632. Operand res = context.VectorZero();
  633. int elems = 8 >> op.Size;
  634. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  635. for (int index = 0; index < elems; index++)
  636. {
  637. Operand de = EmitVectorExtract(context, op.Rd, index, op.Size + 1, signed);
  638. Operand ne = EmitVectorExtract(context, op.Rn, part + index, op.Size, signed);
  639. Operand me = EmitVectorExtract(context, op.Rm, part + index, op.Size, signed);
  640. res = EmitVectorInsert(context, res, emit(de, ne, me), index, op.Size + 1);
  641. }
  642. context.Copy(GetVec(op.Rd), res);
  643. }
  644. public static void EmitVectorWidenBinaryOpByElemSx(ArmEmitterContext context, Func2I emit)
  645. {
  646. EmitVectorWidenBinaryOpByElem(context, emit, signed: true);
  647. }
  648. public static void EmitVectorWidenBinaryOpByElemZx(ArmEmitterContext context, Func2I emit)
  649. {
  650. EmitVectorWidenBinaryOpByElem(context, emit, signed: false);
  651. }
  652. private static void EmitVectorWidenBinaryOpByElem(ArmEmitterContext context, Func2I emit, bool signed)
  653. {
  654. OpCodeSimdRegElem op = (OpCodeSimdRegElem)context.CurrOp;
  655. Operand res = context.VectorZero();
  656. Operand me = EmitVectorExtract(context, op.Rm, op.Index, op.Size, signed);;
  657. int elems = 8 >> op.Size;
  658. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  659. for (int index = 0; index < elems; index++)
  660. {
  661. Operand ne = EmitVectorExtract(context, op.Rn, part + index, op.Size, signed);
  662. res = EmitVectorInsert(context, res, emit(ne, me), index, op.Size + 1);
  663. }
  664. context.Copy(GetVec(op.Rd), res);
  665. }
  666. public static void EmitVectorWidenTernaryOpByElemSx(ArmEmitterContext context, Func3I emit)
  667. {
  668. EmitVectorWidenTernaryOpByElem(context, emit, signed: true);
  669. }
  670. public static void EmitVectorWidenTernaryOpByElemZx(ArmEmitterContext context, Func3I emit)
  671. {
  672. EmitVectorWidenTernaryOpByElem(context, emit, signed: false);
  673. }
  674. private static void EmitVectorWidenTernaryOpByElem(ArmEmitterContext context, Func3I emit, bool signed)
  675. {
  676. OpCodeSimdRegElem op = (OpCodeSimdRegElem)context.CurrOp;
  677. Operand res = context.VectorZero();
  678. Operand me = EmitVectorExtract(context, op.Rm, op.Index, op.Size, signed);;
  679. int elems = 8 >> op.Size;
  680. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  681. for (int index = 0; index < elems; index++)
  682. {
  683. Operand de = EmitVectorExtract(context, op.Rd, index, op.Size + 1, signed);
  684. Operand ne = EmitVectorExtract(context, op.Rn, part + index, op.Size, signed);
  685. res = EmitVectorInsert(context, res, emit(de, ne, me), index, op.Size + 1);
  686. }
  687. context.Copy(GetVec(op.Rd), res);
  688. }
  689. public static void EmitVectorPairwiseOpSx(ArmEmitterContext context, Func2I emit)
  690. {
  691. EmitVectorPairwiseOp(context, emit, signed: true);
  692. }
  693. public static void EmitVectorPairwiseOpZx(ArmEmitterContext context, Func2I emit)
  694. {
  695. EmitVectorPairwiseOp(context, emit, signed: false);
  696. }
  697. private static void EmitVectorPairwiseOp(ArmEmitterContext context, Func2I emit, bool signed)
  698. {
  699. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  700. Operand res = context.VectorZero();
  701. int pairs = op.GetPairsCount() >> op.Size;
  702. for (int index = 0; index < pairs; index++)
  703. {
  704. int pairIndex = index << 1;
  705. Operand n0 = EmitVectorExtract(context, op.Rn, pairIndex, op.Size, signed);
  706. Operand n1 = EmitVectorExtract(context, op.Rn, pairIndex + 1, op.Size, signed);
  707. Operand m0 = EmitVectorExtract(context, op.Rm, pairIndex, op.Size, signed);
  708. Operand m1 = EmitVectorExtract(context, op.Rm, pairIndex + 1, op.Size, signed);
  709. res = EmitVectorInsert(context, res, emit(n0, n1), index, op.Size);
  710. res = EmitVectorInsert(context, res, emit(m0, m1), pairs + index, op.Size);
  711. }
  712. context.Copy(GetVec(op.Rd), res);
  713. }
  714. public static void EmitVectorAcrossVectorOpSx(ArmEmitterContext context, Func2I emit)
  715. {
  716. EmitVectorAcrossVectorOp(context, emit, signed: true, isLong: false);
  717. }
  718. public static void EmitVectorAcrossVectorOpZx(ArmEmitterContext context, Func2I emit)
  719. {
  720. EmitVectorAcrossVectorOp(context, emit, signed: false, isLong: false);
  721. }
  722. public static void EmitVectorLongAcrossVectorOpSx(ArmEmitterContext context, Func2I emit)
  723. {
  724. EmitVectorAcrossVectorOp(context, emit, signed: true, isLong: true);
  725. }
  726. public static void EmitVectorLongAcrossVectorOpZx(ArmEmitterContext context, Func2I emit)
  727. {
  728. EmitVectorAcrossVectorOp(context, emit, signed: false, isLong: true);
  729. }
  730. private static void EmitVectorAcrossVectorOp(
  731. ArmEmitterContext context,
  732. Func2I emit,
  733. bool signed,
  734. bool isLong)
  735. {
  736. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  737. int elems = op.GetBytesCount() >> op.Size;
  738. Operand res = EmitVectorExtract(context, op.Rn, 0, op.Size, signed);
  739. for (int index = 1; index < elems; index++)
  740. {
  741. Operand n = EmitVectorExtract(context, op.Rn, index, op.Size, signed);
  742. res = emit(res, n);
  743. }
  744. int size = isLong ? op.Size + 1 : op.Size;
  745. Operand d = EmitVectorInsert(context, context.VectorZero(), res, 0, size);
  746. context.Copy(GetVec(op.Rd), d);
  747. }
  748. public static void EmitVectorPairwiseOpF(ArmEmitterContext context, Func2I emit)
  749. {
  750. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  751. Operand res = context.VectorZero();
  752. int sizeF = op.Size & 1;
  753. OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
  754. int pairs = op.GetPairsCount() >> sizeF + 2;
  755. for (int index = 0; index < pairs; index++)
  756. {
  757. int pairIndex = index << 1;
  758. Operand n0 = context.VectorExtract(type, GetVec(op.Rn), pairIndex);
  759. Operand n1 = context.VectorExtract(type, GetVec(op.Rn), pairIndex + 1);
  760. Operand m0 = context.VectorExtract(type, GetVec(op.Rm), pairIndex);
  761. Operand m1 = context.VectorExtract(type, GetVec(op.Rm), pairIndex + 1);
  762. res = context.VectorInsert(res, emit(n0, n1), index);
  763. res = context.VectorInsert(res, emit(m0, m1), pairs + index);
  764. }
  765. context.Copy(GetVec(op.Rd), res);
  766. }
  767. public static void EmitVectorPairwiseOpF(ArmEmitterContext context, Intrinsic inst32, Intrinsic inst64)
  768. {
  769. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  770. Operand n = GetVec(op.Rn);
  771. Operand m = GetVec(op.Rm);
  772. int sizeF = op.Size & 1;
  773. if (sizeF == 0)
  774. {
  775. if (op.RegisterSize == RegisterSize.Simd64)
  776. {
  777. Operand unpck = context.AddIntrinsic(Intrinsic.X86Unpcklps, n, m);
  778. Operand zero = context.VectorZero();
  779. Operand part0 = context.AddIntrinsic(Intrinsic.X86Movlhps, unpck, zero);
  780. Operand part1 = context.AddIntrinsic(Intrinsic.X86Movhlps, zero, unpck);
  781. context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst32, part0, part1));
  782. }
  783. else /* if (op.RegisterSize == RegisterSize.Simd128) */
  784. {
  785. const int sm0 = 2 << 6 | 0 << 4 | 2 << 2 | 0 << 0;
  786. const int sm1 = 3 << 6 | 1 << 4 | 3 << 2 | 1 << 0;
  787. Operand part0 = context.AddIntrinsic(Intrinsic.X86Shufps, n, m, Const(sm0));
  788. Operand part1 = context.AddIntrinsic(Intrinsic.X86Shufps, n, m, Const(sm1));
  789. context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst32, part0, part1));
  790. }
  791. }
  792. else /* if (sizeF == 1) */
  793. {
  794. Operand part0 = context.AddIntrinsic(Intrinsic.X86Unpcklpd, n, m);
  795. Operand part1 = context.AddIntrinsic(Intrinsic.X86Unpckhpd, n, m);
  796. context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst64, part0, part1));
  797. }
  798. }
  799. public enum CmpCondition
  800. {
  801. // Legacy Sse.
  802. Equal = 0, // Ordered, non-signaling.
  803. LessThan = 1, // Ordered, signaling.
  804. LessThanOrEqual = 2, // Ordered, signaling.
  805. NotLessThan = 5, // Unordered, signaling.
  806. NotLessThanOrEqual = 6, // Unordered, signaling.
  807. OrderedQ = 7, // Non-signaling.
  808. // Vex.
  809. GreaterThanOrEqual = 13, // Ordered, signaling.
  810. GreaterThan = 14, // Ordered, signaling.
  811. OrderedS = 23 // Signaling.
  812. }
  813. [Flags]
  814. public enum SaturatingFlags
  815. {
  816. Scalar = 1 << 0,
  817. Signed = 1 << 1,
  818. Add = 1 << 2,
  819. Sub = 1 << 3,
  820. Accumulate = 1 << 4,
  821. ScalarSx = Scalar | Signed,
  822. ScalarZx = Scalar,
  823. VectorSx = Signed,
  824. VectorZx = 0
  825. }
  826. public static void EmitScalarSaturatingUnaryOpSx(ArmEmitterContext context, Func1I emit)
  827. {
  828. EmitSaturatingUnaryOpSx(context, emit, SaturatingFlags.ScalarSx);
  829. }
  830. public static void EmitVectorSaturatingUnaryOpSx(ArmEmitterContext context, Func1I emit)
  831. {
  832. EmitSaturatingUnaryOpSx(context, emit, SaturatingFlags.VectorSx);
  833. }
  834. private static void EmitSaturatingUnaryOpSx(ArmEmitterContext context, Func1I emit, SaturatingFlags flags)
  835. {
  836. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  837. Operand res = context.VectorZero();
  838. bool scalar = (flags & SaturatingFlags.Scalar) != 0;
  839. int elems = !scalar ? op.GetBytesCount() >> op.Size : 1;
  840. for (int index = 0; index < elems; index++)
  841. {
  842. Operand ne = EmitVectorExtractSx(context, op.Rn, index, op.Size);
  843. Operand de;
  844. if (op.Size <= 2)
  845. {
  846. de = EmitSatQ(context, emit(ne), op.Size, signedSrc: true, signedDst: true);
  847. }
  848. else /* if (op.Size == 3) */
  849. {
  850. de = EmitUnarySignedSatQAbsOrNeg(context, emit(ne));
  851. }
  852. res = EmitVectorInsert(context, res, de, index, op.Size);
  853. }
  854. context.Copy(GetVec(op.Rd), res);
  855. }
  856. public static void EmitScalarSaturatingBinaryOpSx(ArmEmitterContext context, SaturatingFlags flags)
  857. {
  858. EmitSaturatingBinaryOp(context, null, SaturatingFlags.ScalarSx | flags);
  859. }
  860. public static void EmitScalarSaturatingBinaryOpZx(ArmEmitterContext context, SaturatingFlags flags)
  861. {
  862. EmitSaturatingBinaryOp(context, null, SaturatingFlags.ScalarZx | flags);
  863. }
  864. public static void EmitVectorSaturatingBinaryOpSx(ArmEmitterContext context, SaturatingFlags flags)
  865. {
  866. EmitSaturatingBinaryOp(context, null, SaturatingFlags.VectorSx | flags);
  867. }
  868. public static void EmitVectorSaturatingBinaryOpZx(ArmEmitterContext context, SaturatingFlags flags)
  869. {
  870. EmitSaturatingBinaryOp(context, null, SaturatingFlags.VectorZx | flags);
  871. }
  872. public static void EmitSaturatingBinaryOp(ArmEmitterContext context, Func2I emit, SaturatingFlags flags)
  873. {
  874. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  875. Operand res = context.VectorZero();
  876. bool scalar = (flags & SaturatingFlags.Scalar) != 0;
  877. bool signed = (flags & SaturatingFlags.Signed) != 0;
  878. bool add = (flags & SaturatingFlags.Add) != 0;
  879. bool sub = (flags & SaturatingFlags.Sub) != 0;
  880. bool accumulate = (flags & SaturatingFlags.Accumulate) != 0;
  881. int elems = !scalar ? op.GetBytesCount() >> op.Size : 1;
  882. if (add || sub)
  883. {
  884. OpCodeSimdReg opReg = (OpCodeSimdReg)op;
  885. for (int index = 0; index < elems; index++)
  886. {
  887. Operand de;
  888. Operand ne = EmitVectorExtract(context, opReg.Rn, index, op.Size, signed);
  889. Operand me = EmitVectorExtract(context, opReg.Rm, index, op.Size, signed);
  890. if (op.Size <= 2)
  891. {
  892. Operand temp = add ? context.Add (ne, me)
  893. : context.Subtract(ne, me);
  894. de = EmitSatQ(context, temp, op.Size, signedSrc: true, signedDst: signed);
  895. }
  896. else if (add) /* if (op.Size == 3) */
  897. {
  898. de = EmitBinarySatQAdd(context, ne, me, signed);
  899. }
  900. else /* if (sub) */
  901. {
  902. de = EmitBinarySatQSub(context, ne, me, signed);
  903. }
  904. res = EmitVectorInsert(context, res, de, index, op.Size);
  905. }
  906. }
  907. else if (accumulate)
  908. {
  909. for (int index = 0; index < elems; index++)
  910. {
  911. Operand de;
  912. Operand ne = EmitVectorExtract(context, op.Rn, index, op.Size, !signed);
  913. Operand me = EmitVectorExtract(context, op.Rd, index, op.Size, signed);
  914. if (op.Size <= 2)
  915. {
  916. Operand temp = context.Add(ne, me);
  917. de = EmitSatQ(context, temp, op.Size, signedSrc: true, signedDst: signed);
  918. }
  919. else /* if (op.Size == 3) */
  920. {
  921. de = EmitBinarySatQAccumulate(context, ne, me, signed);
  922. }
  923. res = EmitVectorInsert(context, res, de, index, op.Size);
  924. }
  925. }
  926. else
  927. {
  928. OpCodeSimdReg opReg = (OpCodeSimdReg)op;
  929. for (int index = 0; index < elems; index++)
  930. {
  931. Operand ne = EmitVectorExtract(context, opReg.Rn, index, op.Size, signed);
  932. Operand me = EmitVectorExtract(context, opReg.Rm, index, op.Size, signed);
  933. Operand de = EmitSatQ(context, emit(ne, me), op.Size, true, signed);
  934. res = EmitVectorInsert(context, res, de, index, op.Size);
  935. }
  936. }
  937. context.Copy(GetVec(op.Rd), res);
  938. }
  939. [Flags]
  940. public enum SaturatingNarrowFlags
  941. {
  942. Scalar = 1 << 0,
  943. SignedSrc = 1 << 1,
  944. SignedDst = 1 << 2,
  945. ScalarSxSx = Scalar | SignedSrc | SignedDst,
  946. ScalarSxZx = Scalar | SignedSrc,
  947. ScalarZxZx = Scalar,
  948. VectorSxSx = SignedSrc | SignedDst,
  949. VectorSxZx = SignedSrc,
  950. VectorZxZx = 0
  951. }
  952. public static void EmitSaturatingNarrowOp(ArmEmitterContext context, SaturatingNarrowFlags flags)
  953. {
  954. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  955. bool scalar = (flags & SaturatingNarrowFlags.Scalar) != 0;
  956. bool signedSrc = (flags & SaturatingNarrowFlags.SignedSrc) != 0;
  957. bool signedDst = (flags & SaturatingNarrowFlags.SignedDst) != 0;
  958. int elems = !scalar ? 8 >> op.Size : 1;
  959. int part = !scalar && (op.RegisterSize == RegisterSize.Simd128) ? elems : 0;
  960. Operand res = part == 0 ? context.VectorZero() : context.Copy(GetVec(op.Rd));
  961. for (int index = 0; index < elems; index++)
  962. {
  963. Operand ne = EmitVectorExtract(context, op.Rn, index, op.Size + 1, signedSrc);
  964. Operand temp = EmitSatQ(context, ne, op.Size, signedSrc, signedDst);
  965. res = EmitVectorInsert(context, res, temp, part + index, op.Size);
  966. }
  967. context.Copy(GetVec(op.Rd), res);
  968. }
  969. // TSrc (16bit, 32bit, 64bit; signed, unsigned) > TDst (8bit, 16bit, 32bit; signed, unsigned).
  970. public static Operand EmitSatQ(ArmEmitterContext context, Operand op, int sizeDst, bool signedSrc, bool signedDst)
  971. {
  972. if ((uint)sizeDst > 2u)
  973. {
  974. throw new ArgumentOutOfRangeException(nameof(sizeDst));
  975. }
  976. Delegate dlg;
  977. if (signedSrc)
  978. {
  979. dlg = signedDst
  980. ? (Delegate)new _S64_S64_S32(SoftFallback.SignedSrcSignedDstSatQ)
  981. : (Delegate)new _U64_S64_S32(SoftFallback.SignedSrcUnsignedDstSatQ);
  982. }
  983. else
  984. {
  985. dlg = signedDst
  986. ? (Delegate)new _S64_U64_S32(SoftFallback.UnsignedSrcSignedDstSatQ)
  987. : (Delegate)new _U64_U64_S32(SoftFallback.UnsignedSrcUnsignedDstSatQ);
  988. }
  989. return context.Call(dlg, op, Const(sizeDst));
  990. }
  991. // TSrc (64bit) == TDst (64bit); signed.
  992. public static Operand EmitUnarySignedSatQAbsOrNeg(ArmEmitterContext context, Operand op)
  993. {
  994. Debug.Assert(((OpCodeSimd)context.CurrOp).Size == 3, "Invalid element size.");
  995. return context.Call(new _S64_S64(SoftFallback.UnarySignedSatQAbsOrNeg), op);
  996. }
  997. // TSrcs (64bit) == TDst (64bit); signed, unsigned.
  998. public static Operand EmitBinarySatQAdd(ArmEmitterContext context, Operand op1, Operand op2, bool signed)
  999. {
  1000. Debug.Assert(((OpCodeSimd)context.CurrOp).Size == 3, "Invalid element size.");
  1001. Delegate dlg = signed
  1002. ? (Delegate)new _S64_S64_S64(SoftFallback.BinarySignedSatQAdd)
  1003. : (Delegate)new _U64_U64_U64(SoftFallback.BinaryUnsignedSatQAdd);
  1004. return context.Call(dlg, op1, op2);
  1005. }
  1006. // TSrcs (64bit) == TDst (64bit); signed, unsigned.
  1007. public static Operand EmitBinarySatQSub(ArmEmitterContext context, Operand op1, Operand op2, bool signed)
  1008. {
  1009. Debug.Assert(((OpCodeSimd)context.CurrOp).Size == 3, "Invalid element size.");
  1010. Delegate dlg = signed
  1011. ? (Delegate)new _S64_S64_S64(SoftFallback.BinarySignedSatQSub)
  1012. : (Delegate)new _U64_U64_U64(SoftFallback.BinaryUnsignedSatQSub);
  1013. return context.Call(dlg, op1, op2);
  1014. }
  1015. // TSrcs (64bit) == TDst (64bit); signed, unsigned.
  1016. public static Operand EmitBinarySatQAccumulate(ArmEmitterContext context, Operand op1, Operand op2, bool signed)
  1017. {
  1018. Debug.Assert(((OpCodeSimd)context.CurrOp).Size == 3, "Invalid element size.");
  1019. Delegate dlg = signed
  1020. ? (Delegate)new _S64_U64_S64(SoftFallback.BinarySignedSatQAcc)
  1021. : (Delegate)new _U64_S64_U64(SoftFallback.BinaryUnsignedSatQAcc);
  1022. return context.Call(dlg, op1, op2);
  1023. }
  1024. public static Operand EmitVectorExtractSx(ArmEmitterContext context, int reg, int index, int size)
  1025. {
  1026. return EmitVectorExtract(context, reg, index, size, true);
  1027. }
  1028. public static Operand EmitVectorExtractZx(ArmEmitterContext context, int reg, int index, int size)
  1029. {
  1030. return EmitVectorExtract(context, reg, index, size, false);
  1031. }
  1032. public static Operand EmitVectorExtract(ArmEmitterContext context, int reg, int index, int size, bool signed)
  1033. {
  1034. ThrowIfInvalid(index, size);
  1035. Operand res = null;
  1036. switch (size)
  1037. {
  1038. case 0:
  1039. res = context.VectorExtract8(GetVec(reg), index);
  1040. break;
  1041. case 1:
  1042. res = context.VectorExtract16(GetVec(reg), index);
  1043. break;
  1044. case 2:
  1045. res = context.VectorExtract(OperandType.I32, GetVec(reg), index);
  1046. break;
  1047. case 3:
  1048. res = context.VectorExtract(OperandType.I64, GetVec(reg), index);
  1049. break;
  1050. }
  1051. if (signed)
  1052. {
  1053. switch (size)
  1054. {
  1055. case 0: res = context.SignExtend8 (OperandType.I64, res); break;
  1056. case 1: res = context.SignExtend16(OperandType.I64, res); break;
  1057. case 2: res = context.SignExtend32(OperandType.I64, res); break;
  1058. }
  1059. }
  1060. else
  1061. {
  1062. switch (size)
  1063. {
  1064. case 0: res = context.ZeroExtend8 (OperandType.I64, res); break;
  1065. case 1: res = context.ZeroExtend16(OperandType.I64, res); break;
  1066. case 2: res = context.ZeroExtend32(OperandType.I64, res); break;
  1067. }
  1068. }
  1069. return res;
  1070. }
  1071. public static Operand EmitVectorInsert(ArmEmitterContext context, Operand vector, Operand value, int index, int size)
  1072. {
  1073. ThrowIfInvalid(index, size);
  1074. if (size < 3)
  1075. {
  1076. value = context.ConvertI64ToI32(value);
  1077. }
  1078. switch (size)
  1079. {
  1080. case 0: vector = context.VectorInsert8 (vector, value, index); break;
  1081. case 1: vector = context.VectorInsert16(vector, value, index); break;
  1082. case 2: vector = context.VectorInsert (vector, value, index); break;
  1083. case 3: vector = context.VectorInsert (vector, value, index); break;
  1084. }
  1085. return vector;
  1086. }
  1087. private static void ThrowIfInvalid(int index, int size)
  1088. {
  1089. if ((uint)size > 3u)
  1090. {
  1091. throw new ArgumentOutOfRangeException(nameof(size));
  1092. }
  1093. if ((uint)index >= 16u >> size)
  1094. {
  1095. throw new ArgumentOutOfRangeException(nameof(index));
  1096. }
  1097. }
  1098. }
  1099. }