Arm64.cs 7.6 KB

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  1. // Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
  2. // ReSharper disable InconsistentNaming
  3. namespace Ryujinx.Tests.Unicorn.Native.Const
  4. {
  5. public enum Arm64
  6. {
  7. // ARM64 CPU
  8. CPU_ARM64_A57 = 0,
  9. CPU_ARM64_A53 = 1,
  10. CPU_ARM64_A72 = 2,
  11. CPU_ARM64_MAX = 3,
  12. CPU_ARM64_ENDING = 4,
  13. // ARM64 registers
  14. REG_INVALID = 0,
  15. REG_X29 = 1,
  16. REG_X30 = 2,
  17. REG_NZCV = 3,
  18. REG_SP = 4,
  19. REG_WSP = 5,
  20. REG_WZR = 6,
  21. REG_XZR = 7,
  22. REG_B0 = 8,
  23. REG_B1 = 9,
  24. REG_B2 = 10,
  25. REG_B3 = 11,
  26. REG_B4 = 12,
  27. REG_B5 = 13,
  28. REG_B6 = 14,
  29. REG_B7 = 15,
  30. REG_B8 = 16,
  31. REG_B9 = 17,
  32. REG_B10 = 18,
  33. REG_B11 = 19,
  34. REG_B12 = 20,
  35. REG_B13 = 21,
  36. REG_B14 = 22,
  37. REG_B15 = 23,
  38. REG_B16 = 24,
  39. REG_B17 = 25,
  40. REG_B18 = 26,
  41. REG_B19 = 27,
  42. REG_B20 = 28,
  43. REG_B21 = 29,
  44. REG_B22 = 30,
  45. REG_B23 = 31,
  46. REG_B24 = 32,
  47. REG_B25 = 33,
  48. REG_B26 = 34,
  49. REG_B27 = 35,
  50. REG_B28 = 36,
  51. REG_B29 = 37,
  52. REG_B30 = 38,
  53. REG_B31 = 39,
  54. REG_D0 = 40,
  55. REG_D1 = 41,
  56. REG_D2 = 42,
  57. REG_D3 = 43,
  58. REG_D4 = 44,
  59. REG_D5 = 45,
  60. REG_D6 = 46,
  61. REG_D7 = 47,
  62. REG_D8 = 48,
  63. REG_D9 = 49,
  64. REG_D10 = 50,
  65. REG_D11 = 51,
  66. REG_D12 = 52,
  67. REG_D13 = 53,
  68. REG_D14 = 54,
  69. REG_D15 = 55,
  70. REG_D16 = 56,
  71. REG_D17 = 57,
  72. REG_D18 = 58,
  73. REG_D19 = 59,
  74. REG_D20 = 60,
  75. REG_D21 = 61,
  76. REG_D22 = 62,
  77. REG_D23 = 63,
  78. REG_D24 = 64,
  79. REG_D25 = 65,
  80. REG_D26 = 66,
  81. REG_D27 = 67,
  82. REG_D28 = 68,
  83. REG_D29 = 69,
  84. REG_D30 = 70,
  85. REG_D31 = 71,
  86. REG_H0 = 72,
  87. REG_H1 = 73,
  88. REG_H2 = 74,
  89. REG_H3 = 75,
  90. REG_H4 = 76,
  91. REG_H5 = 77,
  92. REG_H6 = 78,
  93. REG_H7 = 79,
  94. REG_H8 = 80,
  95. REG_H9 = 81,
  96. REG_H10 = 82,
  97. REG_H11 = 83,
  98. REG_H12 = 84,
  99. REG_H13 = 85,
  100. REG_H14 = 86,
  101. REG_H15 = 87,
  102. REG_H16 = 88,
  103. REG_H17 = 89,
  104. REG_H18 = 90,
  105. REG_H19 = 91,
  106. REG_H20 = 92,
  107. REG_H21 = 93,
  108. REG_H22 = 94,
  109. REG_H23 = 95,
  110. REG_H24 = 96,
  111. REG_H25 = 97,
  112. REG_H26 = 98,
  113. REG_H27 = 99,
  114. REG_H28 = 100,
  115. REG_H29 = 101,
  116. REG_H30 = 102,
  117. REG_H31 = 103,
  118. REG_Q0 = 104,
  119. REG_Q1 = 105,
  120. REG_Q2 = 106,
  121. REG_Q3 = 107,
  122. REG_Q4 = 108,
  123. REG_Q5 = 109,
  124. REG_Q6 = 110,
  125. REG_Q7 = 111,
  126. REG_Q8 = 112,
  127. REG_Q9 = 113,
  128. REG_Q10 = 114,
  129. REG_Q11 = 115,
  130. REG_Q12 = 116,
  131. REG_Q13 = 117,
  132. REG_Q14 = 118,
  133. REG_Q15 = 119,
  134. REG_Q16 = 120,
  135. REG_Q17 = 121,
  136. REG_Q18 = 122,
  137. REG_Q19 = 123,
  138. REG_Q20 = 124,
  139. REG_Q21 = 125,
  140. REG_Q22 = 126,
  141. REG_Q23 = 127,
  142. REG_Q24 = 128,
  143. REG_Q25 = 129,
  144. REG_Q26 = 130,
  145. REG_Q27 = 131,
  146. REG_Q28 = 132,
  147. REG_Q29 = 133,
  148. REG_Q30 = 134,
  149. REG_Q31 = 135,
  150. REG_S0 = 136,
  151. REG_S1 = 137,
  152. REG_S2 = 138,
  153. REG_S3 = 139,
  154. REG_S4 = 140,
  155. REG_S5 = 141,
  156. REG_S6 = 142,
  157. REG_S7 = 143,
  158. REG_S8 = 144,
  159. REG_S9 = 145,
  160. REG_S10 = 146,
  161. REG_S11 = 147,
  162. REG_S12 = 148,
  163. REG_S13 = 149,
  164. REG_S14 = 150,
  165. REG_S15 = 151,
  166. REG_S16 = 152,
  167. REG_S17 = 153,
  168. REG_S18 = 154,
  169. REG_S19 = 155,
  170. REG_S20 = 156,
  171. REG_S21 = 157,
  172. REG_S22 = 158,
  173. REG_S23 = 159,
  174. REG_S24 = 160,
  175. REG_S25 = 161,
  176. REG_S26 = 162,
  177. REG_S27 = 163,
  178. REG_S28 = 164,
  179. REG_S29 = 165,
  180. REG_S30 = 166,
  181. REG_S31 = 167,
  182. REG_W0 = 168,
  183. REG_W1 = 169,
  184. REG_W2 = 170,
  185. REG_W3 = 171,
  186. REG_W4 = 172,
  187. REG_W5 = 173,
  188. REG_W6 = 174,
  189. REG_W7 = 175,
  190. REG_W8 = 176,
  191. REG_W9 = 177,
  192. REG_W10 = 178,
  193. REG_W11 = 179,
  194. REG_W12 = 180,
  195. REG_W13 = 181,
  196. REG_W14 = 182,
  197. REG_W15 = 183,
  198. REG_W16 = 184,
  199. REG_W17 = 185,
  200. REG_W18 = 186,
  201. REG_W19 = 187,
  202. REG_W20 = 188,
  203. REG_W21 = 189,
  204. REG_W22 = 190,
  205. REG_W23 = 191,
  206. REG_W24 = 192,
  207. REG_W25 = 193,
  208. REG_W26 = 194,
  209. REG_W27 = 195,
  210. REG_W28 = 196,
  211. REG_W29 = 197,
  212. REG_W30 = 198,
  213. REG_X0 = 199,
  214. REG_X1 = 200,
  215. REG_X2 = 201,
  216. REG_X3 = 202,
  217. REG_X4 = 203,
  218. REG_X5 = 204,
  219. REG_X6 = 205,
  220. REG_X7 = 206,
  221. REG_X8 = 207,
  222. REG_X9 = 208,
  223. REG_X10 = 209,
  224. REG_X11 = 210,
  225. REG_X12 = 211,
  226. REG_X13 = 212,
  227. REG_X14 = 213,
  228. REG_X15 = 214,
  229. REG_X16 = 215,
  230. REG_X17 = 216,
  231. REG_X18 = 217,
  232. REG_X19 = 218,
  233. REG_X20 = 219,
  234. REG_X21 = 220,
  235. REG_X22 = 221,
  236. REG_X23 = 222,
  237. REG_X24 = 223,
  238. REG_X25 = 224,
  239. REG_X26 = 225,
  240. REG_X27 = 226,
  241. REG_X28 = 227,
  242. REG_V0 = 228,
  243. REG_V1 = 229,
  244. REG_V2 = 230,
  245. REG_V3 = 231,
  246. REG_V4 = 232,
  247. REG_V5 = 233,
  248. REG_V6 = 234,
  249. REG_V7 = 235,
  250. REG_V8 = 236,
  251. REG_V9 = 237,
  252. REG_V10 = 238,
  253. REG_V11 = 239,
  254. REG_V12 = 240,
  255. REG_V13 = 241,
  256. REG_V14 = 242,
  257. REG_V15 = 243,
  258. REG_V16 = 244,
  259. REG_V17 = 245,
  260. REG_V18 = 246,
  261. REG_V19 = 247,
  262. REG_V20 = 248,
  263. REG_V21 = 249,
  264. REG_V22 = 250,
  265. REG_V23 = 251,
  266. REG_V24 = 252,
  267. REG_V25 = 253,
  268. REG_V26 = 254,
  269. REG_V27 = 255,
  270. REG_V28 = 256,
  271. REG_V29 = 257,
  272. REG_V30 = 258,
  273. REG_V31 = 259,
  274. // pseudo registers
  275. REG_PC = 260,
  276. REG_CPACR_EL1 = 261,
  277. // thread registers, depreciated, use UC_ARM64_REG_CP_REG instead
  278. REG_TPIDR_EL0 = 262,
  279. REG_TPIDRRO_EL0 = 263,
  280. REG_TPIDR_EL1 = 264,
  281. REG_PSTATE = 265,
  282. // exception link registers, depreciated, use UC_ARM64_REG_CP_REG instead
  283. REG_ELR_EL0 = 266,
  284. REG_ELR_EL1 = 267,
  285. REG_ELR_EL2 = 268,
  286. REG_ELR_EL3 = 269,
  287. // stack pointers registers, depreciated, use UC_ARM64_REG_CP_REG instead
  288. REG_SP_EL0 = 270,
  289. REG_SP_EL1 = 271,
  290. REG_SP_EL2 = 272,
  291. REG_SP_EL3 = 273,
  292. // other CP15 registers, depreciated, use UC_ARM64_REG_CP_REG instead
  293. REG_TTBR0_EL1 = 274,
  294. REG_TTBR1_EL1 = 275,
  295. REG_ESR_EL0 = 276,
  296. REG_ESR_EL1 = 277,
  297. REG_ESR_EL2 = 278,
  298. REG_ESR_EL3 = 279,
  299. REG_FAR_EL0 = 280,
  300. REG_FAR_EL1 = 281,
  301. REG_FAR_EL2 = 282,
  302. REG_FAR_EL3 = 283,
  303. REG_PAR_EL1 = 284,
  304. REG_MAIR_EL1 = 285,
  305. REG_VBAR_EL0 = 286,
  306. REG_VBAR_EL1 = 287,
  307. REG_VBAR_EL2 = 288,
  308. REG_VBAR_EL3 = 289,
  309. REG_CP_REG = 290,
  310. // floating point control and status registers
  311. REG_FPCR = 291,
  312. REG_FPSR = 292,
  313. REG_ENDING = 293,
  314. // alias registers
  315. REG_IP0 = 215,
  316. REG_IP1 = 216,
  317. REG_FP = 1,
  318. REG_LR = 2,
  319. // ARM64 instructions
  320. INS_INVALID = 0,
  321. INS_MRS = 1,
  322. INS_MSR = 2,
  323. INS_SYS = 3,
  324. INS_SYSL = 4,
  325. INS_ENDING = 5,
  326. }
  327. }