InstEmitSimdCvt.cs 58 KB

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  1. using ARMeilleure.Decoders;
  2. using ARMeilleure.IntermediateRepresentation;
  3. using ARMeilleure.State;
  4. using ARMeilleure.Translation;
  5. using System;
  6. using System.Diagnostics;
  7. using System.Reflection;
  8. using static ARMeilleure.Instructions.InstEmitHelper;
  9. using static ARMeilleure.Instructions.InstEmitSimdHelper;
  10. using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
  11. namespace ARMeilleure.Instructions
  12. {
  13. using Func1I = Func<Operand, Operand>;
  14. static partial class InstEmit
  15. {
  16. public static void Fcvt_S(ArmEmitterContext context)
  17. {
  18. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  19. if (op.Size == 0 && op.Opc == 1) // Single -> Double.
  20. {
  21. if (Optimizations.UseSse2)
  22. {
  23. Operand n = GetVec(op.Rn);
  24. Operand res = context.AddIntrinsic(Intrinsic.X86Cvtss2sd, context.VectorZero(), n);
  25. context.Copy(GetVec(op.Rd), res);
  26. }
  27. else
  28. {
  29. Operand ne = context.VectorExtract(OperandType.FP32, GetVec(op.Rn), 0);
  30. Operand res = context.ConvertToFP(OperandType.FP64, ne);
  31. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  32. }
  33. }
  34. else if (op.Size == 1 && op.Opc == 0) // Double -> Single.
  35. {
  36. if (Optimizations.UseSse2)
  37. {
  38. Operand n = GetVec(op.Rn);
  39. Operand res = context.AddIntrinsic(Intrinsic.X86Cvtsd2ss, context.VectorZero(), n);
  40. context.Copy(GetVec(op.Rd), res);
  41. }
  42. else
  43. {
  44. Operand ne = context.VectorExtract(OperandType.FP64, GetVec(op.Rn), 0);
  45. Operand res = context.ConvertToFP(OperandType.FP32, ne);
  46. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  47. }
  48. }
  49. else if (op.Size == 0 && op.Opc == 3) // Single -> Half.
  50. {
  51. if (Optimizations.UseF16c)
  52. {
  53. Debug.Assert(!Optimizations.ForceLegacySse);
  54. Operand n = GetVec(op.Rn);
  55. Operand res = context.AddIntrinsic(Intrinsic.X86Vcvtps2ph, n, Const(X86GetRoundControl(FPRoundingMode.ToNearest)));
  56. res = context.AddIntrinsic(Intrinsic.X86Pslldq, res, Const(14)); // VectorZeroUpper112()
  57. res = context.AddIntrinsic(Intrinsic.X86Psrldq, res, Const(14));
  58. context.Copy(GetVec(op.Rd), res);
  59. }
  60. else
  61. {
  62. Operand ne = context.VectorExtract(OperandType.FP32, GetVec(op.Rn), 0);
  63. Operand res = context.Call(typeof(SoftFloat32_16).GetMethod(nameof(SoftFloat32_16.FPConvert)), ne);
  64. res = context.ZeroExtend16(OperandType.I64, res);
  65. context.Copy(GetVec(op.Rd), EmitVectorInsert(context, context.VectorZero(), res, 0, 1));
  66. }
  67. }
  68. else if (op.Size == 3 && op.Opc == 0) // Half -> Single.
  69. {
  70. if (Optimizations.UseF16c)
  71. {
  72. Debug.Assert(!Optimizations.ForceLegacySse);
  73. Operand res = context.AddIntrinsic(Intrinsic.X86Vcvtph2ps, GetVec(op.Rn));
  74. res = context.VectorZeroUpper96(res);
  75. context.Copy(GetVec(op.Rd), res);
  76. }
  77. else
  78. {
  79. Operand ne = EmitVectorExtractZx(context, op.Rn, 0, 1);
  80. Operand res = context.Call(typeof(SoftFloat16_32).GetMethod(nameof(SoftFloat16_32.FPConvert)), ne);
  81. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  82. }
  83. }
  84. else if (op.Size == 1 && op.Opc == 3) // Double -> Half.
  85. {
  86. if (Optimizations.UseF16c)
  87. {
  88. Debug.Assert(!Optimizations.ForceLegacySse);
  89. Operand n = GetVec(op.Rn);
  90. Operand res = context.AddIntrinsic(Intrinsic.X86Cvtsd2ss, context.VectorZero(), n);
  91. res = context.AddIntrinsic(Intrinsic.X86Vcvtps2ph, res, Const(X86GetRoundControl(FPRoundingMode.ToNearest)));
  92. context.Copy(GetVec(op.Rd), res);
  93. }
  94. else
  95. {
  96. Operand ne = context.VectorExtract(OperandType.FP64, GetVec(op.Rn), 0);
  97. Operand res = context.Call(typeof(SoftFloat64_16).GetMethod(nameof(SoftFloat64_16.FPConvert)), ne);
  98. res = context.ZeroExtend16(OperandType.I64, res);
  99. context.Copy(GetVec(op.Rd), EmitVectorInsert(context, context.VectorZero(), res, 0, 1));
  100. }
  101. }
  102. else if (op.Size == 3 && op.Opc == 1) // Half -> Double.
  103. {
  104. if (Optimizations.UseF16c)
  105. {
  106. Operand n = GetVec(op.Rn);
  107. Operand res = context.AddIntrinsic(Intrinsic.X86Vcvtph2ps, GetVec(op.Rn));
  108. res = context.AddIntrinsic(Intrinsic.X86Cvtss2sd, context.VectorZero(), res);
  109. res = context.VectorZeroUpper64(res);
  110. context.Copy(GetVec(op.Rd), res);
  111. }
  112. else
  113. {
  114. Operand ne = EmitVectorExtractZx(context, op.Rn, 0, 1);
  115. Operand res = context.Call(typeof(SoftFloat16_64).GetMethod(nameof(SoftFloat16_64.FPConvert)), ne);
  116. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  117. }
  118. }
  119. else // Invalid encoding.
  120. {
  121. Debug.Assert(false, $"type == {op.Size} && opc == {op.Opc}");
  122. }
  123. }
  124. public static void Fcvtas_Gp(ArmEmitterContext context)
  125. {
  126. EmitFcvt_s_Gp(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1));
  127. }
  128. public static void Fcvtas_S(ArmEmitterContext context)
  129. {
  130. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1), signed: true, scalar: true);
  131. }
  132. public static void Fcvtas_V(ArmEmitterContext context)
  133. {
  134. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1), signed: true, scalar: false);
  135. }
  136. public static void Fcvtau_Gp(ArmEmitterContext context)
  137. {
  138. EmitFcvt_u_Gp(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1));
  139. }
  140. public static void Fcvtau_S(ArmEmitterContext context)
  141. {
  142. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1), signed: false, scalar: true);
  143. }
  144. public static void Fcvtau_V(ArmEmitterContext context)
  145. {
  146. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1), signed: false, scalar: false);
  147. }
  148. public static void Fcvtl_V(ArmEmitterContext context)
  149. {
  150. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  151. int sizeF = op.Size & 1;
  152. if (Optimizations.UseSse2 && sizeF == 1)
  153. {
  154. Operand n = GetVec(op.Rn);
  155. Operand res = op.RegisterSize == RegisterSize.Simd128 ? context.AddIntrinsic(Intrinsic.X86Movhlps, n, n) : n;
  156. res = context.AddIntrinsic(Intrinsic.X86Cvtps2pd, res);
  157. context.Copy(GetVec(op.Rd), res);
  158. }
  159. else if (Optimizations.UseF16c && sizeF == 0)
  160. {
  161. Debug.Assert(!Optimizations.ForceLegacySse);
  162. Operand n = GetVec(op.Rn);
  163. Operand res = op.RegisterSize == RegisterSize.Simd128 ? context.AddIntrinsic(Intrinsic.X86Movhlps, n, n) : n;
  164. res = context.AddIntrinsic(Intrinsic.X86Vcvtph2ps, res);
  165. context.Copy(GetVec(op.Rd), res);
  166. }
  167. else
  168. {
  169. Operand res = context.VectorZero();
  170. int elems = 4 >> sizeF;
  171. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  172. for (int index = 0; index < elems; index++)
  173. {
  174. if (sizeF == 0)
  175. {
  176. Operand ne = EmitVectorExtractZx(context, op.Rn, part + index, 1);
  177. Operand e = context.Call(typeof(SoftFloat16_32).GetMethod(nameof(SoftFloat16_32.FPConvert)), ne);
  178. res = context.VectorInsert(res, e, index);
  179. }
  180. else /* if (sizeF == 1) */
  181. {
  182. Operand ne = context.VectorExtract(OperandType.FP32, GetVec(op.Rn), part + index);
  183. Operand e = context.ConvertToFP(OperandType.FP64, ne);
  184. res = context.VectorInsert(res, e, index);
  185. }
  186. }
  187. context.Copy(GetVec(op.Rd), res);
  188. }
  189. }
  190. public static void Fcvtms_Gp(ArmEmitterContext context)
  191. {
  192. if (Optimizations.UseSse41)
  193. {
  194. EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsMinusInfinity, isFixed: false);
  195. }
  196. else
  197. {
  198. EmitFcvt_s_Gp(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Floor), op1));
  199. }
  200. }
  201. public static void Fcvtms_V(ArmEmitterContext context)
  202. {
  203. if (Optimizations.UseSse41)
  204. {
  205. EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsMinusInfinity, scalar: false);
  206. }
  207. else
  208. {
  209. EmitFcvt(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Floor), op1), signed: true, scalar: false);
  210. }
  211. }
  212. public static void Fcvtmu_Gp(ArmEmitterContext context)
  213. {
  214. if (Optimizations.UseSse41)
  215. {
  216. EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsMinusInfinity, isFixed: false);
  217. }
  218. else
  219. {
  220. EmitFcvt_u_Gp(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Floor), op1));
  221. }
  222. }
  223. public static void Fcvtn_V(ArmEmitterContext context)
  224. {
  225. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  226. int sizeF = op.Size & 1;
  227. if (Optimizations.UseSse2 && sizeF == 1)
  228. {
  229. Operand d = GetVec(op.Rd);
  230. Intrinsic movInst = op.RegisterSize == RegisterSize.Simd128 ? Intrinsic.X86Movlhps : Intrinsic.X86Movhlps;
  231. Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtpd2ps, GetVec(op.Rn));
  232. nInt = context.AddIntrinsic(Intrinsic.X86Movlhps, nInt, nInt);
  233. Operand res = context.VectorZeroUpper64(d);
  234. res = context.AddIntrinsic(movInst, res, nInt);
  235. context.Copy(d, res);
  236. }
  237. else if (Optimizations.UseF16c && sizeF == 0)
  238. {
  239. Debug.Assert(!Optimizations.ForceLegacySse);
  240. Operand d = GetVec(op.Rd);
  241. Operand n = GetVec(op.Rn);
  242. Intrinsic movInst = op.RegisterSize == RegisterSize.Simd128 ? Intrinsic.X86Movlhps : Intrinsic.X86Movhlps;
  243. Operand nInt = context.AddIntrinsic(Intrinsic.X86Vcvtps2ph, n, Const(X86GetRoundControl(FPRoundingMode.ToNearest)));
  244. nInt = context.AddIntrinsic(Intrinsic.X86Movlhps, nInt, nInt);
  245. Operand res = context.VectorZeroUpper64(d);
  246. res = context.AddIntrinsic(movInst, res, nInt);
  247. context.Copy(d, res);
  248. }
  249. else
  250. {
  251. OperandType type = sizeF == 0 ? OperandType.FP32 : OperandType.FP64;
  252. int elems = 4 >> sizeF;
  253. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  254. Operand d = GetVec(op.Rd);
  255. Operand res = part == 0 ? context.VectorZero() : context.Copy(d);
  256. for (int index = 0; index < elems; index++)
  257. {
  258. Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
  259. if (sizeF == 0)
  260. {
  261. Operand e = context.Call(typeof(SoftFloat32_16).GetMethod(nameof(SoftFloat32_16.FPConvert)), ne);
  262. e = context.ZeroExtend16(OperandType.I64, e);
  263. res = EmitVectorInsert(context, res, e, part + index, 1);
  264. }
  265. else /* if (sizeF == 1) */
  266. {
  267. Operand e = context.ConvertToFP(OperandType.FP32, ne);
  268. res = context.VectorInsert(res, e, part + index);
  269. }
  270. }
  271. context.Copy(d, res);
  272. }
  273. }
  274. public static void Fcvtns_Gp(ArmEmitterContext context)
  275. {
  276. if (Optimizations.UseSse41)
  277. {
  278. EmitSse41Fcvts_Gp(context, FPRoundingMode.ToNearest, isFixed: false);
  279. }
  280. else
  281. {
  282. EmitFcvt_s_Gp(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1));
  283. }
  284. }
  285. public static void Fcvtns_S(ArmEmitterContext context)
  286. {
  287. if (Optimizations.UseSse41)
  288. {
  289. EmitSse41FcvtsOpF(context, FPRoundingMode.ToNearest, scalar: true);
  290. }
  291. else
  292. {
  293. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1), signed: true, scalar: true);
  294. }
  295. }
  296. public static void Fcvtns_V(ArmEmitterContext context)
  297. {
  298. if (Optimizations.UseSse41)
  299. {
  300. EmitSse41FcvtsOpF(context, FPRoundingMode.ToNearest, scalar: false);
  301. }
  302. else
  303. {
  304. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1), signed: true, scalar: false);
  305. }
  306. }
  307. public static void Fcvtnu_S(ArmEmitterContext context)
  308. {
  309. if (Optimizations.UseSse41)
  310. {
  311. EmitSse41FcvtuOpF(context, FPRoundingMode.ToNearest, scalar: true);
  312. }
  313. else
  314. {
  315. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1), signed: false, scalar: true);
  316. }
  317. }
  318. public static void Fcvtnu_V(ArmEmitterContext context)
  319. {
  320. if (Optimizations.UseSse41)
  321. {
  322. EmitSse41FcvtuOpF(context, FPRoundingMode.ToNearest, scalar: false);
  323. }
  324. else
  325. {
  326. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1), signed: false, scalar: false);
  327. }
  328. }
  329. public static void Fcvtps_Gp(ArmEmitterContext context)
  330. {
  331. if (Optimizations.UseSse41)
  332. {
  333. EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsPlusInfinity, isFixed: false);
  334. }
  335. else
  336. {
  337. EmitFcvt_s_Gp(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Ceiling), op1));
  338. }
  339. }
  340. public static void Fcvtpu_Gp(ArmEmitterContext context)
  341. {
  342. if (Optimizations.UseSse41)
  343. {
  344. EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsPlusInfinity, isFixed: false);
  345. }
  346. else
  347. {
  348. EmitFcvt_u_Gp(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Ceiling), op1));
  349. }
  350. }
  351. public static void Fcvtzs_Gp(ArmEmitterContext context)
  352. {
  353. if (Optimizations.UseSse41)
  354. {
  355. EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsZero, isFixed: false);
  356. }
  357. else
  358. {
  359. EmitFcvt_s_Gp(context, (op1) => op1);
  360. }
  361. }
  362. public static void Fcvtzs_Gp_Fixed(ArmEmitterContext context)
  363. {
  364. if (Optimizations.UseSse41)
  365. {
  366. EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsZero, isFixed: true);
  367. }
  368. else
  369. {
  370. EmitFcvtzs_Gp_Fixed(context);
  371. }
  372. }
  373. public static void Fcvtzs_S(ArmEmitterContext context)
  374. {
  375. if (Optimizations.UseSse41)
  376. {
  377. EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsZero, scalar: true);
  378. }
  379. else
  380. {
  381. EmitFcvtz(context, signed: true, scalar: true);
  382. }
  383. }
  384. public static void Fcvtzs_V(ArmEmitterContext context)
  385. {
  386. if (Optimizations.UseSse41)
  387. {
  388. EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsZero, scalar: false);
  389. }
  390. else
  391. {
  392. EmitFcvtz(context, signed: true, scalar: false);
  393. }
  394. }
  395. public static void Fcvtzs_V_Fixed(ArmEmitterContext context)
  396. {
  397. if (Optimizations.UseSse41)
  398. {
  399. EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsZero, scalar: false);
  400. }
  401. else
  402. {
  403. EmitFcvtz(context, signed: true, scalar: false);
  404. }
  405. }
  406. public static void Fcvtzu_Gp(ArmEmitterContext context)
  407. {
  408. if (Optimizations.UseSse41)
  409. {
  410. EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsZero, isFixed: false);
  411. }
  412. else
  413. {
  414. EmitFcvt_u_Gp(context, (op1) => op1);
  415. }
  416. }
  417. public static void Fcvtzu_Gp_Fixed(ArmEmitterContext context)
  418. {
  419. if (Optimizations.UseSse41)
  420. {
  421. EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsZero, isFixed: true);
  422. }
  423. else
  424. {
  425. EmitFcvtzu_Gp_Fixed(context);
  426. }
  427. }
  428. public static void Fcvtzu_S(ArmEmitterContext context)
  429. {
  430. if (Optimizations.UseSse41)
  431. {
  432. EmitSse41FcvtuOpF(context, FPRoundingMode.TowardsZero, scalar: true);
  433. }
  434. else
  435. {
  436. EmitFcvtz(context, signed: false, scalar: true);
  437. }
  438. }
  439. public static void Fcvtzu_V(ArmEmitterContext context)
  440. {
  441. if (Optimizations.UseSse41)
  442. {
  443. EmitSse41FcvtuOpF(context, FPRoundingMode.TowardsZero, scalar: false);
  444. }
  445. else
  446. {
  447. EmitFcvtz(context, signed: false, scalar: false);
  448. }
  449. }
  450. public static void Fcvtzu_V_Fixed(ArmEmitterContext context)
  451. {
  452. if (Optimizations.UseSse41)
  453. {
  454. EmitSse41FcvtuOpF(context, FPRoundingMode.TowardsZero, scalar: false);
  455. }
  456. else
  457. {
  458. EmitFcvtz(context, signed: false, scalar: false);
  459. }
  460. }
  461. public static void Scvtf_Gp(ArmEmitterContext context)
  462. {
  463. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  464. Operand res = GetIntOrZR(context, op.Rn);
  465. if (op.RegisterSize == RegisterSize.Int32)
  466. {
  467. res = context.SignExtend32(OperandType.I64, res);
  468. }
  469. res = EmitFPConvert(context, res, op.Size, signed: true);
  470. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  471. }
  472. public static void Scvtf_Gp_Fixed(ArmEmitterContext context)
  473. {
  474. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  475. Operand res = GetIntOrZR(context, op.Rn);
  476. if (op.RegisterSize == RegisterSize.Int32)
  477. {
  478. res = context.SignExtend32(OperandType.I64, res);
  479. }
  480. res = EmitFPConvert(context, res, op.Size, signed: true);
  481. res = EmitI2fFBitsMul(context, res, op.FBits);
  482. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  483. }
  484. public static void Scvtf_S(ArmEmitterContext context)
  485. {
  486. if (Optimizations.UseSse2)
  487. {
  488. EmitSse2ScvtfOp(context, scalar: true);
  489. }
  490. else
  491. {
  492. EmitCvtf(context, signed: true, scalar: true);
  493. }
  494. }
  495. public static void Scvtf_S_Fixed(ArmEmitterContext context)
  496. {
  497. if (Optimizations.UseSse2)
  498. {
  499. EmitSse2ScvtfOp(context, scalar: true);
  500. }
  501. else
  502. {
  503. EmitCvtf(context, signed: true, scalar: true);
  504. }
  505. }
  506. public static void Scvtf_V(ArmEmitterContext context)
  507. {
  508. if (Optimizations.UseSse2)
  509. {
  510. EmitSse2ScvtfOp(context, scalar: false);
  511. }
  512. else
  513. {
  514. EmitCvtf(context, signed: true, scalar: false);
  515. }
  516. }
  517. public static void Scvtf_V_Fixed(ArmEmitterContext context)
  518. {
  519. if (Optimizations.UseSse2)
  520. {
  521. EmitSse2ScvtfOp(context, scalar: false);
  522. }
  523. else
  524. {
  525. EmitCvtf(context, signed: true, scalar: false);
  526. }
  527. }
  528. public static void Ucvtf_Gp(ArmEmitterContext context)
  529. {
  530. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  531. Operand res = GetIntOrZR(context, op.Rn);
  532. res = EmitFPConvert(context, res, op.Size, signed: false);
  533. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  534. }
  535. public static void Ucvtf_Gp_Fixed(ArmEmitterContext context)
  536. {
  537. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  538. Operand res = GetIntOrZR(context, op.Rn);
  539. res = EmitFPConvert(context, res, op.Size, signed: false);
  540. res = EmitI2fFBitsMul(context, res, op.FBits);
  541. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  542. }
  543. public static void Ucvtf_S(ArmEmitterContext context)
  544. {
  545. if (Optimizations.UseSse2)
  546. {
  547. EmitSse2UcvtfOp(context, scalar: true);
  548. }
  549. else
  550. {
  551. EmitCvtf(context, signed: false, scalar: true);
  552. }
  553. }
  554. public static void Ucvtf_S_Fixed(ArmEmitterContext context)
  555. {
  556. if (Optimizations.UseSse2)
  557. {
  558. EmitSse2UcvtfOp(context, scalar: true);
  559. }
  560. else
  561. {
  562. EmitCvtf(context, signed: false, scalar: true);
  563. }
  564. }
  565. public static void Ucvtf_V(ArmEmitterContext context)
  566. {
  567. if (Optimizations.UseSse2)
  568. {
  569. EmitSse2UcvtfOp(context, scalar: false);
  570. }
  571. else
  572. {
  573. EmitCvtf(context, signed: false, scalar: false);
  574. }
  575. }
  576. public static void Ucvtf_V_Fixed(ArmEmitterContext context)
  577. {
  578. if (Optimizations.UseSse2)
  579. {
  580. EmitSse2UcvtfOp(context, scalar: false);
  581. }
  582. else
  583. {
  584. EmitCvtf(context, signed: false, scalar: false);
  585. }
  586. }
  587. private static void EmitFcvt(ArmEmitterContext context, Func1I emit, bool signed, bool scalar)
  588. {
  589. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  590. Operand res = context.VectorZero();
  591. Operand n = GetVec(op.Rn);
  592. int sizeF = op.Size & 1;
  593. int sizeI = sizeF + 2;
  594. OperandType type = sizeF == 0 ? OperandType.FP32 : OperandType.FP64;
  595. int elems = !scalar ? op.GetBytesCount() >> sizeI : 1;
  596. for (int index = 0; index < elems; index++)
  597. {
  598. Operand ne = context.VectorExtract(type, n, index);
  599. Operand e = emit(ne);
  600. if (sizeF == 0)
  601. {
  602. MethodInfo info = signed
  603. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS32))
  604. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU32));
  605. e = context.Call(info, e);
  606. e = context.ZeroExtend32(OperandType.I64, e);
  607. }
  608. else /* if (sizeF == 1) */
  609. {
  610. MethodInfo info = signed
  611. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS64))
  612. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU64));
  613. e = context.Call(info, e);
  614. }
  615. res = EmitVectorInsert(context, res, e, index, sizeI);
  616. }
  617. context.Copy(GetVec(op.Rd), res);
  618. }
  619. private static void EmitFcvtz(ArmEmitterContext context, bool signed, bool scalar)
  620. {
  621. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  622. Operand res = context.VectorZero();
  623. Operand n = GetVec(op.Rn);
  624. int sizeF = op.Size & 1;
  625. int sizeI = sizeF + 2;
  626. OperandType type = sizeF == 0 ? OperandType.FP32 : OperandType.FP64;
  627. int fBits = GetFBits(context);
  628. int elems = !scalar ? op.GetBytesCount() >> sizeI : 1;
  629. for (int index = 0; index < elems; index++)
  630. {
  631. Operand ne = context.VectorExtract(type, n, index);
  632. Operand e = EmitF2iFBitsMul(context, ne, fBits);
  633. if (sizeF == 0)
  634. {
  635. MethodInfo info = signed
  636. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS32))
  637. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU32));
  638. e = context.Call(info, e);
  639. e = context.ZeroExtend32(OperandType.I64, e);
  640. }
  641. else /* if (sizeF == 1) */
  642. {
  643. MethodInfo info = signed
  644. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS64))
  645. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU64));
  646. e = context.Call(info, e);
  647. }
  648. res = EmitVectorInsert(context, res, e, index, sizeI);
  649. }
  650. context.Copy(GetVec(op.Rd), res);
  651. }
  652. private static void EmitFcvt_s_Gp(ArmEmitterContext context, Func1I emit)
  653. {
  654. EmitFcvt___Gp(context, emit, signed: true);
  655. }
  656. private static void EmitFcvt_u_Gp(ArmEmitterContext context, Func1I emit)
  657. {
  658. EmitFcvt___Gp(context, emit, signed: false);
  659. }
  660. private static void EmitFcvt___Gp(ArmEmitterContext context, Func1I emit, bool signed)
  661. {
  662. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  663. OperandType type = op.Size == 0 ? OperandType.FP32 : OperandType.FP64;
  664. Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
  665. Operand res = signed
  666. ? EmitScalarFcvts(context, emit(ne), 0)
  667. : EmitScalarFcvtu(context, emit(ne), 0);
  668. SetIntOrZR(context, op.Rd, res);
  669. }
  670. private static void EmitFcvtzs_Gp_Fixed(ArmEmitterContext context)
  671. {
  672. EmitFcvtz__Gp_Fixed(context, signed: true);
  673. }
  674. private static void EmitFcvtzu_Gp_Fixed(ArmEmitterContext context)
  675. {
  676. EmitFcvtz__Gp_Fixed(context, signed: false);
  677. }
  678. private static void EmitFcvtz__Gp_Fixed(ArmEmitterContext context, bool signed)
  679. {
  680. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  681. OperandType type = op.Size == 0 ? OperandType.FP32 : OperandType.FP64;
  682. Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
  683. Operand res = signed
  684. ? EmitScalarFcvts(context, ne, op.FBits)
  685. : EmitScalarFcvtu(context, ne, op.FBits);
  686. SetIntOrZR(context, op.Rd, res);
  687. }
  688. private static void EmitCvtf(ArmEmitterContext context, bool signed, bool scalar)
  689. {
  690. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  691. Operand res = context.VectorZero();
  692. int sizeF = op.Size & 1;
  693. int sizeI = sizeF + 2;
  694. int fBits = GetFBits(context);
  695. int elems = !scalar ? op.GetBytesCount() >> sizeI : 1;
  696. for (int index = 0; index < elems; index++)
  697. {
  698. Operand ne = EmitVectorLongExtract(context, op.Rn, index, sizeI);
  699. Operand e = EmitFPConvert(context, ne, sizeF, signed);
  700. e = EmitI2fFBitsMul(context, e, fBits);
  701. res = context.VectorInsert(res, e, index);
  702. }
  703. context.Copy(GetVec(op.Rd), res);
  704. }
  705. private static int GetFBits(ArmEmitterContext context)
  706. {
  707. if (context.CurrOp is OpCodeSimdShImm op)
  708. {
  709. return GetImmShr(op);
  710. }
  711. return 0;
  712. }
  713. private static Operand EmitFPConvert(ArmEmitterContext context, Operand value, int size, bool signed)
  714. {
  715. Debug.Assert(value.Type == OperandType.I32 || value.Type == OperandType.I64);
  716. Debug.Assert((uint)size < 2);
  717. OperandType type = size == 0 ? OperandType.FP32 : OperandType.FP64;
  718. if (signed)
  719. {
  720. return context.ConvertToFP(type, value);
  721. }
  722. else
  723. {
  724. return context.ConvertToFPUI(type, value);
  725. }
  726. }
  727. private static Operand EmitScalarFcvts(ArmEmitterContext context, Operand value, int fBits)
  728. {
  729. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  730. value = EmitF2iFBitsMul(context, value, fBits);
  731. MethodInfo info;
  732. if (context.CurrOp.RegisterSize == RegisterSize.Int32)
  733. {
  734. info = value.Type == OperandType.FP32
  735. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS32))
  736. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS32));
  737. }
  738. else
  739. {
  740. info = value.Type == OperandType.FP32
  741. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS64))
  742. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS64));
  743. }
  744. return context.Call(info, value);
  745. }
  746. private static Operand EmitScalarFcvtu(ArmEmitterContext context, Operand value, int fBits)
  747. {
  748. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  749. value = EmitF2iFBitsMul(context, value, fBits);
  750. MethodInfo info;
  751. if (context.CurrOp.RegisterSize == RegisterSize.Int32)
  752. {
  753. info = value.Type == OperandType.FP32
  754. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU32))
  755. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU32));
  756. }
  757. else
  758. {
  759. info = value.Type == OperandType.FP32
  760. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU64))
  761. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU64));
  762. }
  763. return context.Call(info, value);
  764. }
  765. private static Operand EmitF2iFBitsMul(ArmEmitterContext context, Operand value, int fBits)
  766. {
  767. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  768. if (fBits == 0)
  769. {
  770. return value;
  771. }
  772. if (value.Type == OperandType.FP32)
  773. {
  774. return context.Multiply(value, ConstF(MathF.Pow(2f, fBits)));
  775. }
  776. else /* if (value.Type == OperandType.FP64) */
  777. {
  778. return context.Multiply(value, ConstF(Math.Pow(2d, fBits)));
  779. }
  780. }
  781. private static Operand EmitI2fFBitsMul(ArmEmitterContext context, Operand value, int fBits)
  782. {
  783. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  784. if (fBits == 0)
  785. {
  786. return value;
  787. }
  788. if (value.Type == OperandType.FP32)
  789. {
  790. return context.Multiply(value, ConstF(1f / MathF.Pow(2f, fBits)));
  791. }
  792. else /* if (value.Type == OperandType.FP64) */
  793. {
  794. return context.Multiply(value, ConstF(1d / Math.Pow(2d, fBits)));
  795. }
  796. }
  797. public static Operand EmitSse2CvtDoubleToInt64OpF(ArmEmitterContext context, Operand opF, bool scalar)
  798. {
  799. Debug.Assert(opF.Type == OperandType.V128);
  800. Operand longL = context.AddIntrinsicLong (Intrinsic.X86Cvtsd2si, opF); // opFL
  801. Operand res = context.VectorCreateScalar(longL);
  802. if (!scalar)
  803. {
  804. Operand opFH = context.AddIntrinsic (Intrinsic.X86Movhlps, res, opF); // res doesn't matter.
  805. Operand longH = context.AddIntrinsicLong (Intrinsic.X86Cvtsd2si, opFH);
  806. Operand resH = context.VectorCreateScalar(longH);
  807. res = context.AddIntrinsic (Intrinsic.X86Movlhps, res, resH);
  808. }
  809. return res;
  810. }
  811. private static Operand EmitSse2CvtInt64ToDoubleOp(ArmEmitterContext context, Operand op, bool scalar)
  812. {
  813. Debug.Assert(op.Type == OperandType.V128);
  814. Operand longL = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, op); // opL
  815. Operand res = context.AddIntrinsic (Intrinsic.X86Cvtsi2sd, context.VectorZero(), longL);
  816. if (!scalar)
  817. {
  818. Operand opH = context.AddIntrinsic (Intrinsic.X86Movhlps, res, op); // res doesn't matter.
  819. Operand longH = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, opH);
  820. Operand resH = context.AddIntrinsic (Intrinsic.X86Cvtsi2sd, res, longH); // res doesn't matter.
  821. res = context.AddIntrinsic (Intrinsic.X86Movlhps, res, resH);
  822. }
  823. return res;
  824. }
  825. private static void EmitSse2ScvtfOp(ArmEmitterContext context, bool scalar)
  826. {
  827. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  828. Operand n = GetVec(op.Rn);
  829. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  830. int sizeF = op.Size & 1;
  831. if (sizeF == 0)
  832. {
  833. Operand res = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, n);
  834. if (op is OpCodeSimdShImm fixedOp)
  835. {
  836. int fBits = GetImmShr(fixedOp);
  837. // BitConverter.Int32BitsToSingle(fpScaled) == 1f / MathF.Pow(2f, fBits)
  838. int fpScaled = 0x3F800000 - fBits * 0x800000;
  839. Operand fpScaledMask = scalar
  840. ? X86GetScalar (context, fpScaled)
  841. : X86GetAllElements(context, fpScaled);
  842. res = context.AddIntrinsic(Intrinsic.X86Mulps, res, fpScaledMask);
  843. }
  844. if (scalar)
  845. {
  846. res = context.VectorZeroUpper96(res);
  847. }
  848. else if (op.RegisterSize == RegisterSize.Simd64)
  849. {
  850. res = context.VectorZeroUpper64(res);
  851. }
  852. context.Copy(GetVec(op.Rd), res);
  853. }
  854. else /* if (sizeF == 1) */
  855. {
  856. Operand res = EmitSse2CvtInt64ToDoubleOp(context, n, scalar);
  857. if (op is OpCodeSimdShImm fixedOp)
  858. {
  859. int fBits = GetImmShr(fixedOp);
  860. // BitConverter.Int64BitsToDouble(fpScaled) == 1d / Math.Pow(2d, fBits)
  861. long fpScaled = 0x3FF0000000000000L - fBits * 0x10000000000000L;
  862. Operand fpScaledMask = scalar
  863. ? X86GetScalar (context, fpScaled)
  864. : X86GetAllElements(context, fpScaled);
  865. res = context.AddIntrinsic(Intrinsic.X86Mulpd, res, fpScaledMask);
  866. }
  867. if (scalar)
  868. {
  869. res = context.VectorZeroUpper64(res);
  870. }
  871. context.Copy(GetVec(op.Rd), res);
  872. }
  873. }
  874. private static void EmitSse2UcvtfOp(ArmEmitterContext context, bool scalar)
  875. {
  876. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  877. Operand n = GetVec(op.Rn);
  878. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  879. int sizeF = op.Size & 1;
  880. if (sizeF == 0)
  881. {
  882. Operand mask = scalar // 65536.000f (1 << 16)
  883. ? X86GetScalar (context, 0x47800000)
  884. : X86GetAllElements(context, 0x47800000);
  885. Operand res = context.AddIntrinsic(Intrinsic.X86Psrld, n, Const(16));
  886. res = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res);
  887. res = context.AddIntrinsic(Intrinsic.X86Mulps, res, mask);
  888. Operand res2 = context.AddIntrinsic(Intrinsic.X86Pslld, n, Const(16));
  889. res2 = context.AddIntrinsic(Intrinsic.X86Psrld, res2, Const(16));
  890. res2 = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res2);
  891. res = context.AddIntrinsic(Intrinsic.X86Addps, res, res2);
  892. if (op is OpCodeSimdShImm fixedOp)
  893. {
  894. int fBits = GetImmShr(fixedOp);
  895. // BitConverter.Int32BitsToSingle(fpScaled) == 1f / MathF.Pow(2f, fBits)
  896. int fpScaled = 0x3F800000 - fBits * 0x800000;
  897. Operand fpScaledMask = scalar
  898. ? X86GetScalar (context, fpScaled)
  899. : X86GetAllElements(context, fpScaled);
  900. res = context.AddIntrinsic(Intrinsic.X86Mulps, res, fpScaledMask);
  901. }
  902. if (scalar)
  903. {
  904. res = context.VectorZeroUpper96(res);
  905. }
  906. else if (op.RegisterSize == RegisterSize.Simd64)
  907. {
  908. res = context.VectorZeroUpper64(res);
  909. }
  910. context.Copy(GetVec(op.Rd), res);
  911. }
  912. else /* if (sizeF == 1) */
  913. {
  914. Operand mask = scalar // 4294967296.0000000d (1L << 32)
  915. ? X86GetScalar (context, 0x41F0000000000000L)
  916. : X86GetAllElements(context, 0x41F0000000000000L);
  917. Operand res = context.AddIntrinsic (Intrinsic.X86Psrlq, n, Const(32));
  918. res = EmitSse2CvtInt64ToDoubleOp(context, res, scalar);
  919. res = context.AddIntrinsic (Intrinsic.X86Mulpd, res, mask);
  920. Operand res2 = context.AddIntrinsic (Intrinsic.X86Psllq, n, Const(32));
  921. res2 = context.AddIntrinsic (Intrinsic.X86Psrlq, res2, Const(32));
  922. res2 = EmitSse2CvtInt64ToDoubleOp(context, res2, scalar);
  923. res = context.AddIntrinsic(Intrinsic.X86Addpd, res, res2);
  924. if (op is OpCodeSimdShImm fixedOp)
  925. {
  926. int fBits = GetImmShr(fixedOp);
  927. // BitConverter.Int64BitsToDouble(fpScaled) == 1d / Math.Pow(2d, fBits)
  928. long fpScaled = 0x3FF0000000000000L - fBits * 0x10000000000000L;
  929. Operand fpScaledMask = scalar
  930. ? X86GetScalar (context, fpScaled)
  931. : X86GetAllElements(context, fpScaled);
  932. res = context.AddIntrinsic(Intrinsic.X86Mulpd, res, fpScaledMask);
  933. }
  934. if (scalar)
  935. {
  936. res = context.VectorZeroUpper64(res);
  937. }
  938. context.Copy(GetVec(op.Rd), res);
  939. }
  940. }
  941. private static void EmitSse41FcvtsOpF(ArmEmitterContext context, FPRoundingMode roundMode, bool scalar)
  942. {
  943. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  944. Operand n = GetVec(op.Rn);
  945. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  946. int sizeF = op.Size & 1;
  947. if (sizeF == 0)
  948. {
  949. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, n, n, Const((int)CmpCondition.OrderedQ));
  950. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  951. if (op is OpCodeSimdShImm fixedOp)
  952. {
  953. int fBits = GetImmShr(fixedOp);
  954. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, fBits)
  955. int fpScaled = 0x3F800000 + fBits * 0x800000;
  956. Operand fpScaledMask = scalar
  957. ? X86GetScalar (context, fpScaled)
  958. : X86GetAllElements(context, fpScaled);
  959. nRes = context.AddIntrinsic(Intrinsic.X86Mulps, nRes, fpScaledMask);
  960. }
  961. nRes = context.AddIntrinsic(Intrinsic.X86Roundps, nRes, Const(X86GetRoundControl(roundMode)));
  962. Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes);
  963. Operand fpMaxValMask = scalar // 2.14748365E9f (2147483648)
  964. ? X86GetScalar (context, 0x4F000000)
  965. : X86GetAllElements(context, 0x4F000000);
  966. nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  967. Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nInt, nRes);
  968. if (scalar)
  969. {
  970. dRes = context.VectorZeroUpper96(dRes);
  971. }
  972. else if (op.RegisterSize == RegisterSize.Simd64)
  973. {
  974. dRes = context.VectorZeroUpper64(dRes);
  975. }
  976. context.Copy(GetVec(op.Rd), dRes);
  977. }
  978. else /* if (sizeF == 1) */
  979. {
  980. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, n, n, Const((int)CmpCondition.OrderedQ));
  981. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  982. if (op is OpCodeSimdShImm fixedOp)
  983. {
  984. int fBits = GetImmShr(fixedOp);
  985. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, fBits)
  986. long fpScaled = 0x3FF0000000000000L + fBits * 0x10000000000000L;
  987. Operand fpScaledMask = scalar
  988. ? X86GetScalar (context, fpScaled)
  989. : X86GetAllElements(context, fpScaled);
  990. nRes = context.AddIntrinsic(Intrinsic.X86Mulpd, nRes, fpScaledMask);
  991. }
  992. nRes = context.AddIntrinsic(Intrinsic.X86Roundpd, nRes, Const(X86GetRoundControl(roundMode)));
  993. Operand nLong = EmitSse2CvtDoubleToInt64OpF(context, nRes, scalar);
  994. Operand fpMaxValMask = scalar // 9.2233720368547760E18d (9223372036854775808)
  995. ? X86GetScalar (context, 0x43E0000000000000L)
  996. : X86GetAllElements(context, 0x43E0000000000000L);
  997. nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  998. Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nLong, nRes);
  999. if (scalar)
  1000. {
  1001. dRes = context.VectorZeroUpper64(dRes);
  1002. }
  1003. context.Copy(GetVec(op.Rd), dRes);
  1004. }
  1005. }
  1006. private static void EmitSse41FcvtuOpF(ArmEmitterContext context, FPRoundingMode roundMode, bool scalar)
  1007. {
  1008. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  1009. Operand n = GetVec(op.Rn);
  1010. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  1011. int sizeF = op.Size & 1;
  1012. if (sizeF == 0)
  1013. {
  1014. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, n, n, Const((int)CmpCondition.OrderedQ));
  1015. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1016. if (op is OpCodeSimdShImm fixedOp)
  1017. {
  1018. int fBits = GetImmShr(fixedOp);
  1019. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, fBits)
  1020. int fpScaled = 0x3F800000 + fBits * 0x800000;
  1021. Operand fpScaledMask = scalar
  1022. ? X86GetScalar (context, fpScaled)
  1023. : X86GetAllElements(context, fpScaled);
  1024. nRes = context.AddIntrinsic(Intrinsic.X86Mulps, nRes, fpScaledMask);
  1025. }
  1026. nRes = context.AddIntrinsic(Intrinsic.X86Roundps, nRes, Const(X86GetRoundControl(roundMode)));
  1027. Operand zero = context.VectorZero();
  1028. Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1029. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1030. Operand fpMaxValMask = scalar // 2.14748365E9f (2147483648)
  1031. ? X86GetScalar (context, 0x4F000000)
  1032. : X86GetAllElements(context, 0x4F000000);
  1033. Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes);
  1034. nRes = context.AddIntrinsic(Intrinsic.X86Subps, nRes, fpMaxValMask);
  1035. nCmp = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1036. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1037. Operand nInt2 = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes);
  1038. nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1039. Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nInt2, nRes);
  1040. dRes = context.AddIntrinsic(Intrinsic.X86Paddd, dRes, nInt);
  1041. if (scalar)
  1042. {
  1043. dRes = context.VectorZeroUpper96(dRes);
  1044. }
  1045. else if (op.RegisterSize == RegisterSize.Simd64)
  1046. {
  1047. dRes = context.VectorZeroUpper64(dRes);
  1048. }
  1049. context.Copy(GetVec(op.Rd), dRes);
  1050. }
  1051. else /* if (sizeF == 1) */
  1052. {
  1053. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, n, n, Const((int)CmpCondition.OrderedQ));
  1054. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1055. if (op is OpCodeSimdShImm fixedOp)
  1056. {
  1057. int fBits = GetImmShr(fixedOp);
  1058. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, fBits)
  1059. long fpScaled = 0x3FF0000000000000L + fBits * 0x10000000000000L;
  1060. Operand fpScaledMask = scalar
  1061. ? X86GetScalar (context, fpScaled)
  1062. : X86GetAllElements(context, fpScaled);
  1063. nRes = context.AddIntrinsic(Intrinsic.X86Mulpd, nRes, fpScaledMask);
  1064. }
  1065. nRes = context.AddIntrinsic(Intrinsic.X86Roundpd, nRes, Const(X86GetRoundControl(roundMode)));
  1066. Operand zero = context.VectorZero();
  1067. Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1068. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1069. Operand fpMaxValMask = scalar // 9.2233720368547760E18d (9223372036854775808)
  1070. ? X86GetScalar (context, 0x43E0000000000000L)
  1071. : X86GetAllElements(context, 0x43E0000000000000L);
  1072. Operand nLong = EmitSse2CvtDoubleToInt64OpF(context, nRes, scalar);
  1073. nRes = context.AddIntrinsic(Intrinsic.X86Subpd, nRes, fpMaxValMask);
  1074. nCmp = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1075. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1076. Operand nLong2 = EmitSse2CvtDoubleToInt64OpF(context, nRes, scalar);
  1077. nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1078. Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nLong2, nRes);
  1079. dRes = context.AddIntrinsic(Intrinsic.X86Paddq, dRes, nLong);
  1080. if (scalar)
  1081. {
  1082. dRes = context.VectorZeroUpper64(dRes);
  1083. }
  1084. context.Copy(GetVec(op.Rd), dRes);
  1085. }
  1086. }
  1087. private static void EmitSse41Fcvts_Gp(ArmEmitterContext context, FPRoundingMode roundMode, bool isFixed)
  1088. {
  1089. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  1090. Operand n = GetVec(op.Rn);
  1091. if (op.Size == 0)
  1092. {
  1093. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, n, n, Const((int)CmpCondition.OrderedQ));
  1094. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1095. if (isFixed)
  1096. {
  1097. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, op.FBits)
  1098. int fpScaled = 0x3F800000 + op.FBits * 0x800000;
  1099. Operand fpScaledMask = X86GetScalar(context, fpScaled);
  1100. nRes = context.AddIntrinsic(Intrinsic.X86Mulss, nRes, fpScaledMask);
  1101. }
  1102. nRes = context.AddIntrinsic(Intrinsic.X86Roundss, nRes, Const(X86GetRoundControl(roundMode)));
  1103. Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
  1104. ? context.AddIntrinsicInt (Intrinsic.X86Cvtss2si, nRes)
  1105. : context.AddIntrinsicLong(Intrinsic.X86Cvtss2si, nRes);
  1106. int fpMaxVal = op.RegisterSize == RegisterSize.Int32
  1107. ? 0x4F000000 // 2.14748365E9f (2147483648)
  1108. : 0x5F000000; // 9.223372E18f (9223372036854775808)
  1109. Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
  1110. nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1111. Operand nInt = context.AddIntrinsicInt(Intrinsic.X86Cvtsi2si, nRes);
  1112. if (op.RegisterSize == RegisterSize.Int64)
  1113. {
  1114. nInt = context.SignExtend32(OperandType.I64, nInt);
  1115. }
  1116. Operand dRes = context.BitwiseExclusiveOr(nIntOrLong, nInt);
  1117. SetIntOrZR(context, op.Rd, dRes);
  1118. }
  1119. else /* if (op.Size == 1) */
  1120. {
  1121. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, n, n, Const((int)CmpCondition.OrderedQ));
  1122. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1123. if (isFixed)
  1124. {
  1125. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, op.FBits)
  1126. long fpScaled = 0x3FF0000000000000L + op.FBits * 0x10000000000000L;
  1127. Operand fpScaledMask = X86GetScalar(context, fpScaled);
  1128. nRes = context.AddIntrinsic(Intrinsic.X86Mulsd, nRes, fpScaledMask);
  1129. }
  1130. nRes = context.AddIntrinsic(Intrinsic.X86Roundsd, nRes, Const(X86GetRoundControl(roundMode)));
  1131. Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
  1132. ? context.AddIntrinsicInt (Intrinsic.X86Cvtsd2si, nRes)
  1133. : context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRes);
  1134. long fpMaxVal = op.RegisterSize == RegisterSize.Int32
  1135. ? 0x41E0000000000000L // 2147483648.0000000d (2147483648)
  1136. : 0x43E0000000000000L; // 9.2233720368547760E18d (9223372036854775808)
  1137. Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
  1138. nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1139. Operand nLong = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, nRes);
  1140. if (op.RegisterSize == RegisterSize.Int32)
  1141. {
  1142. nLong = context.ConvertI64ToI32(nLong);
  1143. }
  1144. Operand dRes = context.BitwiseExclusiveOr(nIntOrLong, nLong);
  1145. SetIntOrZR(context, op.Rd, dRes);
  1146. }
  1147. }
  1148. private static void EmitSse41Fcvtu_Gp(ArmEmitterContext context, FPRoundingMode roundMode, bool isFixed)
  1149. {
  1150. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  1151. Operand n = GetVec(op.Rn);
  1152. if (op.Size == 0)
  1153. {
  1154. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, n, n, Const((int)CmpCondition.OrderedQ));
  1155. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1156. if (isFixed)
  1157. {
  1158. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, op.FBits)
  1159. int fpScaled = 0x3F800000 + op.FBits * 0x800000;
  1160. Operand fpScaledMask = X86GetScalar(context, fpScaled);
  1161. nRes = context.AddIntrinsic(Intrinsic.X86Mulss, nRes, fpScaledMask);
  1162. }
  1163. nRes = context.AddIntrinsic(Intrinsic.X86Roundss, nRes, Const(X86GetRoundControl(roundMode)));
  1164. Operand zero = context.VectorZero();
  1165. Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1166. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1167. int fpMaxVal = op.RegisterSize == RegisterSize.Int32
  1168. ? 0x4F000000 // 2.14748365E9f (2147483648)
  1169. : 0x5F000000; // 9.223372E18f (9223372036854775808)
  1170. Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
  1171. Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
  1172. ? context.AddIntrinsicInt (Intrinsic.X86Cvtss2si, nRes)
  1173. : context.AddIntrinsicLong(Intrinsic.X86Cvtss2si, nRes);
  1174. nRes = context.AddIntrinsic(Intrinsic.X86Subss, nRes, fpMaxValMask);
  1175. nCmp = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1176. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1177. Operand nIntOrLong2 = op.RegisterSize == RegisterSize.Int32
  1178. ? context.AddIntrinsicInt (Intrinsic.X86Cvtss2si, nRes)
  1179. : context.AddIntrinsicLong(Intrinsic.X86Cvtss2si, nRes);
  1180. nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1181. Operand nInt = context.AddIntrinsicInt(Intrinsic.X86Cvtsi2si, nRes);
  1182. if (op.RegisterSize == RegisterSize.Int64)
  1183. {
  1184. nInt = context.SignExtend32(OperandType.I64, nInt);
  1185. }
  1186. Operand dRes = context.BitwiseExclusiveOr(nIntOrLong2, nInt);
  1187. dRes = context.Add(dRes, nIntOrLong);
  1188. SetIntOrZR(context, op.Rd, dRes);
  1189. }
  1190. else /* if (op.Size == 1) */
  1191. {
  1192. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, n, n, Const((int)CmpCondition.OrderedQ));
  1193. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1194. if (isFixed)
  1195. {
  1196. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, op.FBits)
  1197. long fpScaled = 0x3FF0000000000000L + op.FBits * 0x10000000000000L;
  1198. Operand fpScaledMask = X86GetScalar(context, fpScaled);
  1199. nRes = context.AddIntrinsic(Intrinsic.X86Mulsd, nRes, fpScaledMask);
  1200. }
  1201. nRes = context.AddIntrinsic(Intrinsic.X86Roundsd, nRes, Const(X86GetRoundControl(roundMode)));
  1202. Operand zero = context.VectorZero();
  1203. Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1204. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1205. long fpMaxVal = op.RegisterSize == RegisterSize.Int32
  1206. ? 0x41E0000000000000L // 2147483648.0000000d (2147483648)
  1207. : 0x43E0000000000000L; // 9.2233720368547760E18d (9223372036854775808)
  1208. Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
  1209. Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
  1210. ? context.AddIntrinsicInt (Intrinsic.X86Cvtsd2si, nRes)
  1211. : context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRes);
  1212. nRes = context.AddIntrinsic(Intrinsic.X86Subsd, nRes, fpMaxValMask);
  1213. nCmp = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1214. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1215. Operand nIntOrLong2 = op.RegisterSize == RegisterSize.Int32
  1216. ? context.AddIntrinsicInt (Intrinsic.X86Cvtsd2si, nRes)
  1217. : context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRes);
  1218. nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1219. Operand nLong = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, nRes);
  1220. if (op.RegisterSize == RegisterSize.Int32)
  1221. {
  1222. nLong = context.ConvertI64ToI32(nLong);
  1223. }
  1224. Operand dRes = context.BitwiseExclusiveOr(nIntOrLong2, nLong);
  1225. dRes = context.Add(dRes, nIntOrLong);
  1226. SetIntOrZR(context, op.Rd, dRes);
  1227. }
  1228. }
  1229. private static Operand EmitVectorLongExtract(ArmEmitterContext context, int reg, int index, int size)
  1230. {
  1231. OperandType type = size == 3 ? OperandType.I64 : OperandType.I32;
  1232. return context.VectorExtract(type, GetVec(reg), index);
  1233. }
  1234. }
  1235. }