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AInst.cs
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9670c096e4
Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now)
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8 lat temu |
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AInstEmitAlu.cs
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c99b2884e4
Remove broken adds/cmn with condition check optimization (#218)
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8 lat temu |
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AInstEmitAluHelper.cs
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708761963e
Fix corner cases of ADCS and SBFM
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8 lat temu |
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AInstEmitBfm.cs
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708761963e
Fix corner cases of ADCS and SBFM
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8 lat temu |
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AInstEmitCcmp.cs
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62b827f474
Split main project into core,graphics and chocolarm4 subproject (#29)
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8 lat temu |
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AInstEmitCsel.cs
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950011c90f
Added initial support for function names from symbol table on the cpu with tracing, fix wrong ImageEnd on executables with MOD0, fix issue on the CPU on input elimination for instruction with more than one register store
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8 lat temu |
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AInstEmitException.cs
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65105c2a3b
Implement SvcGetThreadContext3
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8 lat temu |
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AInstEmitFlow.cs
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bd9b1e2c6b
Stub a few services, add support for generating call stacks on the CPU
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8 lat temu |
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AInstEmitHash.cs
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8f6387128a
Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
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8 lat temu |
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AInstEmitMemory.cs
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4731c7545d
Fix mistake on astc conversion, make some static methods that shouldn't be public private, remove old commmented out code
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8 lat temu |
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AInstEmitMemoryEx.cs
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3e6afeb513
Fix some thread sync issues (#172)
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8 lat temu |
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AInstEmitMemoryHelper.cs
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a8ba340dde
Improved logging (#103)
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8 lat temu |
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AInstEmitMove.cs
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62b827f474
Split main project into core,graphics and chocolarm4 subproject (#29)
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8 lat temu |
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AInstEmitMul.cs
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62b827f474
Split main project into core,graphics and chocolarm4 subproject (#29)
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8 lat temu |
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AInstEmitSimdArithmetic.cs
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063fae50fe
Fix EmitHighNarrow(), EmitSaturatingNarrowOp() when Rd == Rn || Rd == Rm (& Part != 0). Optimization of EmitVectorTranspose(), EmitVectorUnzip(), EmitVectorZip() algorithms (reduction of the number of operations and their complexity). Add 12 Tests about Trn1/2, Uzp1/2, Zip1/2 (V) instructions. (#268)
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7 lat temu |
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AInstEmitSimdCmp.cs
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514218ab98
Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225)
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7 lat temu |
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AInstEmitSimdCvt.cs
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514218ab98
Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225)
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7 lat temu |
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AInstEmitSimdHelper.cs
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063fae50fe
Fix EmitHighNarrow(), EmitSaturatingNarrowOp() when Rd == Rn || Rd == Rm (& Part != 0). Optimization of EmitVectorTranspose(), EmitVectorUnzip(), EmitVectorZip() algorithms (reduction of the number of operations and their complexity). Add 12 Tests about Trn1/2, Uzp1/2, Zip1/2 (V) instructions. (#268)
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7 lat temu |
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AInstEmitSimdLogical.cs
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514218ab98
Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225)
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7 lat temu |
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AInstEmitSimdMemory.cs
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514218ab98
Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225)
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7 lat temu |
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AInstEmitSimdMove.cs
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063fae50fe
Fix EmitHighNarrow(), EmitSaturatingNarrowOp() when Rd == Rn || Rd == Rm (& Part != 0). Optimization of EmitVectorTranspose(), EmitVectorUnzip(), EmitVectorZip() algorithms (reduction of the number of operations and their complexity). Add 12 Tests about Trn1/2, Uzp1/2, Zip1/2 (V) instructions. (#268)
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7 lat temu |
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AInstEmitSimdShift.cs
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514218ab98
Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225)
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7 lat temu |
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AInstEmitSystem.cs
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2ed24af756
Add pl:u stub, use higher precision on CNTPCT_EL0 register tick count
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8 lat temu |
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AInstEmitter.cs
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62b827f474
Split main project into core,graphics and chocolarm4 subproject (#29)
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8 lat temu |
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AInstInterpreter.cs
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9670c096e4
Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now)
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8 lat temu |
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ASoftFallback.cs
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be31f5b46d
Improve CountLeadingZeros() algorithm, nits. (#219)
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7 lat temu |
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ASoftFloat.cs
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b233ae964f
AInstEmitSimdCvt: Half-precision to single-precision conversion (#235)
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7 lat temu |
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AVectorHelper.cs
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c228cf320d
Add Rbit_V instruction. Add 8 tests (Rbit_V; Rev16_V, Rev32_V, Rev64_V). Improve CountSetBits8() algorithm. (#212)
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8 lat temu |
LDj3SNuD
063fae50fe
Fix EmitHighNarrow(), EmitSaturatingNarrowOp() when Rd == Rn || Rd == Rm (& Part != 0). Optimization of EmitVectorTranspose(), EmitVectorUnzip(), EmitVectorZip() algorithms (reduction of the number of operations and their complexity). Add 12 Tests about Trn1/2, Uzp1/2, Zip1/2 (V) instructions. (#268)