Decoder.cs 12 KB

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  1. using ARMeilleure.Instructions;
  2. using ARMeilleure.Memory;
  3. using ARMeilleure.State;
  4. using System;
  5. using System.Collections.Concurrent;
  6. using System.Collections.Generic;
  7. using System.Reflection.Emit;
  8. namespace ARMeilleure.Decoders
  9. {
  10. static class Decoder
  11. {
  12. // We define a limit on the number of instructions that a function may have,
  13. // this prevents functions being potentially too large, which would
  14. // take too long to compile and use too much memory.
  15. private const int MaxInstsPerFunction = 5000;
  16. private delegate object MakeOp(InstDescriptor inst, ulong address, int opCode);
  17. private static ConcurrentDictionary<Type, MakeOp> _opActivators;
  18. static Decoder()
  19. {
  20. _opActivators = new ConcurrentDictionary<Type, MakeOp>();
  21. }
  22. public static Block[] DecodeBasicBlock(MemoryManager memory, ulong address, ExecutionMode mode)
  23. {
  24. Block block = new Block(address);
  25. FillBlock(memory, mode, block, ulong.MaxValue);
  26. return new Block[] { block };
  27. }
  28. public static Block[] DecodeFunction(MemoryManager memory, ulong address, ExecutionMode mode)
  29. {
  30. List<Block> blocks = new List<Block>();
  31. Queue<Block> workQueue = new Queue<Block>();
  32. Dictionary<ulong, Block> visited = new Dictionary<ulong, Block>();
  33. int opsCount = 0;
  34. Block GetBlock(ulong blkAddress)
  35. {
  36. if (!visited.TryGetValue(blkAddress, out Block block))
  37. {
  38. if (opsCount > MaxInstsPerFunction)
  39. {
  40. return null;
  41. }
  42. block = new Block(blkAddress);
  43. workQueue.Enqueue(block);
  44. visited.Add(blkAddress, block);
  45. }
  46. return block;
  47. }
  48. GetBlock(address);
  49. while (workQueue.TryDequeue(out Block currBlock))
  50. {
  51. // Check if the current block is inside another block.
  52. if (BinarySearch(blocks, currBlock.Address, out int nBlkIndex))
  53. {
  54. Block nBlock = blocks[nBlkIndex];
  55. if (nBlock.Address == currBlock.Address)
  56. {
  57. throw new InvalidOperationException("Found duplicate block address on the list.");
  58. }
  59. nBlock.Split(currBlock);
  60. blocks.Insert(nBlkIndex + 1, currBlock);
  61. continue;
  62. }
  63. // If we have a block after the current one, set the limit address.
  64. ulong limitAddress = ulong.MaxValue;
  65. if (nBlkIndex != blocks.Count)
  66. {
  67. Block nBlock = blocks[nBlkIndex];
  68. int nextIndex = nBlkIndex + 1;
  69. if (nBlock.Address < currBlock.Address && nextIndex < blocks.Count)
  70. {
  71. limitAddress = blocks[nextIndex].Address;
  72. }
  73. else if (nBlock.Address > currBlock.Address)
  74. {
  75. limitAddress = blocks[nBlkIndex].Address;
  76. }
  77. }
  78. FillBlock(memory, mode, currBlock, limitAddress);
  79. opsCount += currBlock.OpCodes.Count;
  80. if (currBlock.OpCodes.Count != 0)
  81. {
  82. // Set child blocks. "Branch" is the block the branch instruction
  83. // points to (when taken), "Next" is the block at the next address,
  84. // executed when the branch is not taken. For Unconditional Branches
  85. // (except BL/BLR that are sub calls) or end of executable, Next is null.
  86. OpCode lastOp = currBlock.GetLastOp();
  87. bool isCall = IsCall(lastOp);
  88. if (lastOp is IOpCodeBImm op && !isCall)
  89. {
  90. currBlock.Branch = GetBlock((ulong)op.Immediate);
  91. }
  92. if (!IsUnconditionalBranch(lastOp) /*|| isCall*/)
  93. {
  94. currBlock.Next = GetBlock(currBlock.EndAddress);
  95. }
  96. }
  97. // Insert the new block on the list (sorted by address).
  98. if (blocks.Count != 0)
  99. {
  100. Block nBlock = blocks[nBlkIndex];
  101. blocks.Insert(nBlkIndex + (nBlock.Address < currBlock.Address ? 1 : 0), currBlock);
  102. }
  103. else
  104. {
  105. blocks.Add(currBlock);
  106. }
  107. }
  108. return blocks.ToArray();
  109. }
  110. private static bool BinarySearch(List<Block> blocks, ulong address, out int index)
  111. {
  112. index = 0;
  113. int left = 0;
  114. int right = blocks.Count - 1;
  115. while (left <= right)
  116. {
  117. int size = right - left;
  118. int middle = left + (size >> 1);
  119. Block block = blocks[middle];
  120. index = middle;
  121. if (address >= block.Address && address < block.EndAddress)
  122. {
  123. return true;
  124. }
  125. if (address < block.Address)
  126. {
  127. right = middle - 1;
  128. }
  129. else
  130. {
  131. left = middle + 1;
  132. }
  133. }
  134. return false;
  135. }
  136. private static void FillBlock(
  137. MemoryManager memory,
  138. ExecutionMode mode,
  139. Block block,
  140. ulong limitAddress)
  141. {
  142. ulong address = block.Address;
  143. OpCode opCode;
  144. do
  145. {
  146. if (address >= limitAddress)
  147. {
  148. break;
  149. }
  150. opCode = DecodeOpCode(memory, address, mode);
  151. block.OpCodes.Add(opCode);
  152. address += (ulong)opCode.OpCodeSizeInBytes;
  153. }
  154. while (!(IsBranch(opCode) || IsException(opCode)));
  155. block.EndAddress = address;
  156. }
  157. private static bool IsBranch(OpCode opCode)
  158. {
  159. return opCode is OpCodeBImm ||
  160. opCode is OpCodeBReg || IsAarch32Branch(opCode);
  161. }
  162. private static bool IsUnconditionalBranch(OpCode opCode)
  163. {
  164. return opCode is OpCodeBImmAl ||
  165. opCode is OpCodeBReg || IsAarch32UnconditionalBranch(opCode);
  166. }
  167. private static bool IsAarch32UnconditionalBranch(OpCode opCode)
  168. {
  169. if (!(opCode is OpCode32 op))
  170. {
  171. return false;
  172. }
  173. // Note: On ARM32, most instructions have conditional execution,
  174. // so there's no "Always" (unconditional) branch like on ARM64.
  175. // We need to check if the condition is "Always" instead.
  176. return IsAarch32Branch(op) && op.Cond >= Condition.Al;
  177. }
  178. private static bool IsAarch32Branch(OpCode opCode)
  179. {
  180. // Note: On ARM32, most ALU operations can write to R15 (PC),
  181. // so we must consider such operations as a branch in potential aswell.
  182. if (opCode is IOpCode32Alu opAlu && opAlu.Rd == RegisterAlias.Aarch32Pc)
  183. {
  184. return true;
  185. }
  186. // Same thing for memory operations. We have the cases where PC is a target
  187. // register (Rt == 15 or (mask & (1 << 15)) != 0), and cases where there is
  188. // a write back to PC (wback == true && Rn == 15), however the later may
  189. // be "undefined" depending on the CPU, so compilers should not produce that.
  190. if (opCode is IOpCode32Mem || opCode is IOpCode32MemMult)
  191. {
  192. int rt, rn;
  193. bool wBack, isLoad;
  194. if (opCode is IOpCode32Mem opMem)
  195. {
  196. rt = opMem.Rt;
  197. rn = opMem.Rn;
  198. wBack = opMem.WBack;
  199. isLoad = opMem.IsLoad;
  200. // For the dual load, we also need to take into account the
  201. // case were Rt2 == 15 (PC).
  202. if (rt == 14 && opMem.Instruction.Name == InstName.Ldrd)
  203. {
  204. rt = RegisterAlias.Aarch32Pc;
  205. }
  206. }
  207. else if (opCode is IOpCode32MemMult opMemMult)
  208. {
  209. const int pcMask = 1 << RegisterAlias.Aarch32Pc;
  210. rt = (opMemMult.RegisterMask & pcMask) != 0 ? RegisterAlias.Aarch32Pc : 0;
  211. rn = opMemMult.Rn;
  212. wBack = opMemMult.PostOffset != 0;
  213. isLoad = opMemMult.IsLoad;
  214. }
  215. else
  216. {
  217. throw new NotImplementedException($"The type \"{opCode.GetType().Name}\" is not implemented on the decoder.");
  218. }
  219. if ((rt == RegisterAlias.Aarch32Pc && isLoad) ||
  220. (rn == RegisterAlias.Aarch32Pc && wBack))
  221. {
  222. return true;
  223. }
  224. }
  225. // Explicit branch instructions.
  226. return opCode is IOpCode32BImm ||
  227. opCode is IOpCode32BReg;
  228. }
  229. private static bool IsCall(OpCode opCode)
  230. {
  231. // TODO (CQ): ARM32 support.
  232. return opCode.Instruction.Name == InstName.Bl ||
  233. opCode.Instruction.Name == InstName.Blr;
  234. }
  235. private static bool IsException(OpCode opCode)
  236. {
  237. return opCode.Instruction.Name == InstName.Brk ||
  238. opCode.Instruction.Name == InstName.Svc ||
  239. opCode.Instruction.Name == InstName.Und;
  240. }
  241. public static OpCode DecodeOpCode(MemoryManager memory, ulong address, ExecutionMode mode)
  242. {
  243. int opCode = memory.ReadInt32((long)address);
  244. InstDescriptor inst;
  245. Type type;
  246. if (mode == ExecutionMode.Aarch64)
  247. {
  248. (inst, type) = OpCodeTable.GetInstA64(opCode);
  249. }
  250. else
  251. {
  252. if (mode == ExecutionMode.Aarch32Arm)
  253. {
  254. (inst, type) = OpCodeTable.GetInstA32(opCode);
  255. }
  256. else /* if (mode == ExecutionMode.Aarch32Thumb) */
  257. {
  258. (inst, type) = OpCodeTable.GetInstT32(opCode);
  259. }
  260. }
  261. if (type != null)
  262. {
  263. return MakeOpCode(inst, type, address, opCode);
  264. }
  265. else
  266. {
  267. return new OpCode(inst, address, opCode);
  268. }
  269. }
  270. private static OpCode MakeOpCode(InstDescriptor inst, Type type, ulong address, int opCode)
  271. {
  272. MakeOp createInstance = _opActivators.GetOrAdd(type, CacheOpActivator);
  273. return (OpCode)createInstance(inst, address, opCode);
  274. }
  275. private static MakeOp CacheOpActivator(Type type)
  276. {
  277. Type[] argTypes = new Type[] { typeof(InstDescriptor), typeof(ulong), typeof(int) };
  278. DynamicMethod mthd = new DynamicMethod($"Make{type.Name}", type, argTypes);
  279. ILGenerator generator = mthd.GetILGenerator();
  280. generator.Emit(OpCodes.Ldarg_0);
  281. generator.Emit(OpCodes.Ldarg_1);
  282. generator.Emit(OpCodes.Ldarg_2);
  283. generator.Emit(OpCodes.Newobj, type.GetConstructor(argTypes));
  284. generator.Emit(OpCodes.Ret);
  285. return (MakeOp)mthd.CreateDelegate(typeof(MakeOp));
  286. }
  287. }
  288. }