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CpuTest.cs
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9d7627af64
Add multi-level function table (#2228)
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4 anni fa |
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CpuTest32.cs
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bb2f9df0a1
KThread: Fix GetPsr mask (#3180)
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4 anni fa |
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CpuTestAlu.cs
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d87c5375f1
Implement a custom value generator for the Tests of the CLS and CLZ instructions (Base: 32, 64 bits. Simd: 8, 16, 32 bits). (#696)
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6 anni fa |
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CpuTestAlu32.cs
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86b37d0ff7
ARMeilleure: A32: Implement SHSUB8 and UHSUB8 (#3089)
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4 anni fa |
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CpuTestAluBinary.cs
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d7044b10a2
Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328)
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5 anni fa |
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CpuTestAluBinary32.cs
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d7044b10a2
Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328)
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5 anni fa |
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CpuTestAluImm.cs
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1e7ea76f14
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
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7 anni fa |
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CpuTestAluImm32.cs
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b97ff4da5e
A32: Fix ALU immediate instructions (#3179)
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4 anni fa |
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CpuTestAluRs.cs
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a731ab3a2a
Add a new JIT compiler for CPU code (#693)
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6 anni fa |
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CpuTestAluRs32.cs
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b1b6f294f2
Add most of the A32 instruction set to ARMeilleure (#897)
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6 anni fa |
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CpuTestAluRx.cs
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1e7ea76f14
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
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7 anni fa |
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CpuTestBf32.cs
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b1b6f294f2
Add most of the A32 instruction set to ARMeilleure (#897)
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6 anni fa |
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CpuTestBfm.cs
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1e7ea76f14
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
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7 anni fa |
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CpuTestCcmpImm.cs
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1e7ea76f14
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
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7 anni fa |
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CpuTestCcmpReg.cs
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1e7ea76f14
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
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7 anni fa |
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CpuTestCsel.cs
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1e7ea76f14
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
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7 anni fa |
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CpuTestMisc.cs
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a804db6eed
Add Fmax/minv_V & S/Ushl_S Inst.s with Tests. Fix Maxps/d & Minps/d d… (#1335)
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5 anni fa |
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CpuTestMisc32.cs
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e36e97c64d
CPU: This PR fixes Fpscr, among other things. (#1433)
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5 anni fa |
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CpuTestMov.cs
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d87c5375f1
Implement a custom value generator for the Tests of the CLS and CLZ instructions (Base: 32, 64 bits. Simd: 8, 16, 32 bits). (#696)
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6 anni fa |
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CpuTestMul.cs
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1e7ea76f14
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
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7 anni fa |
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CpuTestMul32.cs
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fb0939f9b6
Add SSAT, SSAT16, USAT and USAT16 ARM32 instructions (#954)
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6 anni fa |
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CpuTestSimd.cs
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e5f7ff1eee
CPU - Implement FCVTMS (Vector) (#2937)
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4 anni fa |
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CpuTestSimd32.cs
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9bda7b4699
Implement VCNT instruction (#1963)
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5 anni fa |
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CpuTestSimdCrypto.cs
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a731ab3a2a
Add a new JIT compiler for CPU code (#693)
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6 anni fa |
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CpuTestSimdCrypto32.cs
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dd433c1296
Implement AESMC, AESIMC, AESE, AESD and VEOR AArch32 instructions (#982)
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6 anni fa |
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CpuTestSimdCvt.cs
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60f7cba30a
Implement FCVTNS (Scalar GP) (#2953)
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4 anni fa |
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CpuTestSimdCvt32.cs
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8a33e884f8
Fix Vnmls_S fast path (F64: losing input d value). Fix Vnmla_S & Vnmls_S slow paths (using fused inst.s). Fix Vfma_V slow path not using StandardFPSCRValue(). (#1775)
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5 anni fa |
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CpuTestSimdExt.cs
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a731ab3a2a
Add a new JIT compiler for CPU code (#693)
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6 anni fa |
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CpuTestSimdFcond.cs
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a731ab3a2a
Add a new JIT compiler for CPU code (#693)
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6 anni fa |
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CpuTestSimdFmov.cs
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a731ab3a2a
Add a new JIT compiler for CPU code (#693)
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6 anni fa |
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CpuTestSimdImm.cs
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a731ab3a2a
Add a new JIT compiler for CPU code (#693)
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6 anni fa |
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CpuTestSimdIns.cs
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a731ab3a2a
Add a new JIT compiler for CPU code (#693)
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6 anni fa |
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CpuTestSimdLogical32.cs
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ab9d4b862d
Implement VORN (register) Arm32 instruction (#2396)
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4 anni fa |
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CpuTestSimdMemory32.cs
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e36e97c64d
CPU: This PR fixes Fpscr, among other things. (#1433)
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5 anni fa |
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CpuTestSimdMov32.cs
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9a49f8aec9
Fix VMVN (immediate), Add VPMIN, VPMAX, VMVN (register) (#1303)
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5 anni fa |
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CpuTestSimdReg.cs
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430ba6da65
CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)
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5 anni fa |
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CpuTestSimdReg32.cs
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430ba6da65
CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)
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5 anni fa |
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CpuTestSimdRegElem.cs
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4bd1ad16f9
Add Sqdmulh_Ve & Sqrdmulh_Ve Inst.s with Tests. (#2139)
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5 anni fa |
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CpuTestSimdRegElem32.cs
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c26f3774bd
Implement VMULL, VMLSL, VRSHR, VQRSHRN, VQRSHRUN AArch32 instructions + other fixes (#977)
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6 anni fa |
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CpuTestSimdRegElemF.cs
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a731ab3a2a
Add a new JIT compiler for CPU code (#693)
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6 anni fa |
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CpuTestSimdShImm.cs
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2cb8bd7006
CPU (A64): Add Scvtf_S_Fixed & Ucvtf_S_Fixed with Tests. (#1492)
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5 anni fa |
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CpuTestSimdShImm32.cs
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e36e97c64d
CPU: This PR fixes Fpscr, among other things. (#1433)
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5 anni fa |
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CpuTestSimdTbl.cs
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16869402bf
Add Tbx Inst. (fast & slow paths), with Tests. (#782)
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6 anni fa |
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CpuTestSystem.cs
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7c111a3567
Add Mrs & Msr (Nzcv) Inst., with Tests. (#819)
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6 anni fa |
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CpuTestT32Alu.cs
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7af9fcbc06
T32: Implement Data Processing (Modified Immediate) instructions (#3178)
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4 anni fa |
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CpuTestT32Flow.cs
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bd9ac0fdaa
T32: Implement B, B.cond, BL, BLX (#3155)
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4 anni fa |
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CpuTestThumb.cs
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7b35ebc64a
T32: Implement ALU (shifted register) instructions (#3135)
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4 anni fa |
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PrecomputedThumbTestCase.cs
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7b35ebc64a
T32: Implement ALU (shifted register) instructions (#3135)
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4 anni fa |
merry