InstEmitSimdCvt.cs 54 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504
  1. using ARMeilleure.Decoders;
  2. using ARMeilleure.IntermediateRepresentation;
  3. using ARMeilleure.State;
  4. using ARMeilleure.Translation;
  5. using System;
  6. using System.Diagnostics;
  7. using System.Reflection;
  8. using static ARMeilleure.Instructions.InstEmitHelper;
  9. using static ARMeilleure.Instructions.InstEmitSimdHelper;
  10. using static ARMeilleure.IntermediateRepresentation.OperandHelper;
  11. namespace ARMeilleure.Instructions
  12. {
  13. using Func1I = Func<Operand, Operand>;
  14. static partial class InstEmit
  15. {
  16. public static void Fcvt_S(ArmEmitterContext context)
  17. {
  18. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  19. if (op.Size == 0 && op.Opc == 1) // Single -> Double.
  20. {
  21. if (Optimizations.UseSse2)
  22. {
  23. Operand n = GetVec(op.Rn);
  24. Operand res = context.AddIntrinsic(Intrinsic.X86Cvtss2sd, context.VectorZero(), n);
  25. context.Copy(GetVec(op.Rd), res);
  26. }
  27. else
  28. {
  29. Operand ne = context.VectorExtract(OperandType.FP32, GetVec(op.Rn), 0);
  30. Operand res = context.ConvertToFP(OperandType.FP64, ne);
  31. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  32. }
  33. }
  34. else if (op.Size == 1 && op.Opc == 0) // Double -> Single.
  35. {
  36. if (Optimizations.UseSse2)
  37. {
  38. Operand n = GetVec(op.Rn);
  39. Operand res = context.AddIntrinsic(Intrinsic.X86Cvtsd2ss, context.VectorZero(), n);
  40. context.Copy(GetVec(op.Rd), res);
  41. }
  42. else
  43. {
  44. Operand ne = context.VectorExtract(OperandType.FP64, GetVec(op.Rn), 0);
  45. Operand res = context.ConvertToFP(OperandType.FP32, ne);
  46. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  47. }
  48. }
  49. else if (op.Size == 0 && op.Opc == 3) // Single -> Half.
  50. {
  51. Operand ne = context.VectorExtract(OperandType.FP32, GetVec(op.Rn), 0);
  52. Operand res = context.Call(typeof(SoftFloat32_16).GetMethod(nameof(SoftFloat32_16.FPConvert)), ne);
  53. res = context.ZeroExtend16(OperandType.I64, res);
  54. context.Copy(GetVec(op.Rd), EmitVectorInsert(context, context.VectorZero(), res, 0, 1));
  55. }
  56. else if (op.Size == 3 && op.Opc == 0) // Half -> Single.
  57. {
  58. Operand ne = EmitVectorExtractZx(context, op.Rn, 0, 1);
  59. Operand res = context.Call(typeof(SoftFloat16_32).GetMethod(nameof(SoftFloat16_32.FPConvert)), ne);
  60. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  61. }
  62. else if (op.Size == 1 && op.Opc == 3) // Double -> Half.
  63. {
  64. throw new NotImplementedException("Double-precision to half-precision.");
  65. }
  66. else if (op.Size == 3 && op.Opc == 1) // Double -> Half.
  67. {
  68. throw new NotImplementedException("Half-precision to double-precision.");
  69. }
  70. else // Invalid encoding.
  71. {
  72. Debug.Assert(false, $"type == {op.Size} && opc == {op.Opc}");
  73. }
  74. }
  75. public static void Fcvtas_Gp(ArmEmitterContext context)
  76. {
  77. EmitFcvt_s_Gp(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1));
  78. }
  79. public static void Fcvtas_S(ArmEmitterContext context)
  80. {
  81. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1), signed: true, scalar: true);
  82. }
  83. public static void Fcvtas_V(ArmEmitterContext context)
  84. {
  85. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1), signed: true, scalar: false);
  86. }
  87. public static void Fcvtau_Gp(ArmEmitterContext context)
  88. {
  89. EmitFcvt_u_Gp(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1));
  90. }
  91. public static void Fcvtau_S(ArmEmitterContext context)
  92. {
  93. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1), signed: false, scalar: true);
  94. }
  95. public static void Fcvtau_V(ArmEmitterContext context)
  96. {
  97. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1), signed: false, scalar: false);
  98. }
  99. public static void Fcvtl_V(ArmEmitterContext context)
  100. {
  101. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  102. int sizeF = op.Size & 1;
  103. if (Optimizations.UseSse2 && sizeF == 1)
  104. {
  105. Operand n = GetVec(op.Rn);
  106. Operand res;
  107. if (op.RegisterSize == RegisterSize.Simd128)
  108. {
  109. res = context.AddIntrinsic(Intrinsic.X86Movhlps, n, n);
  110. }
  111. else
  112. {
  113. res = n;
  114. }
  115. res = context.AddIntrinsic(Intrinsic.X86Cvtps2pd, res);
  116. context.Copy(GetVec(op.Rd), res);
  117. }
  118. else
  119. {
  120. Operand res = context.VectorZero();
  121. int elems = 4 >> sizeF;
  122. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  123. for (int index = 0; index < elems; index++)
  124. {
  125. if (sizeF == 0)
  126. {
  127. Operand ne = EmitVectorExtractZx(context, op.Rn, part + index, 1);
  128. Operand e = context.Call(typeof(SoftFloat16_32).GetMethod(nameof(SoftFloat16_32.FPConvert)), ne);
  129. res = context.VectorInsert(res, e, index);
  130. }
  131. else /* if (sizeF == 1) */
  132. {
  133. Operand ne = context.VectorExtract(OperandType.FP32, GetVec(op.Rn), part + index);
  134. Operand e = context.ConvertToFP(OperandType.FP64, ne);
  135. res = context.VectorInsert(res, e, index);
  136. }
  137. }
  138. context.Copy(GetVec(op.Rd), res);
  139. }
  140. }
  141. public static void Fcvtms_Gp(ArmEmitterContext context)
  142. {
  143. if (Optimizations.UseSse41)
  144. {
  145. EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsMinusInfinity, isFixed: false);
  146. }
  147. else
  148. {
  149. EmitFcvt_s_Gp(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Floor), op1));
  150. }
  151. }
  152. public static void Fcvtmu_Gp(ArmEmitterContext context)
  153. {
  154. if (Optimizations.UseSse41)
  155. {
  156. EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsMinusInfinity, isFixed: false);
  157. }
  158. else
  159. {
  160. EmitFcvt_u_Gp(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Floor), op1));
  161. }
  162. }
  163. public static void Fcvtn_V(ArmEmitterContext context)
  164. {
  165. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  166. int sizeF = op.Size & 1;
  167. if (Optimizations.UseSse2 && sizeF == 1)
  168. {
  169. Operand d = GetVec(op.Rd);
  170. Operand res = context.VectorZeroUpper64(d);
  171. Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtpd2ps, GetVec(op.Rn));
  172. nInt = context.AddIntrinsic(Intrinsic.X86Movlhps, nInt, nInt);
  173. Intrinsic movInst = op.RegisterSize == RegisterSize.Simd128
  174. ? Intrinsic.X86Movlhps
  175. : Intrinsic.X86Movhlps;
  176. res = context.AddIntrinsic(movInst, res, nInt);
  177. context.Copy(d, res);
  178. }
  179. else
  180. {
  181. OperandType type = sizeF == 0 ? OperandType.FP32 : OperandType.FP64;
  182. int elems = 4 >> sizeF;
  183. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  184. Operand d = GetVec(op.Rd);
  185. Operand res = part == 0 ? context.VectorZero() : context.Copy(d);
  186. for (int index = 0; index < elems; index++)
  187. {
  188. Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
  189. if (sizeF == 0)
  190. {
  191. Operand e = context.Call(typeof(SoftFloat32_16).GetMethod(nameof(SoftFloat32_16.FPConvert)), ne);
  192. e = context.ZeroExtend16(OperandType.I64, e);
  193. res = EmitVectorInsert(context, res, e, part + index, 1);
  194. }
  195. else /* if (sizeF == 1) */
  196. {
  197. Operand e = context.ConvertToFP(OperandType.FP32, ne);
  198. res = context.VectorInsert(res, e, part + index);
  199. }
  200. }
  201. context.Copy(d, res);
  202. }
  203. }
  204. public static void Fcvtns_S(ArmEmitterContext context)
  205. {
  206. if (Optimizations.UseSse41)
  207. {
  208. EmitSse41FcvtsOpF(context, FPRoundingMode.ToNearest, scalar: true);
  209. }
  210. else
  211. {
  212. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1), signed: true, scalar: true);
  213. }
  214. }
  215. public static void Fcvtns_V(ArmEmitterContext context)
  216. {
  217. if (Optimizations.UseSse41)
  218. {
  219. EmitSse41FcvtsOpF(context, FPRoundingMode.ToNearest, scalar: false);
  220. }
  221. else
  222. {
  223. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1), signed: true, scalar: false);
  224. }
  225. }
  226. public static void Fcvtnu_S(ArmEmitterContext context)
  227. {
  228. if (Optimizations.UseSse41)
  229. {
  230. EmitSse41FcvtuOpF(context, FPRoundingMode.ToNearest, scalar: true);
  231. }
  232. else
  233. {
  234. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1), signed: false, scalar: true);
  235. }
  236. }
  237. public static void Fcvtnu_V(ArmEmitterContext context)
  238. {
  239. if (Optimizations.UseSse41)
  240. {
  241. EmitSse41FcvtuOpF(context, FPRoundingMode.ToNearest, scalar: false);
  242. }
  243. else
  244. {
  245. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1), signed: false, scalar: false);
  246. }
  247. }
  248. public static void Fcvtps_Gp(ArmEmitterContext context)
  249. {
  250. if (Optimizations.UseSse41)
  251. {
  252. EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsPlusInfinity, isFixed: false);
  253. }
  254. else
  255. {
  256. EmitFcvt_s_Gp(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Ceiling), op1));
  257. }
  258. }
  259. public static void Fcvtpu_Gp(ArmEmitterContext context)
  260. {
  261. if (Optimizations.UseSse41)
  262. {
  263. EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsPlusInfinity, isFixed: false);
  264. }
  265. else
  266. {
  267. EmitFcvt_u_Gp(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Ceiling), op1));
  268. }
  269. }
  270. public static void Fcvtzs_Gp(ArmEmitterContext context)
  271. {
  272. if (Optimizations.UseSse41)
  273. {
  274. EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsZero, isFixed: false);
  275. }
  276. else
  277. {
  278. EmitFcvt_s_Gp(context, (op1) => op1);
  279. }
  280. }
  281. public static void Fcvtzs_Gp_Fixed(ArmEmitterContext context)
  282. {
  283. if (Optimizations.UseSse41)
  284. {
  285. EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsZero, isFixed: true);
  286. }
  287. else
  288. {
  289. EmitFcvtzs_Gp_Fixed(context);
  290. }
  291. }
  292. public static void Fcvtzs_S(ArmEmitterContext context)
  293. {
  294. if (Optimizations.UseSse41)
  295. {
  296. EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsZero, scalar: true);
  297. }
  298. else
  299. {
  300. EmitFcvtz(context, signed: true, scalar: true);
  301. }
  302. }
  303. public static void Fcvtzs_V(ArmEmitterContext context)
  304. {
  305. if (Optimizations.UseSse41)
  306. {
  307. EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsZero, scalar: false);
  308. }
  309. else
  310. {
  311. EmitFcvtz(context, signed: true, scalar: false);
  312. }
  313. }
  314. public static void Fcvtzs_V_Fixed(ArmEmitterContext context)
  315. {
  316. if (Optimizations.UseSse41)
  317. {
  318. EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsZero, scalar: false);
  319. }
  320. else
  321. {
  322. EmitFcvtz(context, signed: true, scalar: false);
  323. }
  324. }
  325. public static void Fcvtzu_Gp(ArmEmitterContext context)
  326. {
  327. if (Optimizations.UseSse41)
  328. {
  329. EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsZero, isFixed: false);
  330. }
  331. else
  332. {
  333. EmitFcvt_u_Gp(context, (op1) => op1);
  334. }
  335. }
  336. public static void Fcvtzu_Gp_Fixed(ArmEmitterContext context)
  337. {
  338. if (Optimizations.UseSse41)
  339. {
  340. EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsZero, isFixed: true);
  341. }
  342. else
  343. {
  344. EmitFcvtzu_Gp_Fixed(context);
  345. }
  346. }
  347. public static void Fcvtzu_S(ArmEmitterContext context)
  348. {
  349. if (Optimizations.UseSse41)
  350. {
  351. EmitSse41FcvtuOpF(context, FPRoundingMode.TowardsZero, scalar: true);
  352. }
  353. else
  354. {
  355. EmitFcvtz(context, signed: false, scalar: true);
  356. }
  357. }
  358. public static void Fcvtzu_V(ArmEmitterContext context)
  359. {
  360. if (Optimizations.UseSse41)
  361. {
  362. EmitSse41FcvtuOpF(context, FPRoundingMode.TowardsZero, scalar: false);
  363. }
  364. else
  365. {
  366. EmitFcvtz(context, signed: false, scalar: false);
  367. }
  368. }
  369. public static void Fcvtzu_V_Fixed(ArmEmitterContext context)
  370. {
  371. if (Optimizations.UseSse41)
  372. {
  373. EmitSse41FcvtuOpF(context, FPRoundingMode.TowardsZero, scalar: false);
  374. }
  375. else
  376. {
  377. EmitFcvtz(context, signed: false, scalar: false);
  378. }
  379. }
  380. public static void Scvtf_Gp(ArmEmitterContext context)
  381. {
  382. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  383. Operand res = GetIntOrZR(context, op.Rn);
  384. if (op.RegisterSize == RegisterSize.Int32)
  385. {
  386. res = context.SignExtend32(OperandType.I64, res);
  387. }
  388. res = EmitFPConvert(context, res, op.Size, signed: true);
  389. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  390. }
  391. public static void Scvtf_Gp_Fixed(ArmEmitterContext context)
  392. {
  393. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  394. Operand res = GetIntOrZR(context, op.Rn);
  395. if (op.RegisterSize == RegisterSize.Int32)
  396. {
  397. res = context.SignExtend32(OperandType.I64, res);
  398. }
  399. res = EmitFPConvert(context, res, op.Size, signed: true);
  400. res = EmitI2fFBitsMul(context, res, op.FBits);
  401. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  402. }
  403. public static void Scvtf_S(ArmEmitterContext context)
  404. {
  405. if (Optimizations.UseSse2)
  406. {
  407. EmitSse2ScvtfOp(context, scalar: true);
  408. }
  409. else
  410. {
  411. EmitCvtf(context, signed: true, scalar: true);
  412. }
  413. }
  414. public static void Scvtf_S_Fixed(ArmEmitterContext context)
  415. {
  416. if (Optimizations.UseSse2)
  417. {
  418. EmitSse2ScvtfOp(context, scalar: true);
  419. }
  420. else
  421. {
  422. EmitCvtf(context, signed: true, scalar: true);
  423. }
  424. }
  425. public static void Scvtf_V(ArmEmitterContext context)
  426. {
  427. if (Optimizations.UseSse2)
  428. {
  429. EmitSse2ScvtfOp(context, scalar: false);
  430. }
  431. else
  432. {
  433. EmitCvtf(context, signed: true, scalar: false);
  434. }
  435. }
  436. public static void Scvtf_V_Fixed(ArmEmitterContext context)
  437. {
  438. if (Optimizations.UseSse2)
  439. {
  440. EmitSse2ScvtfOp(context, scalar: false);
  441. }
  442. else
  443. {
  444. EmitCvtf(context, signed: true, scalar: false);
  445. }
  446. }
  447. public static void Ucvtf_Gp(ArmEmitterContext context)
  448. {
  449. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  450. Operand res = GetIntOrZR(context, op.Rn);
  451. res = EmitFPConvert(context, res, op.Size, signed: false);
  452. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  453. }
  454. public static void Ucvtf_Gp_Fixed(ArmEmitterContext context)
  455. {
  456. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  457. Operand res = GetIntOrZR(context, op.Rn);
  458. res = EmitFPConvert(context, res, op.Size, signed: false);
  459. res = EmitI2fFBitsMul(context, res, op.FBits);
  460. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  461. }
  462. public static void Ucvtf_S(ArmEmitterContext context)
  463. {
  464. if (Optimizations.UseSse2)
  465. {
  466. EmitSse2UcvtfOp(context, scalar: true);
  467. }
  468. else
  469. {
  470. EmitCvtf(context, signed: false, scalar: true);
  471. }
  472. }
  473. public static void Ucvtf_S_Fixed(ArmEmitterContext context)
  474. {
  475. if (Optimizations.UseSse2)
  476. {
  477. EmitSse2UcvtfOp(context, scalar: true);
  478. }
  479. else
  480. {
  481. EmitCvtf(context, signed: false, scalar: true);
  482. }
  483. }
  484. public static void Ucvtf_V(ArmEmitterContext context)
  485. {
  486. if (Optimizations.UseSse2)
  487. {
  488. EmitSse2UcvtfOp(context, scalar: false);
  489. }
  490. else
  491. {
  492. EmitCvtf(context, signed: false, scalar: false);
  493. }
  494. }
  495. public static void Ucvtf_V_Fixed(ArmEmitterContext context)
  496. {
  497. if (Optimizations.UseSse2)
  498. {
  499. EmitSse2UcvtfOp(context, scalar: false);
  500. }
  501. else
  502. {
  503. EmitCvtf(context, signed: false, scalar: false);
  504. }
  505. }
  506. private static void EmitFcvt(ArmEmitterContext context, Func1I emit, bool signed, bool scalar)
  507. {
  508. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  509. Operand res = context.VectorZero();
  510. Operand n = GetVec(op.Rn);
  511. int sizeF = op.Size & 1;
  512. int sizeI = sizeF + 2;
  513. OperandType type = sizeF == 0 ? OperandType.FP32 : OperandType.FP64;
  514. int elems = !scalar ? op.GetBytesCount() >> sizeI : 1;
  515. for (int index = 0; index < elems; index++)
  516. {
  517. Operand ne = context.VectorExtract(type, n, index);
  518. Operand e = emit(ne);
  519. if (sizeF == 0)
  520. {
  521. MethodInfo info = signed
  522. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS32))
  523. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU32));
  524. e = context.Call(info, e);
  525. e = context.ZeroExtend32(OperandType.I64, e);
  526. }
  527. else /* if (sizeF == 1) */
  528. {
  529. MethodInfo info = signed
  530. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS64))
  531. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU64));
  532. e = context.Call(info, e);
  533. }
  534. res = EmitVectorInsert(context, res, e, index, sizeI);
  535. }
  536. context.Copy(GetVec(op.Rd), res);
  537. }
  538. private static void EmitFcvtz(ArmEmitterContext context, bool signed, bool scalar)
  539. {
  540. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  541. Operand res = context.VectorZero();
  542. Operand n = GetVec(op.Rn);
  543. int sizeF = op.Size & 1;
  544. int sizeI = sizeF + 2;
  545. OperandType type = sizeF == 0 ? OperandType.FP32 : OperandType.FP64;
  546. int fBits = GetFBits(context);
  547. int elems = !scalar ? op.GetBytesCount() >> sizeI : 1;
  548. for (int index = 0; index < elems; index++)
  549. {
  550. Operand ne = context.VectorExtract(type, n, index);
  551. Operand e = EmitF2iFBitsMul(context, ne, fBits);
  552. if (sizeF == 0)
  553. {
  554. MethodInfo info = signed
  555. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS32))
  556. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU32));
  557. e = context.Call(info, e);
  558. e = context.ZeroExtend32(OperandType.I64, e);
  559. }
  560. else /* if (sizeF == 1) */
  561. {
  562. MethodInfo info = signed
  563. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS64))
  564. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU64));
  565. e = context.Call(info, e);
  566. }
  567. res = EmitVectorInsert(context, res, e, index, sizeI);
  568. }
  569. context.Copy(GetVec(op.Rd), res);
  570. }
  571. private static void EmitFcvt_s_Gp(ArmEmitterContext context, Func1I emit)
  572. {
  573. EmitFcvt___Gp(context, emit, signed: true);
  574. }
  575. private static void EmitFcvt_u_Gp(ArmEmitterContext context, Func1I emit)
  576. {
  577. EmitFcvt___Gp(context, emit, signed: false);
  578. }
  579. private static void EmitFcvt___Gp(ArmEmitterContext context, Func1I emit, bool signed)
  580. {
  581. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  582. OperandType type = op.Size == 0 ? OperandType.FP32 : OperandType.FP64;
  583. Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
  584. Operand res = signed
  585. ? EmitScalarFcvts(context, emit(ne), 0)
  586. : EmitScalarFcvtu(context, emit(ne), 0);
  587. SetIntOrZR(context, op.Rd, res);
  588. }
  589. private static void EmitFcvtzs_Gp_Fixed(ArmEmitterContext context)
  590. {
  591. EmitFcvtz__Gp_Fixed(context, signed: true);
  592. }
  593. private static void EmitFcvtzu_Gp_Fixed(ArmEmitterContext context)
  594. {
  595. EmitFcvtz__Gp_Fixed(context, signed: false);
  596. }
  597. private static void EmitFcvtz__Gp_Fixed(ArmEmitterContext context, bool signed)
  598. {
  599. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  600. OperandType type = op.Size == 0 ? OperandType.FP32 : OperandType.FP64;
  601. Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
  602. Operand res = signed
  603. ? EmitScalarFcvts(context, ne, op.FBits)
  604. : EmitScalarFcvtu(context, ne, op.FBits);
  605. SetIntOrZR(context, op.Rd, res);
  606. }
  607. private static void EmitCvtf(ArmEmitterContext context, bool signed, bool scalar)
  608. {
  609. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  610. Operand res = context.VectorZero();
  611. int sizeF = op.Size & 1;
  612. int sizeI = sizeF + 2;
  613. int fBits = GetFBits(context);
  614. int elems = !scalar ? op.GetBytesCount() >> sizeI : 1;
  615. for (int index = 0; index < elems; index++)
  616. {
  617. Operand ne = EmitVectorLongExtract(context, op.Rn, index, sizeI);
  618. Operand e = EmitFPConvert(context, ne, sizeF, signed);
  619. e = EmitI2fFBitsMul(context, e, fBits);
  620. res = context.VectorInsert(res, e, index);
  621. }
  622. context.Copy(GetVec(op.Rd), res);
  623. }
  624. private static int GetFBits(ArmEmitterContext context)
  625. {
  626. if (context.CurrOp is OpCodeSimdShImm op)
  627. {
  628. return GetImmShr(op);
  629. }
  630. return 0;
  631. }
  632. private static Operand EmitFPConvert(ArmEmitterContext context, Operand value, int size, bool signed)
  633. {
  634. Debug.Assert(value.Type == OperandType.I32 || value.Type == OperandType.I64);
  635. Debug.Assert((uint)size < 2);
  636. OperandType type = size == 0 ? OperandType.FP32 : OperandType.FP64;
  637. if (signed)
  638. {
  639. return context.ConvertToFP(type, value);
  640. }
  641. else
  642. {
  643. return context.ConvertToFPUI(type, value);
  644. }
  645. }
  646. private static Operand EmitScalarFcvts(ArmEmitterContext context, Operand value, int fBits)
  647. {
  648. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  649. value = EmitF2iFBitsMul(context, value, fBits);
  650. MethodInfo info;
  651. if (context.CurrOp.RegisterSize == RegisterSize.Int32)
  652. {
  653. info = value.Type == OperandType.FP32
  654. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS32))
  655. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS32));
  656. }
  657. else
  658. {
  659. info = value.Type == OperandType.FP32
  660. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS64))
  661. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS64));
  662. }
  663. return context.Call(info, value);
  664. }
  665. private static Operand EmitScalarFcvtu(ArmEmitterContext context, Operand value, int fBits)
  666. {
  667. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  668. value = EmitF2iFBitsMul(context, value, fBits);
  669. MethodInfo info;
  670. if (context.CurrOp.RegisterSize == RegisterSize.Int32)
  671. {
  672. info = value.Type == OperandType.FP32
  673. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU32))
  674. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU32));
  675. }
  676. else
  677. {
  678. info = value.Type == OperandType.FP32
  679. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU64))
  680. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU64));
  681. }
  682. return context.Call(info, value);
  683. }
  684. private static Operand EmitF2iFBitsMul(ArmEmitterContext context, Operand value, int fBits)
  685. {
  686. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  687. if (fBits == 0)
  688. {
  689. return value;
  690. }
  691. if (value.Type == OperandType.FP32)
  692. {
  693. return context.Multiply(value, ConstF(MathF.Pow(2f, fBits)));
  694. }
  695. else /* if (value.Type == OperandType.FP64) */
  696. {
  697. return context.Multiply(value, ConstF(Math.Pow(2d, fBits)));
  698. }
  699. }
  700. private static Operand EmitI2fFBitsMul(ArmEmitterContext context, Operand value, int fBits)
  701. {
  702. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  703. if (fBits == 0)
  704. {
  705. return value;
  706. }
  707. if (value.Type == OperandType.FP32)
  708. {
  709. return context.Multiply(value, ConstF(1f / MathF.Pow(2f, fBits)));
  710. }
  711. else /* if (value.Type == OperandType.FP64) */
  712. {
  713. return context.Multiply(value, ConstF(1d / Math.Pow(2d, fBits)));
  714. }
  715. }
  716. public static Operand EmitSse2CvtDoubleToInt64OpF(ArmEmitterContext context, Operand opF, bool scalar)
  717. {
  718. Debug.Assert(opF.Type == OperandType.V128);
  719. Operand longL = context.AddIntrinsicLong (Intrinsic.X86Cvtsd2si, opF); // opFL
  720. Operand res = context.VectorCreateScalar(longL);
  721. if (!scalar)
  722. {
  723. Operand opFH = context.AddIntrinsic (Intrinsic.X86Movhlps, res, opF); // res doesn't matter.
  724. Operand longH = context.AddIntrinsicLong (Intrinsic.X86Cvtsd2si, opFH);
  725. Operand resH = context.VectorCreateScalar(longH);
  726. res = context.AddIntrinsic (Intrinsic.X86Movlhps, res, resH);
  727. }
  728. return res;
  729. }
  730. private static Operand EmitSse2CvtInt64ToDoubleOp(ArmEmitterContext context, Operand op, bool scalar)
  731. {
  732. Debug.Assert(op.Type == OperandType.V128);
  733. Operand longL = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, op); // opL
  734. Operand res = context.AddIntrinsic (Intrinsic.X86Cvtsi2sd, context.VectorZero(), longL);
  735. if (!scalar)
  736. {
  737. Operand opH = context.AddIntrinsic (Intrinsic.X86Movhlps, res, op); // res doesn't matter.
  738. Operand longH = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, opH);
  739. Operand resH = context.AddIntrinsic (Intrinsic.X86Cvtsi2sd, res, longH); // res doesn't matter.
  740. res = context.AddIntrinsic (Intrinsic.X86Movlhps, res, resH);
  741. }
  742. return res;
  743. }
  744. private static void EmitSse2ScvtfOp(ArmEmitterContext context, bool scalar)
  745. {
  746. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  747. Operand n = GetVec(op.Rn);
  748. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  749. int sizeF = op.Size & 1;
  750. if (sizeF == 0)
  751. {
  752. Operand res = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, n);
  753. if (op is OpCodeSimdShImm fixedOp)
  754. {
  755. int fBits = GetImmShr(fixedOp);
  756. // BitConverter.Int32BitsToSingle(fpScaled) == 1f / MathF.Pow(2f, fBits)
  757. int fpScaled = 0x3F800000 - fBits * 0x800000;
  758. Operand fpScaledMask = scalar
  759. ? X86GetScalar (context, fpScaled)
  760. : X86GetAllElements(context, fpScaled);
  761. res = context.AddIntrinsic(Intrinsic.X86Mulps, res, fpScaledMask);
  762. }
  763. if (scalar)
  764. {
  765. res = context.VectorZeroUpper96(res);
  766. }
  767. else if (op.RegisterSize == RegisterSize.Simd64)
  768. {
  769. res = context.VectorZeroUpper64(res);
  770. }
  771. context.Copy(GetVec(op.Rd), res);
  772. }
  773. else /* if (sizeF == 1) */
  774. {
  775. Operand res = EmitSse2CvtInt64ToDoubleOp(context, n, scalar);
  776. if (op is OpCodeSimdShImm fixedOp)
  777. {
  778. int fBits = GetImmShr(fixedOp);
  779. // BitConverter.Int64BitsToDouble(fpScaled) == 1d / Math.Pow(2d, fBits)
  780. long fpScaled = 0x3FF0000000000000L - fBits * 0x10000000000000L;
  781. Operand fpScaledMask = scalar
  782. ? X86GetScalar (context, fpScaled)
  783. : X86GetAllElements(context, fpScaled);
  784. res = context.AddIntrinsic(Intrinsic.X86Mulpd, res, fpScaledMask);
  785. }
  786. if (scalar)
  787. {
  788. res = context.VectorZeroUpper64(res);
  789. }
  790. context.Copy(GetVec(op.Rd), res);
  791. }
  792. }
  793. private static void EmitSse2UcvtfOp(ArmEmitterContext context, bool scalar)
  794. {
  795. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  796. Operand n = GetVec(op.Rn);
  797. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  798. int sizeF = op.Size & 1;
  799. if (sizeF == 0)
  800. {
  801. Operand mask = scalar // 65536.000f (1 << 16)
  802. ? X86GetScalar (context, 0x47800000)
  803. : X86GetAllElements(context, 0x47800000);
  804. Operand res = context.AddIntrinsic(Intrinsic.X86Psrld, n, Const(16));
  805. res = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res);
  806. res = context.AddIntrinsic(Intrinsic.X86Mulps, res, mask);
  807. Operand res2 = context.AddIntrinsic(Intrinsic.X86Pslld, n, Const(16));
  808. res2 = context.AddIntrinsic(Intrinsic.X86Psrld, res2, Const(16));
  809. res2 = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res2);
  810. res = context.AddIntrinsic(Intrinsic.X86Addps, res, res2);
  811. if (op is OpCodeSimdShImm fixedOp)
  812. {
  813. int fBits = GetImmShr(fixedOp);
  814. // BitConverter.Int32BitsToSingle(fpScaled) == 1f / MathF.Pow(2f, fBits)
  815. int fpScaled = 0x3F800000 - fBits * 0x800000;
  816. Operand fpScaledMask = scalar
  817. ? X86GetScalar (context, fpScaled)
  818. : X86GetAllElements(context, fpScaled);
  819. res = context.AddIntrinsic(Intrinsic.X86Mulps, res, fpScaledMask);
  820. }
  821. if (scalar)
  822. {
  823. res = context.VectorZeroUpper96(res);
  824. }
  825. else if (op.RegisterSize == RegisterSize.Simd64)
  826. {
  827. res = context.VectorZeroUpper64(res);
  828. }
  829. context.Copy(GetVec(op.Rd), res);
  830. }
  831. else /* if (sizeF == 1) */
  832. {
  833. Operand mask = scalar // 4294967296.0000000d (1L << 32)
  834. ? X86GetScalar (context, 0x41F0000000000000L)
  835. : X86GetAllElements(context, 0x41F0000000000000L);
  836. Operand res = context.AddIntrinsic (Intrinsic.X86Psrlq, n, Const(32));
  837. res = EmitSse2CvtInt64ToDoubleOp(context, res, scalar);
  838. res = context.AddIntrinsic (Intrinsic.X86Mulpd, res, mask);
  839. Operand res2 = context.AddIntrinsic (Intrinsic.X86Psllq, n, Const(32));
  840. res2 = context.AddIntrinsic (Intrinsic.X86Psrlq, res2, Const(32));
  841. res2 = EmitSse2CvtInt64ToDoubleOp(context, res2, scalar);
  842. res = context.AddIntrinsic(Intrinsic.X86Addpd, res, res2);
  843. if (op is OpCodeSimdShImm fixedOp)
  844. {
  845. int fBits = GetImmShr(fixedOp);
  846. // BitConverter.Int64BitsToDouble(fpScaled) == 1d / Math.Pow(2d, fBits)
  847. long fpScaled = 0x3FF0000000000000L - fBits * 0x10000000000000L;
  848. Operand fpScaledMask = scalar
  849. ? X86GetScalar (context, fpScaled)
  850. : X86GetAllElements(context, fpScaled);
  851. res = context.AddIntrinsic(Intrinsic.X86Mulpd, res, fpScaledMask);
  852. }
  853. if (scalar)
  854. {
  855. res = context.VectorZeroUpper64(res);
  856. }
  857. context.Copy(GetVec(op.Rd), res);
  858. }
  859. }
  860. private static void EmitSse41FcvtsOpF(ArmEmitterContext context, FPRoundingMode roundMode, bool scalar)
  861. {
  862. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  863. Operand n = GetVec(op.Rn);
  864. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  865. int sizeF = op.Size & 1;
  866. if (sizeF == 0)
  867. {
  868. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, n, n, Const((int)CmpCondition.OrderedQ));
  869. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  870. if (op is OpCodeSimdShImm fixedOp)
  871. {
  872. int fBits = GetImmShr(fixedOp);
  873. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, fBits)
  874. int fpScaled = 0x3F800000 + fBits * 0x800000;
  875. Operand fpScaledMask = scalar
  876. ? X86GetScalar (context, fpScaled)
  877. : X86GetAllElements(context, fpScaled);
  878. nRes = context.AddIntrinsic(Intrinsic.X86Mulps, nRes, fpScaledMask);
  879. }
  880. nRes = context.AddIntrinsic(Intrinsic.X86Roundps, nRes, Const(X86GetRoundControl(roundMode)));
  881. Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes);
  882. Operand fpMaxValMask = scalar // 2.14748365E9f (2147483648)
  883. ? X86GetScalar (context, 0x4F000000)
  884. : X86GetAllElements(context, 0x4F000000);
  885. nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  886. Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nInt, nRes);
  887. if (scalar)
  888. {
  889. dRes = context.VectorZeroUpper96(dRes);
  890. }
  891. else if (op.RegisterSize == RegisterSize.Simd64)
  892. {
  893. dRes = context.VectorZeroUpper64(dRes);
  894. }
  895. context.Copy(GetVec(op.Rd), dRes);
  896. }
  897. else /* if (sizeF == 1) */
  898. {
  899. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, n, n, Const((int)CmpCondition.OrderedQ));
  900. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  901. if (op is OpCodeSimdShImm fixedOp)
  902. {
  903. int fBits = GetImmShr(fixedOp);
  904. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, fBits)
  905. long fpScaled = 0x3FF0000000000000L + fBits * 0x10000000000000L;
  906. Operand fpScaledMask = scalar
  907. ? X86GetScalar (context, fpScaled)
  908. : X86GetAllElements(context, fpScaled);
  909. nRes = context.AddIntrinsic(Intrinsic.X86Mulpd, nRes, fpScaledMask);
  910. }
  911. nRes = context.AddIntrinsic(Intrinsic.X86Roundpd, nRes, Const(X86GetRoundControl(roundMode)));
  912. Operand nLong = EmitSse2CvtDoubleToInt64OpF(context, nRes, scalar);
  913. Operand fpMaxValMask = scalar // 9.2233720368547760E18d (9223372036854775808)
  914. ? X86GetScalar (context, 0x43E0000000000000L)
  915. : X86GetAllElements(context, 0x43E0000000000000L);
  916. nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  917. Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nLong, nRes);
  918. if (scalar)
  919. {
  920. dRes = context.VectorZeroUpper64(dRes);
  921. }
  922. context.Copy(GetVec(op.Rd), dRes);
  923. }
  924. }
  925. private static void EmitSse41FcvtuOpF(ArmEmitterContext context, FPRoundingMode roundMode, bool scalar)
  926. {
  927. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  928. Operand n = GetVec(op.Rn);
  929. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  930. int sizeF = op.Size & 1;
  931. if (sizeF == 0)
  932. {
  933. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, n, n, Const((int)CmpCondition.OrderedQ));
  934. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  935. if (op is OpCodeSimdShImm fixedOp)
  936. {
  937. int fBits = GetImmShr(fixedOp);
  938. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, fBits)
  939. int fpScaled = 0x3F800000 + fBits * 0x800000;
  940. Operand fpScaledMask = scalar
  941. ? X86GetScalar (context, fpScaled)
  942. : X86GetAllElements(context, fpScaled);
  943. nRes = context.AddIntrinsic(Intrinsic.X86Mulps, nRes, fpScaledMask);
  944. }
  945. nRes = context.AddIntrinsic(Intrinsic.X86Roundps, nRes, Const(X86GetRoundControl(roundMode)));
  946. Operand zero = context.VectorZero();
  947. Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  948. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  949. Operand fpMaxValMask = scalar // 2.14748365E9f (2147483648)
  950. ? X86GetScalar (context, 0x4F000000)
  951. : X86GetAllElements(context, 0x4F000000);
  952. Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes);
  953. nRes = context.AddIntrinsic(Intrinsic.X86Subps, nRes, fpMaxValMask);
  954. nCmp = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  955. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  956. Operand nInt2 = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes);
  957. nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  958. Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nInt2, nRes);
  959. dRes = context.AddIntrinsic(Intrinsic.X86Paddd, dRes, nInt);
  960. if (scalar)
  961. {
  962. dRes = context.VectorZeroUpper96(dRes);
  963. }
  964. else if (op.RegisterSize == RegisterSize.Simd64)
  965. {
  966. dRes = context.VectorZeroUpper64(dRes);
  967. }
  968. context.Copy(GetVec(op.Rd), dRes);
  969. }
  970. else /* if (sizeF == 1) */
  971. {
  972. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, n, n, Const((int)CmpCondition.OrderedQ));
  973. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  974. if (op is OpCodeSimdShImm fixedOp)
  975. {
  976. int fBits = GetImmShr(fixedOp);
  977. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, fBits)
  978. long fpScaled = 0x3FF0000000000000L + fBits * 0x10000000000000L;
  979. Operand fpScaledMask = scalar
  980. ? X86GetScalar (context, fpScaled)
  981. : X86GetAllElements(context, fpScaled);
  982. nRes = context.AddIntrinsic(Intrinsic.X86Mulpd, nRes, fpScaledMask);
  983. }
  984. nRes = context.AddIntrinsic(Intrinsic.X86Roundpd, nRes, Const(X86GetRoundControl(roundMode)));
  985. Operand zero = context.VectorZero();
  986. Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  987. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  988. Operand fpMaxValMask = scalar // 9.2233720368547760E18d (9223372036854775808)
  989. ? X86GetScalar (context, 0x43E0000000000000L)
  990. : X86GetAllElements(context, 0x43E0000000000000L);
  991. Operand nLong = EmitSse2CvtDoubleToInt64OpF(context, nRes, scalar);
  992. nRes = context.AddIntrinsic(Intrinsic.X86Subpd, nRes, fpMaxValMask);
  993. nCmp = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  994. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  995. Operand nLong2 = EmitSse2CvtDoubleToInt64OpF(context, nRes, scalar);
  996. nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  997. Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nLong2, nRes);
  998. dRes = context.AddIntrinsic(Intrinsic.X86Paddq, dRes, nLong);
  999. if (scalar)
  1000. {
  1001. dRes = context.VectorZeroUpper64(dRes);
  1002. }
  1003. context.Copy(GetVec(op.Rd), dRes);
  1004. }
  1005. }
  1006. private static void EmitSse41Fcvts_Gp(ArmEmitterContext context, FPRoundingMode roundMode, bool isFixed)
  1007. {
  1008. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  1009. Operand n = GetVec(op.Rn);
  1010. if (op.Size == 0)
  1011. {
  1012. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, n, n, Const((int)CmpCondition.OrderedQ));
  1013. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1014. if (isFixed)
  1015. {
  1016. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, op.FBits)
  1017. int fpScaled = 0x3F800000 + op.FBits * 0x800000;
  1018. Operand fpScaledMask = X86GetScalar(context, fpScaled);
  1019. nRes = context.AddIntrinsic(Intrinsic.X86Mulss, nRes, fpScaledMask);
  1020. }
  1021. nRes = context.AddIntrinsic(Intrinsic.X86Roundss, nRes, Const(X86GetRoundControl(roundMode)));
  1022. Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
  1023. ? context.AddIntrinsicInt (Intrinsic.X86Cvtss2si, nRes)
  1024. : context.AddIntrinsicLong(Intrinsic.X86Cvtss2si, nRes);
  1025. int fpMaxVal = op.RegisterSize == RegisterSize.Int32
  1026. ? 0x4F000000 // 2.14748365E9f (2147483648)
  1027. : 0x5F000000; // 9.223372E18f (9223372036854775808)
  1028. Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
  1029. nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1030. Operand nInt = context.AddIntrinsicInt(Intrinsic.X86Cvtsi2si, nRes);
  1031. if (op.RegisterSize == RegisterSize.Int64)
  1032. {
  1033. nInt = context.SignExtend32(OperandType.I64, nInt);
  1034. }
  1035. Operand dRes = context.BitwiseExclusiveOr(nIntOrLong, nInt);
  1036. SetIntOrZR(context, op.Rd, dRes);
  1037. }
  1038. else /* if (op.Size == 1) */
  1039. {
  1040. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, n, n, Const((int)CmpCondition.OrderedQ));
  1041. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1042. if (isFixed)
  1043. {
  1044. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, op.FBits)
  1045. long fpScaled = 0x3FF0000000000000L + op.FBits * 0x10000000000000L;
  1046. Operand fpScaledMask = X86GetScalar(context, fpScaled);
  1047. nRes = context.AddIntrinsic(Intrinsic.X86Mulsd, nRes, fpScaledMask);
  1048. }
  1049. nRes = context.AddIntrinsic(Intrinsic.X86Roundsd, nRes, Const(X86GetRoundControl(roundMode)));
  1050. Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
  1051. ? context.AddIntrinsicInt (Intrinsic.X86Cvtsd2si, nRes)
  1052. : context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRes);
  1053. long fpMaxVal = op.RegisterSize == RegisterSize.Int32
  1054. ? 0x41E0000000000000L // 2147483648.0000000d (2147483648)
  1055. : 0x43E0000000000000L; // 9.2233720368547760E18d (9223372036854775808)
  1056. Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
  1057. nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1058. Operand nLong = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, nRes);
  1059. if (op.RegisterSize == RegisterSize.Int32)
  1060. {
  1061. nLong = context.ConvertI64ToI32(nLong);
  1062. }
  1063. Operand dRes = context.BitwiseExclusiveOr(nIntOrLong, nLong);
  1064. SetIntOrZR(context, op.Rd, dRes);
  1065. }
  1066. }
  1067. private static void EmitSse41Fcvtu_Gp(ArmEmitterContext context, FPRoundingMode roundMode, bool isFixed)
  1068. {
  1069. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  1070. Operand n = GetVec(op.Rn);
  1071. if (op.Size == 0)
  1072. {
  1073. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, n, n, Const((int)CmpCondition.OrderedQ));
  1074. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1075. if (isFixed)
  1076. {
  1077. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, op.FBits)
  1078. int fpScaled = 0x3F800000 + op.FBits * 0x800000;
  1079. Operand fpScaledMask = X86GetScalar(context, fpScaled);
  1080. nRes = context.AddIntrinsic(Intrinsic.X86Mulss, nRes, fpScaledMask);
  1081. }
  1082. nRes = context.AddIntrinsic(Intrinsic.X86Roundss, nRes, Const(X86GetRoundControl(roundMode)));
  1083. Operand zero = context.VectorZero();
  1084. Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1085. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1086. int fpMaxVal = op.RegisterSize == RegisterSize.Int32
  1087. ? 0x4F000000 // 2.14748365E9f (2147483648)
  1088. : 0x5F000000; // 9.223372E18f (9223372036854775808)
  1089. Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
  1090. Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
  1091. ? context.AddIntrinsicInt (Intrinsic.X86Cvtss2si, nRes)
  1092. : context.AddIntrinsicLong(Intrinsic.X86Cvtss2si, nRes);
  1093. nRes = context.AddIntrinsic(Intrinsic.X86Subss, nRes, fpMaxValMask);
  1094. nCmp = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1095. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1096. Operand nIntOrLong2 = op.RegisterSize == RegisterSize.Int32
  1097. ? context.AddIntrinsicInt (Intrinsic.X86Cvtss2si, nRes)
  1098. : context.AddIntrinsicLong(Intrinsic.X86Cvtss2si, nRes);
  1099. nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1100. Operand nInt = context.AddIntrinsicInt(Intrinsic.X86Cvtsi2si, nRes);
  1101. if (op.RegisterSize == RegisterSize.Int64)
  1102. {
  1103. nInt = context.SignExtend32(OperandType.I64, nInt);
  1104. }
  1105. Operand dRes = context.BitwiseExclusiveOr(nIntOrLong2, nInt);
  1106. dRes = context.Add(dRes, nIntOrLong);
  1107. SetIntOrZR(context, op.Rd, dRes);
  1108. }
  1109. else /* if (op.Size == 1) */
  1110. {
  1111. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, n, n, Const((int)CmpCondition.OrderedQ));
  1112. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1113. if (isFixed)
  1114. {
  1115. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, op.FBits)
  1116. long fpScaled = 0x3FF0000000000000L + op.FBits * 0x10000000000000L;
  1117. Operand fpScaledMask = X86GetScalar(context, fpScaled);
  1118. nRes = context.AddIntrinsic(Intrinsic.X86Mulsd, nRes, fpScaledMask);
  1119. }
  1120. nRes = context.AddIntrinsic(Intrinsic.X86Roundsd, nRes, Const(X86GetRoundControl(roundMode)));
  1121. Operand zero = context.VectorZero();
  1122. Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1123. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1124. long fpMaxVal = op.RegisterSize == RegisterSize.Int32
  1125. ? 0x41E0000000000000L // 2147483648.0000000d (2147483648)
  1126. : 0x43E0000000000000L; // 9.2233720368547760E18d (9223372036854775808)
  1127. Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
  1128. Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
  1129. ? context.AddIntrinsicInt (Intrinsic.X86Cvtsd2si, nRes)
  1130. : context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRes);
  1131. nRes = context.AddIntrinsic(Intrinsic.X86Subsd, nRes, fpMaxValMask);
  1132. nCmp = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1133. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1134. Operand nIntOrLong2 = op.RegisterSize == RegisterSize.Int32
  1135. ? context.AddIntrinsicInt (Intrinsic.X86Cvtsd2si, nRes)
  1136. : context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRes);
  1137. nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1138. Operand nLong = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, nRes);
  1139. if (op.RegisterSize == RegisterSize.Int32)
  1140. {
  1141. nLong = context.ConvertI64ToI32(nLong);
  1142. }
  1143. Operand dRes = context.BitwiseExclusiveOr(nIntOrLong2, nLong);
  1144. dRes = context.Add(dRes, nIntOrLong);
  1145. SetIntOrZR(context, op.Rd, dRes);
  1146. }
  1147. }
  1148. private static Operand EmitVectorLongExtract(ArmEmitterContext context, int reg, int index, int size)
  1149. {
  1150. OperandType type = size == 3 ? OperandType.I64 : OperandType.I32;
  1151. return context.VectorExtract(type, GetVec(reg), index);
  1152. }
  1153. }
  1154. }