| .. |
|
CpuContext.cs
|
0c87bf9ea4
Refactor CPU interface to allow the implementation of other CPU emulators (#3362)
|
3 år sedan |
|
CpuTest.cs
|
905a191e28
Use upstream unicorn for Ryujinx.Tests.Unicorn (#3771)
|
3 år sedan |
|
CpuTest32.cs
|
905a191e28
Use upstream unicorn for Ryujinx.Tests.Unicorn (#3771)
|
3 år sedan |
|
CpuTestAlu.cs
|
d87c5375f1
Implement a custom value generator for the Tests of the CLS and CLZ instructions (Base: 32, 64 bits. Simd: 8, 16, 32 bits). (#696)
|
6 år sedan |
|
CpuTestAlu32.cs
|
8e119a1e96
Implement PLD and SUB (imm16) on T32, plus UADD8, SADD8, USUB8 and SSUB8 on both A32 and T32 (#3693)
|
3 år sedan |
|
CpuTestAluBinary.cs
|
d7044b10a2
Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328)
|
5 år sedan |
|
CpuTestAluBinary32.cs
|
951700fdd8
Removed unused usings. (#3593)
|
3 år sedan |
|
CpuTestAluImm.cs
|
1e7ea76f14
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
|
7 år sedan |
|
CpuTestAluImm32.cs
|
951700fdd8
Removed unused usings. (#3593)
|
3 år sedan |
|
CpuTestAluRs.cs
|
a731ab3a2a
Add a new JIT compiler for CPU code (#693)
|
6 år sedan |
|
CpuTestAluRs32.cs
|
b1b6f294f2
Add most of the A32 instruction set to ARMeilleure (#897)
|
6 år sedan |
|
CpuTestAluRx.cs
|
1e7ea76f14
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
|
7 år sedan |
|
CpuTestBf32.cs
|
b1b6f294f2
Add most of the A32 instruction set to ARMeilleure (#897)
|
6 år sedan |
|
CpuTestBfm.cs
|
1e7ea76f14
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
|
7 år sedan |
|
CpuTestCcmpImm.cs
|
1e7ea76f14
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
|
7 år sedan |
|
CpuTestCcmpReg.cs
|
1e7ea76f14
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
|
7 år sedan |
|
CpuTestCsel.cs
|
1e7ea76f14
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
|
7 år sedan |
|
CpuTestMisc.cs
|
a804db6eed
Add Fmax/minv_V & S/Ushl_S Inst.s with Tests. Fix Maxps/d & Minps/d d… (#1335)
|
5 år sedan |
|
CpuTestMisc32.cs
|
e36e97c64d
CPU: This PR fixes Fpscr, among other things. (#1433)
|
5 år sedan |
|
CpuTestMov.cs
|
d87c5375f1
Implement a custom value generator for the Tests of the CLS and CLZ instructions (Base: 32, 64 bits. Simd: 8, 16, 32 bits). (#696)
|
6 år sedan |
|
CpuTestMul.cs
|
1e7ea76f14
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
|
7 år sedan |
|
CpuTestMul32.cs
|
951700fdd8
Removed unused usings. (#3593)
|
3 år sedan |
|
CpuTestSimd.cs
|
f7ef6364b7
Implement CPU FCVT Half <-> Double conversion variants (#3439)
|
3 år sedan |
|
CpuTestSimd32.cs
|
db45688aa8
Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677)
|
3 år sedan |
|
CpuTestSimdCrypto.cs
|
a731ab3a2a
Add a new JIT compiler for CPU code (#693)
|
6 år sedan |
|
CpuTestSimdCrypto32.cs
|
dd433c1296
Implement AESMC, AESIMC, AESE, AESD and VEOR AArch32 instructions (#982)
|
6 år sedan |
|
CpuTestSimdCvt.cs
|
60f7cba30a
Implement FCVTNS (Scalar GP) (#2953)
|
4 år sedan |
|
CpuTestSimdCvt32.cs
|
8d41402fa6
A32: Implement VCVTT, VCVTB (#3710)
|
3 år sedan |
|
CpuTestSimdExt.cs
|
a731ab3a2a
Add a new JIT compiler for CPU code (#693)
|
6 år sedan |
|
CpuTestSimdFcond.cs
|
a731ab3a2a
Add a new JIT compiler for CPU code (#693)
|
6 år sedan |
|
CpuTestSimdFmov.cs
|
a731ab3a2a
Add a new JIT compiler for CPU code (#693)
|
6 år sedan |
|
CpuTestSimdImm.cs
|
a731ab3a2a
Add a new JIT compiler for CPU code (#693)
|
6 år sedan |
|
CpuTestSimdIns.cs
|
a731ab3a2a
Add a new JIT compiler for CPU code (#693)
|
6 år sedan |
|
CpuTestSimdLogical32.cs
|
951700fdd8
Removed unused usings. (#3593)
|
3 år sedan |
|
CpuTestSimdMemory32.cs
|
729ff5337c
Fix increment on Arm32 NEON VLDn/VSTn instructions with regs > 1 (#3695)
|
3 år sedan |
|
CpuTestSimdMov32.cs
|
951700fdd8
Removed unused usings. (#3593)
|
3 år sedan |
|
CpuTestSimdReg.cs
|
430ba6da65
CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)
|
5 år sedan |
|
CpuTestSimdReg32.cs
|
db45688aa8
Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677)
|
3 år sedan |
|
CpuTestSimdRegElem.cs
|
4bd1ad16f9
Add Sqdmulh_Ve & Sqrdmulh_Ve Inst.s with Tests. (#2139)
|
5 år sedan |
|
CpuTestSimdRegElem32.cs
|
951700fdd8
Removed unused usings. (#3593)
|
3 år sedan |
|
CpuTestSimdRegElemF.cs
|
a731ab3a2a
Add a new JIT compiler for CPU code (#693)
|
6 år sedan |
|
CpuTestSimdShImm.cs
|
2cb8bd7006
CPU (A64): Add Scvtf_S_Fixed & Ucvtf_S_Fixed with Tests. (#1492)
|
5 år sedan |
|
CpuTestSimdShImm32.cs
|
db45688aa8
Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677)
|
3 år sedan |
|
CpuTestSimdTbl.cs
|
16869402bf
Add Tbx Inst. (fast & slow paths), with Tests. (#782)
|
6 år sedan |
|
CpuTestSystem.cs
|
7c111a3567
Add Mrs & Msr (Nzcv) Inst., with Tests. (#819)
|
6 år sedan |
|
CpuTestT32Alu.cs
|
951700fdd8
Removed unused usings. (#3593)
|
3 år sedan |
|
CpuTestT32Flow.cs
|
bd9ac0fdaa
T32: Implement B, B.cond, BL, BLX (#3155)
|
4 år sedan |
|
CpuTestT32Mem.cs
|
951700fdd8
Removed unused usings. (#3593)
|
3 år sedan |
|
CpuTestThumb.cs
|
951700fdd8
Removed unused usings. (#3593)
|
3 år sedan |
|
PrecomputedMemoryThumbTestCase.cs
|
951700fdd8
Removed unused usings. (#3593)
|
3 år sedan |
|
PrecomputedThumbTestCase.cs
|
7b35ebc64a
T32: Implement ALU (shifted register) instructions (#3135)
|
4 år sedan |
TSRBerry