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ryujinx
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Ryujinx.Tests
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Cpu
gdkchan 8e119a1e96 Implement PLD and SUB (imm16) on T32, plus UADD8, SADD8, USUB8 and SSUB8 on both A32 and T32 (#3693) %!s(int64=3) %!d(string=hai) anos
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CpuContext.cs 0c87bf9ea4 Refactor CPU interface to allow the implementation of other CPU emulators (#3362) %!s(int64=3) %!d(string=hai) anos
CpuTest.cs 0c87bf9ea4 Refactor CPU interface to allow the implementation of other CPU emulators (#3362) %!s(int64=3) %!d(string=hai) anos
CpuTest32.cs 8e119a1e96 Implement PLD and SUB (imm16) on T32, plus UADD8, SADD8, USUB8 and SSUB8 on both A32 and T32 (#3693) %!s(int64=3) %!d(string=hai) anos
CpuTestAlu.cs d87c5375f1 Implement a custom value generator for the Tests of the CLS and CLZ instructions (Base: 32, 64 bits. Simd: 8, 16, 32 bits). (#696) %!s(int64=6) %!d(string=hai) anos
CpuTestAlu32.cs 8e119a1e96 Implement PLD and SUB (imm16) on T32, plus UADD8, SADD8, USUB8 and SSUB8 on both A32 and T32 (#3693) %!s(int64=3) %!d(string=hai) anos
CpuTestAluBinary.cs d7044b10a2 Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328) %!s(int64=5) %!d(string=hai) anos
CpuTestAluBinary32.cs 951700fdd8 Removed unused usings. (#3593) %!s(int64=3) %!d(string=hai) anos
CpuTestAluImm.cs 1e7ea76f14 Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489) %!s(int64=7) %!d(string=hai) anos
CpuTestAluImm32.cs 951700fdd8 Removed unused usings. (#3593) %!s(int64=3) %!d(string=hai) anos
CpuTestAluRs.cs a731ab3a2a Add a new JIT compiler for CPU code (#693) %!s(int64=6) %!d(string=hai) anos
CpuTestAluRs32.cs b1b6f294f2 Add most of the A32 instruction set to ARMeilleure (#897) %!s(int64=6) %!d(string=hai) anos
CpuTestAluRx.cs 1e7ea76f14 Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489) %!s(int64=7) %!d(string=hai) anos
CpuTestBf32.cs b1b6f294f2 Add most of the A32 instruction set to ARMeilleure (#897) %!s(int64=6) %!d(string=hai) anos
CpuTestBfm.cs 1e7ea76f14 Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489) %!s(int64=7) %!d(string=hai) anos
CpuTestCcmpImm.cs 1e7ea76f14 Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489) %!s(int64=7) %!d(string=hai) anos
CpuTestCcmpReg.cs 1e7ea76f14 Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489) %!s(int64=7) %!d(string=hai) anos
CpuTestCsel.cs 1e7ea76f14 Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489) %!s(int64=7) %!d(string=hai) anos
CpuTestMisc.cs a804db6eed Add Fmax/minv_V & S/Ushl_S Inst.s with Tests. Fix Maxps/d & Minps/d d… (#1335) %!s(int64=5) %!d(string=hai) anos
CpuTestMisc32.cs e36e97c64d CPU: This PR fixes Fpscr, among other things. (#1433) %!s(int64=5) %!d(string=hai) anos
CpuTestMov.cs d87c5375f1 Implement a custom value generator for the Tests of the CLS and CLZ instructions (Base: 32, 64 bits. Simd: 8, 16, 32 bits). (#696) %!s(int64=6) %!d(string=hai) anos
CpuTestMul.cs 1e7ea76f14 Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489) %!s(int64=7) %!d(string=hai) anos
CpuTestMul32.cs 951700fdd8 Removed unused usings. (#3593) %!s(int64=3) %!d(string=hai) anos
CpuTestSimd.cs f7ef6364b7 Implement CPU FCVT Half <-> Double conversion variants (#3439) %!s(int64=3) %!d(string=hai) anos
CpuTestSimd32.cs db45688aa8 Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677) %!s(int64=3) %!d(string=hai) anos
CpuTestSimdCrypto.cs a731ab3a2a Add a new JIT compiler for CPU code (#693) %!s(int64=6) %!d(string=hai) anos
CpuTestSimdCrypto32.cs dd433c1296 Implement AESMC, AESIMC, AESE, AESD and VEOR AArch32 instructions (#982) %!s(int64=6) %!d(string=hai) anos
CpuTestSimdCvt.cs 60f7cba30a Implement FCVTNS (Scalar GP) (#2953) %!s(int64=4) %!d(string=hai) anos
CpuTestSimdCvt32.cs 4d69286a9c Implement VRINT (vector) Arm32 NEON instructions (#3691) %!s(int64=3) %!d(string=hai) anos
CpuTestSimdExt.cs a731ab3a2a Add a new JIT compiler for CPU code (#693) %!s(int64=6) %!d(string=hai) anos
CpuTestSimdFcond.cs a731ab3a2a Add a new JIT compiler for CPU code (#693) %!s(int64=6) %!d(string=hai) anos
CpuTestSimdFmov.cs a731ab3a2a Add a new JIT compiler for CPU code (#693) %!s(int64=6) %!d(string=hai) anos
CpuTestSimdImm.cs a731ab3a2a Add a new JIT compiler for CPU code (#693) %!s(int64=6) %!d(string=hai) anos
CpuTestSimdIns.cs a731ab3a2a Add a new JIT compiler for CPU code (#693) %!s(int64=6) %!d(string=hai) anos
CpuTestSimdLogical32.cs 951700fdd8 Removed unused usings. (#3593) %!s(int64=3) %!d(string=hai) anos
CpuTestSimdMemory32.cs 729ff5337c Fix increment on Arm32 NEON VLDn/VSTn instructions with regs > 1 (#3695) %!s(int64=3) %!d(string=hai) anos
CpuTestSimdMov32.cs 951700fdd8 Removed unused usings. (#3593) %!s(int64=3) %!d(string=hai) anos
CpuTestSimdReg.cs 430ba6da65 CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817) %!s(int64=5) %!d(string=hai) anos
CpuTestSimdReg32.cs db45688aa8 Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677) %!s(int64=3) %!d(string=hai) anos
CpuTestSimdRegElem.cs 4bd1ad16f9 Add Sqdmulh_Ve & Sqrdmulh_Ve Inst.s with Tests. (#2139) %!s(int64=5) %!d(string=hai) anos
CpuTestSimdRegElem32.cs 951700fdd8 Removed unused usings. (#3593) %!s(int64=3) %!d(string=hai) anos
CpuTestSimdRegElemF.cs a731ab3a2a Add a new JIT compiler for CPU code (#693) %!s(int64=6) %!d(string=hai) anos
CpuTestSimdShImm.cs 2cb8bd7006 CPU (A64): Add Scvtf_S_Fixed & Ucvtf_S_Fixed with Tests. (#1492) %!s(int64=5) %!d(string=hai) anos
CpuTestSimdShImm32.cs db45688aa8 Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677) %!s(int64=3) %!d(string=hai) anos
CpuTestSimdTbl.cs 16869402bf Add Tbx Inst. (fast & slow paths), with Tests. (#782) %!s(int64=6) %!d(string=hai) anos
CpuTestSystem.cs 7c111a3567 Add Mrs & Msr (Nzcv) Inst., with Tests. (#819) %!s(int64=6) %!d(string=hai) anos
CpuTestT32Alu.cs 951700fdd8 Removed unused usings. (#3593) %!s(int64=3) %!d(string=hai) anos
CpuTestT32Flow.cs bd9ac0fdaa T32: Implement B, B.cond, BL, BLX (#3155) %!s(int64=4) %!d(string=hai) anos
CpuTestT32Mem.cs 951700fdd8 Removed unused usings. (#3593) %!s(int64=3) %!d(string=hai) anos
CpuTestThumb.cs 951700fdd8 Removed unused usings. (#3593) %!s(int64=3) %!d(string=hai) anos
PrecomputedMemoryThumbTestCase.cs 951700fdd8 Removed unused usings. (#3593) %!s(int64=3) %!d(string=hai) anos
PrecomputedThumbTestCase.cs 7b35ebc64a T32: Implement ALU (shifted register) instructions (#3135) %!s(int64=4) %!d(string=hai) anos