| .. |
|
Aarch32Mode.cs
|
a731ab3a2a
Add a new JIT compiler for CPU code (#693)
|
6 years ago |
|
ExecutionContext.cs
|
cf6cd71488
IPC refactor part 2: Use ReplyAndReceive on HLE services and remove special handling from kernel (#1458)
|
5 years ago |
|
ExecutionMode.cs
|
b5c215111d
PPTC Follow-up. (#1712)
|
5 years ago |
|
FPCR.cs
|
e36e97c64d
CPU: This PR fixes Fpscr, among other things. (#1433)
|
5 years ago |
|
FPException.cs
|
a731ab3a2a
Add a new JIT compiler for CPU code (#693)
|
6 years ago |
|
FPRoundingMode.cs
|
a731ab3a2a
Add a new JIT compiler for CPU code (#693)
|
6 years ago |
|
FPSR.cs
|
e36e97c64d
CPU: This PR fixes Fpscr, among other things. (#1433)
|
5 years ago |
|
FPState.cs
|
e36e97c64d
CPU: This PR fixes Fpscr, among other things. (#1433)
|
5 years ago |
|
FPType.cs
|
a731ab3a2a
Add a new JIT compiler for CPU code (#693)
|
6 years ago |
|
InstExceptionEventArgs.cs
|
a731ab3a2a
Add a new JIT compiler for CPU code (#693)
|
6 years ago |
|
InstUndefinedEventArgs.cs
|
a731ab3a2a
Add a new JIT compiler for CPU code (#693)
|
6 years ago |
|
NativeContext.cs
|
9878fc2d3c
Implement inline memory load/store exclusive and ordered (#1413)
|
5 years ago |
|
PState.cs
|
e36e97c64d
CPU: This PR fixes Fpscr, among other things. (#1433)
|
5 years ago |
|
RegisterAlias.cs
|
b1b6f294f2
Add most of the A32 instruction set to ARMeilleure (#897)
|
6 years ago |
|
RegisterConsts.cs
|
b1b6f294f2
Add most of the A32 instruction set to ARMeilleure (#897)
|
6 years ago |
|
V128.cs
|
430ba6da65
CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)
|
5 years ago |
LDj3SNuD
430ba6da65
CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)