InstEmitSimdHelper.cs 59 KB

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  1. using ARMeilleure.Decoders;
  2. using ARMeilleure.IntermediateRepresentation;
  3. using ARMeilleure.State;
  4. using ARMeilleure.Translation;
  5. using System;
  6. using System.Diagnostics;
  7. using System.Reflection;
  8. using static ARMeilleure.Instructions.InstEmitHelper;
  9. using static ARMeilleure.IntermediateRepresentation.OperandHelper;
  10. namespace ARMeilleure.Instructions
  11. {
  12. using Func1I = Func<Operand, Operand>;
  13. using Func2I = Func<Operand, Operand, Operand>;
  14. using Func3I = Func<Operand, Operand, Operand, Operand>;
  15. static class InstEmitSimdHelper
  16. {
  17. #region "Masks"
  18. public static readonly long[] EvenMasks = new long[]
  19. {
  20. 14L << 56 | 12L << 48 | 10L << 40 | 08L << 32 | 06L << 24 | 04L << 16 | 02L << 8 | 00L << 0, // B
  21. 13L << 56 | 12L << 48 | 09L << 40 | 08L << 32 | 05L << 24 | 04L << 16 | 01L << 8 | 00L << 0, // H
  22. 11L << 56 | 10L << 48 | 09L << 40 | 08L << 32 | 03L << 24 | 02L << 16 | 01L << 8 | 00L << 0 // S
  23. };
  24. public static readonly long[] OddMasks = new long[]
  25. {
  26. 15L << 56 | 13L << 48 | 11L << 40 | 09L << 32 | 07L << 24 | 05L << 16 | 03L << 8 | 01L << 0, // B
  27. 15L << 56 | 14L << 48 | 11L << 40 | 10L << 32 | 07L << 24 | 06L << 16 | 03L << 8 | 02L << 0, // H
  28. 15L << 56 | 14L << 48 | 13L << 40 | 12L << 32 | 07L << 24 | 06L << 16 | 05L << 8 | 04L << 0 // S
  29. };
  30. public static readonly long ZeroMask = 128L << 56 | 128L << 48 | 128L << 40 | 128L << 32 | 128L << 24 | 128L << 16 | 128L << 8 | 128L << 0;
  31. #endregion
  32. #region "X86 SSE Intrinsics"
  33. public static readonly Intrinsic[] X86PaddInstruction = new Intrinsic[]
  34. {
  35. Intrinsic.X86Paddb,
  36. Intrinsic.X86Paddw,
  37. Intrinsic.X86Paddd,
  38. Intrinsic.X86Paddq
  39. };
  40. public static readonly Intrinsic[] X86PcmpeqInstruction = new Intrinsic[]
  41. {
  42. Intrinsic.X86Pcmpeqb,
  43. Intrinsic.X86Pcmpeqw,
  44. Intrinsic.X86Pcmpeqd,
  45. Intrinsic.X86Pcmpeqq
  46. };
  47. public static readonly Intrinsic[] X86PcmpgtInstruction = new Intrinsic[]
  48. {
  49. Intrinsic.X86Pcmpgtb,
  50. Intrinsic.X86Pcmpgtw,
  51. Intrinsic.X86Pcmpgtd,
  52. Intrinsic.X86Pcmpgtq
  53. };
  54. public static readonly Intrinsic[] X86PmaxsInstruction = new Intrinsic[]
  55. {
  56. Intrinsic.X86Pmaxsb,
  57. Intrinsic.X86Pmaxsw,
  58. Intrinsic.X86Pmaxsd
  59. };
  60. public static readonly Intrinsic[] X86PmaxuInstruction = new Intrinsic[]
  61. {
  62. Intrinsic.X86Pmaxub,
  63. Intrinsic.X86Pmaxuw,
  64. Intrinsic.X86Pmaxud
  65. };
  66. public static readonly Intrinsic[] X86PminsInstruction = new Intrinsic[]
  67. {
  68. Intrinsic.X86Pminsb,
  69. Intrinsic.X86Pminsw,
  70. Intrinsic.X86Pminsd
  71. };
  72. public static readonly Intrinsic[] X86PminuInstruction = new Intrinsic[]
  73. {
  74. Intrinsic.X86Pminub,
  75. Intrinsic.X86Pminuw,
  76. Intrinsic.X86Pminud
  77. };
  78. public static readonly Intrinsic[] X86PmovsxInstruction = new Intrinsic[]
  79. {
  80. Intrinsic.X86Pmovsxbw,
  81. Intrinsic.X86Pmovsxwd,
  82. Intrinsic.X86Pmovsxdq
  83. };
  84. public static readonly Intrinsic[] X86PmovzxInstruction = new Intrinsic[]
  85. {
  86. Intrinsic.X86Pmovzxbw,
  87. Intrinsic.X86Pmovzxwd,
  88. Intrinsic.X86Pmovzxdq
  89. };
  90. public static readonly Intrinsic[] X86PsllInstruction = new Intrinsic[]
  91. {
  92. 0,
  93. Intrinsic.X86Psllw,
  94. Intrinsic.X86Pslld,
  95. Intrinsic.X86Psllq
  96. };
  97. public static readonly Intrinsic[] X86PsraInstruction = new Intrinsic[]
  98. {
  99. 0,
  100. Intrinsic.X86Psraw,
  101. Intrinsic.X86Psrad
  102. };
  103. public static readonly Intrinsic[] X86PsrlInstruction = new Intrinsic[]
  104. {
  105. 0,
  106. Intrinsic.X86Psrlw,
  107. Intrinsic.X86Psrld,
  108. Intrinsic.X86Psrlq
  109. };
  110. public static readonly Intrinsic[] X86PsubInstruction = new Intrinsic[]
  111. {
  112. Intrinsic.X86Psubb,
  113. Intrinsic.X86Psubw,
  114. Intrinsic.X86Psubd,
  115. Intrinsic.X86Psubq
  116. };
  117. public static readonly Intrinsic[] X86PunpckhInstruction = new Intrinsic[]
  118. {
  119. Intrinsic.X86Punpckhbw,
  120. Intrinsic.X86Punpckhwd,
  121. Intrinsic.X86Punpckhdq,
  122. Intrinsic.X86Punpckhqdq
  123. };
  124. public static readonly Intrinsic[] X86PunpcklInstruction = new Intrinsic[]
  125. {
  126. Intrinsic.X86Punpcklbw,
  127. Intrinsic.X86Punpcklwd,
  128. Intrinsic.X86Punpckldq,
  129. Intrinsic.X86Punpcklqdq
  130. };
  131. #endregion
  132. public static int GetImmShl(OpCodeSimdShImm op)
  133. {
  134. return op.Imm - (8 << op.Size);
  135. }
  136. public static int GetImmShr(OpCodeSimdShImm op)
  137. {
  138. return (8 << (op.Size + 1)) - op.Imm;
  139. }
  140. public static Operand X86GetScalar(ArmEmitterContext context, float value)
  141. {
  142. return X86GetScalar(context, BitConverter.SingleToInt32Bits(value));
  143. }
  144. public static Operand X86GetScalar(ArmEmitterContext context, double value)
  145. {
  146. return X86GetScalar(context, BitConverter.DoubleToInt64Bits(value));
  147. }
  148. public static Operand X86GetScalar(ArmEmitterContext context, int value)
  149. {
  150. return context.VectorCreateScalar(Const(value));
  151. }
  152. public static Operand X86GetScalar(ArmEmitterContext context, long value)
  153. {
  154. return context.VectorCreateScalar(Const(value));
  155. }
  156. public static Operand X86GetAllElements(ArmEmitterContext context, float value)
  157. {
  158. return X86GetAllElements(context, BitConverter.SingleToInt32Bits(value));
  159. }
  160. public static Operand X86GetAllElements(ArmEmitterContext context, double value)
  161. {
  162. return X86GetAllElements(context, BitConverter.DoubleToInt64Bits(value));
  163. }
  164. public static Operand X86GetAllElements(ArmEmitterContext context, int value)
  165. {
  166. Operand vector = context.VectorCreateScalar(Const(value));
  167. vector = context.AddIntrinsic(Intrinsic.X86Shufps, vector, vector, Const(0));
  168. return vector;
  169. }
  170. public static Operand X86GetAllElements(ArmEmitterContext context, long value)
  171. {
  172. Operand vector = context.VectorCreateScalar(Const(value));
  173. vector = context.AddIntrinsic(Intrinsic.X86Movlhps, vector, vector);
  174. return vector;
  175. }
  176. public static Operand X86GetElements(ArmEmitterContext context, long e1, long e0)
  177. {
  178. return X86GetElements(context, (ulong)e1, (ulong)e0);
  179. }
  180. public static Operand X86GetElements(ArmEmitterContext context, ulong e1, ulong e0)
  181. {
  182. Operand vector0 = context.VectorCreateScalar(Const(e0));
  183. Operand vector1 = context.VectorCreateScalar(Const(e1));
  184. return context.AddIntrinsic(Intrinsic.X86Punpcklqdq, vector0, vector1);
  185. }
  186. public static int X86GetRoundControl(FPRoundingMode roundMode)
  187. {
  188. switch (roundMode)
  189. {
  190. case FPRoundingMode.ToNearest: return 8 | 0; // even
  191. case FPRoundingMode.TowardsPlusInfinity: return 8 | 2;
  192. case FPRoundingMode.TowardsMinusInfinity: return 8 | 1;
  193. case FPRoundingMode.TowardsZero: return 8 | 3;
  194. }
  195. throw new ArgumentException($"Invalid rounding mode \"{roundMode}\".");
  196. }
  197. public static void EmitScalarUnaryOpF(ArmEmitterContext context, Intrinsic inst32, Intrinsic inst64)
  198. {
  199. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  200. Operand n = GetVec(op.Rn);
  201. Intrinsic inst = (op.Size & 1) != 0 ? inst64 : inst32;
  202. Operand res = context.AddIntrinsic(inst, n);
  203. if ((op.Size & 1) != 0)
  204. {
  205. res = context.VectorZeroUpper64(res);
  206. }
  207. else
  208. {
  209. res = context.VectorZeroUpper96(res);
  210. }
  211. context.Copy(GetVec(op.Rd), res);
  212. }
  213. public static void EmitScalarBinaryOpF(ArmEmitterContext context, Intrinsic inst32, Intrinsic inst64)
  214. {
  215. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  216. Operand n = GetVec(op.Rn);
  217. Operand m = GetVec(op.Rm);
  218. Intrinsic inst = (op.Size & 1) != 0 ? inst64 : inst32;
  219. Operand res = context.AddIntrinsic(inst, n, m);
  220. if ((op.Size & 1) != 0)
  221. {
  222. res = context.VectorZeroUpper64(res);
  223. }
  224. else
  225. {
  226. res = context.VectorZeroUpper96(res);
  227. }
  228. context.Copy(GetVec(op.Rd), res);
  229. }
  230. public static void EmitVectorUnaryOpF(ArmEmitterContext context, Intrinsic inst32, Intrinsic inst64)
  231. {
  232. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  233. Operand n = GetVec(op.Rn);
  234. Intrinsic inst = (op.Size & 1) != 0 ? inst64 : inst32;
  235. Operand res = context.AddIntrinsic(inst, n);
  236. if (op.RegisterSize == RegisterSize.Simd64)
  237. {
  238. res = context.VectorZeroUpper64(res);
  239. }
  240. context.Copy(GetVec(op.Rd), res);
  241. }
  242. public static void EmitVectorBinaryOpF(ArmEmitterContext context, Intrinsic inst32, Intrinsic inst64)
  243. {
  244. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  245. Operand n = GetVec(op.Rn);
  246. Operand m = GetVec(op.Rm);
  247. Intrinsic inst = (op.Size & 1) != 0 ? inst64 : inst32;
  248. Operand res = context.AddIntrinsic(inst, n, m);
  249. if (op.RegisterSize == RegisterSize.Simd64)
  250. {
  251. res = context.VectorZeroUpper64(res);
  252. }
  253. context.Copy(GetVec(op.Rd), res);
  254. }
  255. public static Operand EmitUnaryMathCall(ArmEmitterContext context, string name, Operand n)
  256. {
  257. IOpCodeSimd op = (IOpCodeSimd)context.CurrOp;
  258. MethodInfo info = (op.Size & 1) == 0
  259. ? typeof(MathF).GetMethod(name, new Type[] { typeof(float) })
  260. : typeof(Math). GetMethod(name, new Type[] { typeof(double) });
  261. return context.Call(info, n);
  262. }
  263. public static Operand EmitRoundMathCall(ArmEmitterContext context, MidpointRounding roundMode, Operand n)
  264. {
  265. IOpCodeSimd op = (IOpCodeSimd)context.CurrOp;
  266. string name = nameof(Math.Round);
  267. MethodInfo info = (op.Size & 1) == 0
  268. ? typeof(MathF).GetMethod(name, new Type[] { typeof(float), typeof(MidpointRounding) })
  269. : typeof(Math). GetMethod(name, new Type[] { typeof(double), typeof(MidpointRounding) });
  270. return context.Call(info, n, Const((int)roundMode));
  271. }
  272. public static Operand EmitSoftFloatCall(ArmEmitterContext context, string name, params Operand[] callArgs)
  273. {
  274. IOpCodeSimd op = (IOpCodeSimd)context.CurrOp;
  275. MethodInfo info = (op.Size & 1) == 0
  276. ? typeof(SoftFloat32).GetMethod(name)
  277. : typeof(SoftFloat64).GetMethod(name);
  278. return context.Call(info, callArgs);
  279. }
  280. public static void EmitScalarBinaryOpByElemF(ArmEmitterContext context, Func2I emit)
  281. {
  282. OpCodeSimdRegElemF op = (OpCodeSimdRegElemF)context.CurrOp;
  283. OperandType type = (op.Size & 1) != 0 ? OperandType.FP64 : OperandType.FP32;
  284. Operand n = context.VectorExtract(type, GetVec(op.Rn), 0);
  285. Operand m = context.VectorExtract(type, GetVec(op.Rm), op.Index);
  286. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), emit(n, m), 0));
  287. }
  288. public static void EmitScalarTernaryOpByElemF(ArmEmitterContext context, Func3I emit)
  289. {
  290. OpCodeSimdRegElemF op = (OpCodeSimdRegElemF)context.CurrOp;
  291. OperandType type = (op.Size & 1) != 0 ? OperandType.FP64 : OperandType.FP32;
  292. Operand d = context.VectorExtract(type, GetVec(op.Rd), 0);
  293. Operand n = context.VectorExtract(type, GetVec(op.Rn), 0);
  294. Operand m = context.VectorExtract(type, GetVec(op.Rm), op.Index);
  295. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), emit(d, n, m), 0));
  296. }
  297. public static void EmitScalarUnaryOpSx(ArmEmitterContext context, Func1I emit)
  298. {
  299. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  300. Operand n = EmitVectorExtractSx(context, op.Rn, 0, op.Size);
  301. Operand d = EmitVectorInsert(context, context.VectorZero(), emit(n), 0, op.Size);
  302. context.Copy(GetVec(op.Rd), d);
  303. }
  304. public static void EmitScalarBinaryOpSx(ArmEmitterContext context, Func2I emit)
  305. {
  306. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  307. Operand n = EmitVectorExtractSx(context, op.Rn, 0, op.Size);
  308. Operand m = EmitVectorExtractSx(context, op.Rm, 0, op.Size);
  309. Operand d = EmitVectorInsert(context, context.VectorZero(), emit(n, m), 0, op.Size);
  310. context.Copy(GetVec(op.Rd), d);
  311. }
  312. public static void EmitScalarUnaryOpZx(ArmEmitterContext context, Func1I emit)
  313. {
  314. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  315. Operand n = EmitVectorExtractZx(context, op.Rn, 0, op.Size);
  316. Operand d = EmitVectorInsert(context, context.VectorZero(), emit(n), 0, op.Size);
  317. context.Copy(GetVec(op.Rd), d);
  318. }
  319. public static void EmitScalarBinaryOpZx(ArmEmitterContext context, Func2I emit)
  320. {
  321. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  322. Operand n = EmitVectorExtractZx(context, op.Rn, 0, op.Size);
  323. Operand m = EmitVectorExtractZx(context, op.Rm, 0, op.Size);
  324. Operand d = EmitVectorInsert(context, context.VectorZero(), emit(n, m), 0, op.Size);
  325. context.Copy(GetVec(op.Rd), d);
  326. }
  327. public static void EmitScalarTernaryOpZx(ArmEmitterContext context, Func3I emit)
  328. {
  329. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  330. Operand d = EmitVectorExtractZx(context, op.Rd, 0, op.Size);
  331. Operand n = EmitVectorExtractZx(context, op.Rn, 0, op.Size);
  332. Operand m = EmitVectorExtractZx(context, op.Rm, 0, op.Size);
  333. d = EmitVectorInsert(context, context.VectorZero(), emit(d, n, m), 0, op.Size);
  334. context.Copy(GetVec(op.Rd), d);
  335. }
  336. public static void EmitScalarUnaryOpF(ArmEmitterContext context, Func1I emit)
  337. {
  338. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  339. OperandType type = (op.Size & 1) != 0 ? OperandType.FP64 : OperandType.FP32;
  340. Operand n = context.VectorExtract(type, GetVec(op.Rn), 0);
  341. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), emit(n), 0));
  342. }
  343. public static void EmitScalarBinaryOpF(ArmEmitterContext context, Func2I emit)
  344. {
  345. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  346. OperandType type = (op.Size & 1) != 0 ? OperandType.FP64 : OperandType.FP32;
  347. Operand n = context.VectorExtract(type, GetVec(op.Rn), 0);
  348. Operand m = context.VectorExtract(type, GetVec(op.Rm), 0);
  349. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), emit(n, m), 0));
  350. }
  351. public static void EmitScalarTernaryRaOpF(ArmEmitterContext context, Func3I emit)
  352. {
  353. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  354. OperandType type = (op.Size & 1) != 0 ? OperandType.FP64 : OperandType.FP32;
  355. Operand a = context.VectorExtract(type, GetVec(op.Ra), 0);
  356. Operand n = context.VectorExtract(type, GetVec(op.Rn), 0);
  357. Operand m = context.VectorExtract(type, GetVec(op.Rm), 0);
  358. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), emit(a, n, m), 0));
  359. }
  360. public static void EmitVectorUnaryOpF(ArmEmitterContext context, Func1I emit)
  361. {
  362. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  363. Operand res = context.VectorZero();
  364. int sizeF = op.Size & 1;
  365. OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
  366. int elems = op.GetBytesCount() >> sizeF + 2;
  367. for (int index = 0; index < elems; index++)
  368. {
  369. Operand ne = context.VectorExtract(type, GetVec(op.Rn), index);
  370. res = context.VectorInsert(res, emit(ne), index);
  371. }
  372. context.Copy(GetVec(op.Rd), res);
  373. }
  374. public static void EmitVectorBinaryOpF(ArmEmitterContext context, Func2I emit)
  375. {
  376. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  377. Operand res = context.VectorZero();
  378. int sizeF = op.Size & 1;
  379. OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
  380. int elems = op.GetBytesCount() >> sizeF + 2;
  381. for (int index = 0; index < elems; index++)
  382. {
  383. Operand ne = context.VectorExtract(type, GetVec(op.Rn), index);
  384. Operand me = context.VectorExtract(type, GetVec(op.Rm), index);
  385. res = context.VectorInsert(res, emit(ne, me), index);
  386. }
  387. context.Copy(GetVec(op.Rd), res);
  388. }
  389. public static void EmitVectorTernaryOpF(ArmEmitterContext context, Func3I emit)
  390. {
  391. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  392. Operand res = context.VectorZero();
  393. int sizeF = op.Size & 1;
  394. OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
  395. int elems = op.GetBytesCount() >> sizeF + 2;
  396. for (int index = 0; index < elems; index++)
  397. {
  398. Operand de = context.VectorExtract(type, GetVec(op.Rd), index);
  399. Operand ne = context.VectorExtract(type, GetVec(op.Rn), index);
  400. Operand me = context.VectorExtract(type, GetVec(op.Rm), index);
  401. res = context.VectorInsert(res, emit(de, ne, me), index);
  402. }
  403. context.Copy(GetVec(op.Rd), res);
  404. }
  405. public static void EmitVectorBinaryOpByElemF(ArmEmitterContext context, Func2I emit)
  406. {
  407. OpCodeSimdRegElemF op = (OpCodeSimdRegElemF)context.CurrOp;
  408. Operand res = context.VectorZero();
  409. int sizeF = op.Size & 1;
  410. OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
  411. int elems = op.GetBytesCount() >> sizeF + 2;
  412. for (int index = 0; index < elems; index++)
  413. {
  414. Operand ne = context.VectorExtract(type, GetVec(op.Rn), index);
  415. Operand me = context.VectorExtract(type, GetVec(op.Rm), op.Index);
  416. res = context.VectorInsert(res, emit(ne, me), index);
  417. }
  418. context.Copy(GetVec(op.Rd), res);
  419. }
  420. public static void EmitVectorTernaryOpByElemF(ArmEmitterContext context, Func3I emit)
  421. {
  422. OpCodeSimdRegElemF op = (OpCodeSimdRegElemF)context.CurrOp;
  423. Operand res = context.VectorZero();
  424. int sizeF = op.Size & 1;
  425. OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
  426. int elems = op.GetBytesCount() >> sizeF + 2;
  427. for (int index = 0; index < elems; index++)
  428. {
  429. Operand de = context.VectorExtract(type, GetVec(op.Rd), index);
  430. Operand ne = context.VectorExtract(type, GetVec(op.Rn), index);
  431. Operand me = context.VectorExtract(type, GetVec(op.Rm), op.Index);
  432. res = context.VectorInsert(res, emit(de, ne, me), index);
  433. }
  434. context.Copy(GetVec(op.Rd), res);
  435. }
  436. public static void EmitVectorUnaryOpSx(ArmEmitterContext context, Func1I emit)
  437. {
  438. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  439. Operand res = context.VectorZero();
  440. int elems = op.GetBytesCount() >> op.Size;
  441. for (int index = 0; index < elems; index++)
  442. {
  443. Operand ne = EmitVectorExtractSx(context, op.Rn, index, op.Size);
  444. res = EmitVectorInsert(context, res, emit(ne), index, op.Size);
  445. }
  446. context.Copy(GetVec(op.Rd), res);
  447. }
  448. public static void EmitVectorBinaryOpSx(ArmEmitterContext context, Func2I emit)
  449. {
  450. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  451. Operand res = context.VectorZero();
  452. int elems = op.GetBytesCount() >> op.Size;
  453. for (int index = 0; index < elems; index++)
  454. {
  455. Operand ne = EmitVectorExtractSx(context, op.Rn, index, op.Size);
  456. Operand me = EmitVectorExtractSx(context, op.Rm, index, op.Size);
  457. res = EmitVectorInsert(context, res, emit(ne, me), index, op.Size);
  458. }
  459. context.Copy(GetVec(op.Rd), res);
  460. }
  461. public static void EmitVectorTernaryOpSx(ArmEmitterContext context, Func3I emit)
  462. {
  463. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  464. Operand res = context.VectorZero();
  465. int elems = op.GetBytesCount() >> op.Size;
  466. for (int index = 0; index < elems; index++)
  467. {
  468. Operand de = EmitVectorExtractSx(context, op.Rd, index, op.Size);
  469. Operand ne = EmitVectorExtractSx(context, op.Rn, index, op.Size);
  470. Operand me = EmitVectorExtractSx(context, op.Rm, index, op.Size);
  471. res = EmitVectorInsert(context, res, emit(de, ne, me), index, op.Size);
  472. }
  473. context.Copy(GetVec(op.Rd), res);
  474. }
  475. public static void EmitVectorUnaryOpZx(ArmEmitterContext context, Func1I emit)
  476. {
  477. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  478. Operand res = context.VectorZero();
  479. int elems = op.GetBytesCount() >> op.Size;
  480. for (int index = 0; index < elems; index++)
  481. {
  482. Operand ne = EmitVectorExtractZx(context, op.Rn, index, op.Size);
  483. res = EmitVectorInsert(context, res, emit(ne), index, op.Size);
  484. }
  485. context.Copy(GetVec(op.Rd), res);
  486. }
  487. public static void EmitVectorBinaryOpZx(ArmEmitterContext context, Func2I emit)
  488. {
  489. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  490. Operand res = context.VectorZero();
  491. int elems = op.GetBytesCount() >> op.Size;
  492. for (int index = 0; index < elems; index++)
  493. {
  494. Operand ne = EmitVectorExtractZx(context, op.Rn, index, op.Size);
  495. Operand me = EmitVectorExtractZx(context, op.Rm, index, op.Size);
  496. res = EmitVectorInsert(context, res, emit(ne, me), index, op.Size);
  497. }
  498. context.Copy(GetVec(op.Rd), res);
  499. }
  500. public static void EmitVectorTernaryOpZx(ArmEmitterContext context, Func3I emit)
  501. {
  502. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  503. Operand res = context.VectorZero();
  504. int elems = op.GetBytesCount() >> op.Size;
  505. for (int index = 0; index < elems; index++)
  506. {
  507. Operand de = EmitVectorExtractZx(context, op.Rd, index, op.Size);
  508. Operand ne = EmitVectorExtractZx(context, op.Rn, index, op.Size);
  509. Operand me = EmitVectorExtractZx(context, op.Rm, index, op.Size);
  510. res = EmitVectorInsert(context, res, emit(de, ne, me), index, op.Size);
  511. }
  512. context.Copy(GetVec(op.Rd), res);
  513. }
  514. public static void EmitVectorBinaryOpByElemSx(ArmEmitterContext context, Func2I emit)
  515. {
  516. OpCodeSimdRegElem op = (OpCodeSimdRegElem)context.CurrOp;
  517. Operand res = context.VectorZero();
  518. Operand me = EmitVectorExtractSx(context, op.Rm, op.Index, op.Size);
  519. int elems = op.GetBytesCount() >> op.Size;
  520. for (int index = 0; index < elems; index++)
  521. {
  522. Operand ne = EmitVectorExtractSx(context, op.Rn, index, op.Size);
  523. res = EmitVectorInsert(context, res, emit(ne, me), index, op.Size);
  524. }
  525. context.Copy(GetVec(op.Rd), res);
  526. }
  527. public static void EmitVectorBinaryOpByElemZx(ArmEmitterContext context, Func2I emit)
  528. {
  529. OpCodeSimdRegElem op = (OpCodeSimdRegElem)context.CurrOp;
  530. Operand res = context.VectorZero();
  531. Operand me = EmitVectorExtractZx(context, op.Rm, op.Index, op.Size);
  532. int elems = op.GetBytesCount() >> op.Size;
  533. for (int index = 0; index < elems; index++)
  534. {
  535. Operand ne = EmitVectorExtractZx(context, op.Rn, index, op.Size);
  536. res = EmitVectorInsert(context, res, emit(ne, me), index, op.Size);
  537. }
  538. context.Copy(GetVec(op.Rd), res);
  539. }
  540. public static void EmitVectorTernaryOpByElemZx(ArmEmitterContext context, Func3I emit)
  541. {
  542. OpCodeSimdRegElem op = (OpCodeSimdRegElem)context.CurrOp;
  543. Operand res = context.VectorZero();
  544. Operand me = EmitVectorExtractZx(context, op.Rm, op.Index, op.Size);
  545. int elems = op.GetBytesCount() >> op.Size;
  546. for (int index = 0; index < elems; index++)
  547. {
  548. Operand de = EmitVectorExtractZx(context, op.Rd, index, op.Size);
  549. Operand ne = EmitVectorExtractZx(context, op.Rn, index, op.Size);
  550. res = EmitVectorInsert(context, res, emit(de, ne, me), index, op.Size);
  551. }
  552. context.Copy(GetVec(op.Rd), res);
  553. }
  554. public static void EmitVectorImmUnaryOp(ArmEmitterContext context, Func1I emit)
  555. {
  556. OpCodeSimdImm op = (OpCodeSimdImm)context.CurrOp;
  557. Operand imm = Const(op.Immediate);
  558. Operand res = context.VectorZero();
  559. int elems = op.GetBytesCount() >> op.Size;
  560. for (int index = 0; index < elems; index++)
  561. {
  562. res = EmitVectorInsert(context, res, emit(imm), index, op.Size);
  563. }
  564. context.Copy(GetVec(op.Rd), res);
  565. }
  566. public static void EmitVectorImmBinaryOp(ArmEmitterContext context, Func2I emit)
  567. {
  568. OpCodeSimdImm op = (OpCodeSimdImm)context.CurrOp;
  569. Operand imm = Const(op.Immediate);
  570. Operand res = context.VectorZero();
  571. int elems = op.GetBytesCount() >> op.Size;
  572. for (int index = 0; index < elems; index++)
  573. {
  574. Operand de = EmitVectorExtractZx(context, op.Rd, index, op.Size);
  575. res = EmitVectorInsert(context, res, emit(de, imm), index, op.Size);
  576. }
  577. context.Copy(GetVec(op.Rd), res);
  578. }
  579. public static void EmitVectorWidenRmBinaryOpSx(ArmEmitterContext context, Func2I emit)
  580. {
  581. EmitVectorWidenRmBinaryOp(context, emit, signed: true);
  582. }
  583. public static void EmitVectorWidenRmBinaryOpZx(ArmEmitterContext context, Func2I emit)
  584. {
  585. EmitVectorWidenRmBinaryOp(context, emit, signed: false);
  586. }
  587. private static void EmitVectorWidenRmBinaryOp(ArmEmitterContext context, Func2I emit, bool signed)
  588. {
  589. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  590. Operand res = context.VectorZero();
  591. int elems = 8 >> op.Size;
  592. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  593. for (int index = 0; index < elems; index++)
  594. {
  595. Operand ne = EmitVectorExtract(context, op.Rn, index, op.Size + 1, signed);
  596. Operand me = EmitVectorExtract(context, op.Rm, part + index, op.Size, signed);
  597. res = EmitVectorInsert(context, res, emit(ne, me), index, op.Size + 1);
  598. }
  599. context.Copy(GetVec(op.Rd), res);
  600. }
  601. public static void EmitVectorWidenRnRmBinaryOpSx(ArmEmitterContext context, Func2I emit)
  602. {
  603. EmitVectorWidenRnRmBinaryOp(context, emit, signed: true);
  604. }
  605. public static void EmitVectorWidenRnRmBinaryOpZx(ArmEmitterContext context, Func2I emit)
  606. {
  607. EmitVectorWidenRnRmBinaryOp(context, emit, signed: false);
  608. }
  609. private static void EmitVectorWidenRnRmBinaryOp(ArmEmitterContext context, Func2I emit, bool signed)
  610. {
  611. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  612. Operand res = context.VectorZero();
  613. int elems = 8 >> op.Size;
  614. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  615. for (int index = 0; index < elems; index++)
  616. {
  617. Operand ne = EmitVectorExtract(context, op.Rn, part + index, op.Size, signed);
  618. Operand me = EmitVectorExtract(context, op.Rm, part + index, op.Size, signed);
  619. res = EmitVectorInsert(context, res, emit(ne, me), index, op.Size + 1);
  620. }
  621. context.Copy(GetVec(op.Rd), res);
  622. }
  623. public static void EmitVectorWidenRnRmTernaryOpSx(ArmEmitterContext context, Func3I emit)
  624. {
  625. EmitVectorWidenRnRmTernaryOp(context, emit, signed: true);
  626. }
  627. public static void EmitVectorWidenRnRmTernaryOpZx(ArmEmitterContext context, Func3I emit)
  628. {
  629. EmitVectorWidenRnRmTernaryOp(context, emit, signed: false);
  630. }
  631. private static void EmitVectorWidenRnRmTernaryOp(ArmEmitterContext context, Func3I emit, bool signed)
  632. {
  633. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  634. Operand res = context.VectorZero();
  635. int elems = 8 >> op.Size;
  636. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  637. for (int index = 0; index < elems; index++)
  638. {
  639. Operand de = EmitVectorExtract(context, op.Rd, index, op.Size + 1, signed);
  640. Operand ne = EmitVectorExtract(context, op.Rn, part + index, op.Size, signed);
  641. Operand me = EmitVectorExtract(context, op.Rm, part + index, op.Size, signed);
  642. res = EmitVectorInsert(context, res, emit(de, ne, me), index, op.Size + 1);
  643. }
  644. context.Copy(GetVec(op.Rd), res);
  645. }
  646. public static void EmitVectorWidenBinaryOpByElemSx(ArmEmitterContext context, Func2I emit)
  647. {
  648. EmitVectorWidenBinaryOpByElem(context, emit, signed: true);
  649. }
  650. public static void EmitVectorWidenBinaryOpByElemZx(ArmEmitterContext context, Func2I emit)
  651. {
  652. EmitVectorWidenBinaryOpByElem(context, emit, signed: false);
  653. }
  654. private static void EmitVectorWidenBinaryOpByElem(ArmEmitterContext context, Func2I emit, bool signed)
  655. {
  656. OpCodeSimdRegElem op = (OpCodeSimdRegElem)context.CurrOp;
  657. Operand res = context.VectorZero();
  658. Operand me = EmitVectorExtract(context, op.Rm, op.Index, op.Size, signed);
  659. int elems = 8 >> op.Size;
  660. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  661. for (int index = 0; index < elems; index++)
  662. {
  663. Operand ne = EmitVectorExtract(context, op.Rn, part + index, op.Size, signed);
  664. res = EmitVectorInsert(context, res, emit(ne, me), index, op.Size + 1);
  665. }
  666. context.Copy(GetVec(op.Rd), res);
  667. }
  668. public static void EmitVectorWidenTernaryOpByElemSx(ArmEmitterContext context, Func3I emit)
  669. {
  670. EmitVectorWidenTernaryOpByElem(context, emit, signed: true);
  671. }
  672. public static void EmitVectorWidenTernaryOpByElemZx(ArmEmitterContext context, Func3I emit)
  673. {
  674. EmitVectorWidenTernaryOpByElem(context, emit, signed: false);
  675. }
  676. private static void EmitVectorWidenTernaryOpByElem(ArmEmitterContext context, Func3I emit, bool signed)
  677. {
  678. OpCodeSimdRegElem op = (OpCodeSimdRegElem)context.CurrOp;
  679. Operand res = context.VectorZero();
  680. Operand me = EmitVectorExtract(context, op.Rm, op.Index, op.Size, signed);
  681. int elems = 8 >> op.Size;
  682. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  683. for (int index = 0; index < elems; index++)
  684. {
  685. Operand de = EmitVectorExtract(context, op.Rd, index, op.Size + 1, signed);
  686. Operand ne = EmitVectorExtract(context, op.Rn, part + index, op.Size, signed);
  687. res = EmitVectorInsert(context, res, emit(de, ne, me), index, op.Size + 1);
  688. }
  689. context.Copy(GetVec(op.Rd), res);
  690. }
  691. public static void EmitVectorPairwiseOpSx(ArmEmitterContext context, Func2I emit)
  692. {
  693. EmitVectorPairwiseOp(context, emit, signed: true);
  694. }
  695. public static void EmitVectorPairwiseOpZx(ArmEmitterContext context, Func2I emit)
  696. {
  697. EmitVectorPairwiseOp(context, emit, signed: false);
  698. }
  699. private static void EmitVectorPairwiseOp(ArmEmitterContext context, Func2I emit, bool signed)
  700. {
  701. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  702. Operand res = context.VectorZero();
  703. int pairs = op.GetPairsCount() >> op.Size;
  704. for (int index = 0; index < pairs; index++)
  705. {
  706. int pairIndex = index << 1;
  707. Operand n0 = EmitVectorExtract(context, op.Rn, pairIndex, op.Size, signed);
  708. Operand n1 = EmitVectorExtract(context, op.Rn, pairIndex + 1, op.Size, signed);
  709. Operand m0 = EmitVectorExtract(context, op.Rm, pairIndex, op.Size, signed);
  710. Operand m1 = EmitVectorExtract(context, op.Rm, pairIndex + 1, op.Size, signed);
  711. res = EmitVectorInsert(context, res, emit(n0, n1), index, op.Size);
  712. res = EmitVectorInsert(context, res, emit(m0, m1), pairs + index, op.Size);
  713. }
  714. context.Copy(GetVec(op.Rd), res);
  715. }
  716. public static void EmitSsse3VectorPairwiseOp(ArmEmitterContext context, Intrinsic[] inst)
  717. {
  718. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  719. Operand n = GetVec(op.Rn);
  720. Operand m = GetVec(op.Rm);
  721. if (op.RegisterSize == RegisterSize.Simd64)
  722. {
  723. Operand zeroEvenMask = X86GetElements(context, ZeroMask, EvenMasks[op.Size]);
  724. Operand zeroOddMask = X86GetElements(context, ZeroMask, OddMasks [op.Size]);
  725. Operand mN = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, n, m); // m:n
  726. Operand left = context.AddIntrinsic(Intrinsic.X86Pshufb, mN, zeroEvenMask); // 0:even from m:n
  727. Operand right = context.AddIntrinsic(Intrinsic.X86Pshufb, mN, zeroOddMask); // 0:odd from m:n
  728. context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst[op.Size], left, right));
  729. }
  730. else if (op.Size < 3)
  731. {
  732. Operand oddEvenMask = X86GetElements(context, OddMasks[op.Size], EvenMasks[op.Size]);
  733. Operand oddEvenN = context.AddIntrinsic(Intrinsic.X86Pshufb, n, oddEvenMask); // odd:even from n
  734. Operand oddEvenM = context.AddIntrinsic(Intrinsic.X86Pshufb, m, oddEvenMask); // odd:even from m
  735. Operand left = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, oddEvenN, oddEvenM);
  736. Operand right = context.AddIntrinsic(Intrinsic.X86Punpckhqdq, oddEvenN, oddEvenM);
  737. context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst[op.Size], left, right));
  738. }
  739. else
  740. {
  741. Operand left = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, n, m);
  742. Operand right = context.AddIntrinsic(Intrinsic.X86Punpckhqdq, n, m);
  743. context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst[3], left, right));
  744. }
  745. }
  746. public static void EmitVectorAcrossVectorOpSx(ArmEmitterContext context, Func2I emit)
  747. {
  748. EmitVectorAcrossVectorOp(context, emit, signed: true, isLong: false);
  749. }
  750. public static void EmitVectorAcrossVectorOpZx(ArmEmitterContext context, Func2I emit)
  751. {
  752. EmitVectorAcrossVectorOp(context, emit, signed: false, isLong: false);
  753. }
  754. public static void EmitVectorLongAcrossVectorOpSx(ArmEmitterContext context, Func2I emit)
  755. {
  756. EmitVectorAcrossVectorOp(context, emit, signed: true, isLong: true);
  757. }
  758. public static void EmitVectorLongAcrossVectorOpZx(ArmEmitterContext context, Func2I emit)
  759. {
  760. EmitVectorAcrossVectorOp(context, emit, signed: false, isLong: true);
  761. }
  762. private static void EmitVectorAcrossVectorOp(
  763. ArmEmitterContext context,
  764. Func2I emit,
  765. bool signed,
  766. bool isLong)
  767. {
  768. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  769. int elems = op.GetBytesCount() >> op.Size;
  770. Operand res = EmitVectorExtract(context, op.Rn, 0, op.Size, signed);
  771. for (int index = 1; index < elems; index++)
  772. {
  773. Operand n = EmitVectorExtract(context, op.Rn, index, op.Size, signed);
  774. res = emit(res, n);
  775. }
  776. int size = isLong ? op.Size + 1 : op.Size;
  777. Operand d = EmitVectorInsert(context, context.VectorZero(), res, 0, size);
  778. context.Copy(GetVec(op.Rd), d);
  779. }
  780. public static void EmitVectorAcrossVectorOpF(ArmEmitterContext context, Func2I emit)
  781. {
  782. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  783. Debug.Assert((op.Size & 1) == 0 && op.RegisterSize == RegisterSize.Simd128);
  784. Operand res = context.VectorExtract(OperandType.FP32, GetVec(op.Rn), 0);
  785. for (int index = 1; index < 4; index++)
  786. {
  787. Operand n = context.VectorExtract(OperandType.FP32, GetVec(op.Rn), index);
  788. res = emit(res, n);
  789. }
  790. Operand d = context.VectorInsert(context.VectorZero(), res, 0);
  791. context.Copy(GetVec(op.Rd), d);
  792. }
  793. public static void EmitSse2VectorAcrossVectorOpF(ArmEmitterContext context, Func2I emit)
  794. {
  795. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  796. Debug.Assert((op.Size & 1) == 0 && op.RegisterSize == RegisterSize.Simd128);
  797. const int sm0 = 0 << 6 | 0 << 4 | 0 << 2 | 0 << 0;
  798. const int sm1 = 1 << 6 | 1 << 4 | 1 << 2 | 1 << 0;
  799. const int sm2 = 2 << 6 | 2 << 4 | 2 << 2 | 2 << 0;
  800. const int sm3 = 3 << 6 | 3 << 4 | 3 << 2 | 3 << 0;
  801. Operand nCopy = context.Copy(GetVec(op.Rn));
  802. Operand part0 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, nCopy, Const(sm0));
  803. Operand part1 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, nCopy, Const(sm1));
  804. Operand part2 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, nCopy, Const(sm2));
  805. Operand part3 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, nCopy, Const(sm3));
  806. Operand res = emit(emit(part0, part1), emit(part2, part3));
  807. context.Copy(GetVec(op.Rd), context.VectorZeroUpper96(res));
  808. }
  809. public static void EmitScalarPairwiseOpF(ArmEmitterContext context, Func2I emit)
  810. {
  811. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  812. OperandType type = (op.Size & 1) != 0 ? OperandType.FP64 : OperandType.FP32;
  813. Operand ne0 = context.VectorExtract(type, GetVec(op.Rn), 0);
  814. Operand ne1 = context.VectorExtract(type, GetVec(op.Rn), 1);
  815. Operand res = context.VectorInsert(context.VectorZero(), emit(ne0, ne1), 0);
  816. context.Copy(GetVec(op.Rd), res);
  817. }
  818. public static void EmitSse2ScalarPairwiseOpF(ArmEmitterContext context, Func2I emit)
  819. {
  820. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  821. Operand n = GetVec(op.Rn);
  822. Operand op0, op1;
  823. if ((op.Size & 1) == 0)
  824. {
  825. const int sm0 = 2 << 6 | 2 << 4 | 2 << 2 | 0 << 0;
  826. const int sm1 = 2 << 6 | 2 << 4 | 2 << 2 | 1 << 0;
  827. Operand zeroN = context.VectorZeroUpper64(n);
  828. op0 = context.AddIntrinsic(Intrinsic.X86Pshufd, zeroN, Const(sm0));
  829. op1 = context.AddIntrinsic(Intrinsic.X86Pshufd, zeroN, Const(sm1));
  830. }
  831. else /* if ((op.Size & 1) == 1) */
  832. {
  833. Operand zero = context.VectorZero();
  834. op0 = context.AddIntrinsic(Intrinsic.X86Movlhps, n, zero);
  835. op1 = context.AddIntrinsic(Intrinsic.X86Movhlps, zero, n);
  836. }
  837. context.Copy(GetVec(op.Rd), emit(op0, op1));
  838. }
  839. public static void EmitVectorPairwiseOpF(ArmEmitterContext context, Func2I emit)
  840. {
  841. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  842. Operand res = context.VectorZero();
  843. int sizeF = op.Size & 1;
  844. OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
  845. int pairs = op.GetPairsCount() >> sizeF + 2;
  846. for (int index = 0; index < pairs; index++)
  847. {
  848. int pairIndex = index << 1;
  849. Operand n0 = context.VectorExtract(type, GetVec(op.Rn), pairIndex);
  850. Operand n1 = context.VectorExtract(type, GetVec(op.Rn), pairIndex + 1);
  851. Operand m0 = context.VectorExtract(type, GetVec(op.Rm), pairIndex);
  852. Operand m1 = context.VectorExtract(type, GetVec(op.Rm), pairIndex + 1);
  853. res = context.VectorInsert(res, emit(n0, n1), index);
  854. res = context.VectorInsert(res, emit(m0, m1), pairs + index);
  855. }
  856. context.Copy(GetVec(op.Rd), res);
  857. }
  858. public static void EmitSse2VectorPairwiseOpF(ArmEmitterContext context, Func2I emit)
  859. {
  860. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  861. Operand nCopy = context.Copy(GetVec(op.Rn));
  862. Operand mCopy = context.Copy(GetVec(op.Rm));
  863. int sizeF = op.Size & 1;
  864. if (sizeF == 0)
  865. {
  866. if (op.RegisterSize == RegisterSize.Simd64)
  867. {
  868. Operand unpck = context.AddIntrinsic(Intrinsic.X86Unpcklps, nCopy, mCopy);
  869. Operand zero = context.VectorZero();
  870. Operand part0 = context.AddIntrinsic(Intrinsic.X86Movlhps, unpck, zero);
  871. Operand part1 = context.AddIntrinsic(Intrinsic.X86Movhlps, zero, unpck);
  872. context.Copy(GetVec(op.Rd), emit(part0, part1));
  873. }
  874. else /* if (op.RegisterSize == RegisterSize.Simd128) */
  875. {
  876. const int sm0 = 2 << 6 | 0 << 4 | 2 << 2 | 0 << 0;
  877. const int sm1 = 3 << 6 | 1 << 4 | 3 << 2 | 1 << 0;
  878. Operand part0 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, mCopy, Const(sm0));
  879. Operand part1 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, mCopy, Const(sm1));
  880. context.Copy(GetVec(op.Rd), emit(part0, part1));
  881. }
  882. }
  883. else /* if (sizeF == 1) */
  884. {
  885. Operand part0 = context.AddIntrinsic(Intrinsic.X86Unpcklpd, nCopy, mCopy);
  886. Operand part1 = context.AddIntrinsic(Intrinsic.X86Unpckhpd, nCopy, mCopy);
  887. context.Copy(GetVec(op.Rd), emit(part0, part1));
  888. }
  889. }
  890. [Flags]
  891. public enum Mxcsr
  892. {
  893. Ftz = 1 << 15, // Flush To Zero.
  894. Um = 1 << 11, // Underflow Mask.
  895. Dm = 1 << 8, // Denormal Mask.
  896. Daz = 1 << 6 // Denormals Are Zero.
  897. }
  898. public static void EmitSseOrAvxEnterFtzAndDazModesOpF(ArmEmitterContext context, out Operand isTrue)
  899. {
  900. isTrue = context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetFpcrFz)));
  901. Operand lblTrue = Label();
  902. context.BranchIfFalse(lblTrue, isTrue);
  903. context.AddIntrinsicNoRet(Intrinsic.X86Mxcsrmb, Const((int)(Mxcsr.Ftz | Mxcsr.Um | Mxcsr.Dm | Mxcsr.Daz)));
  904. context.MarkLabel(lblTrue);
  905. }
  906. public static void EmitSseOrAvxExitFtzAndDazModesOpF(ArmEmitterContext context, Operand isTrue = null)
  907. {
  908. isTrue ??= context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetFpcrFz)));
  909. Operand lblTrue = Label();
  910. context.BranchIfFalse(lblTrue, isTrue);
  911. context.AddIntrinsicNoRet(Intrinsic.X86Mxcsrub, Const((int)(Mxcsr.Ftz | Mxcsr.Daz)));
  912. context.MarkLabel(lblTrue);
  913. }
  914. public enum CmpCondition
  915. {
  916. // Legacy Sse.
  917. Equal = 0, // Ordered, non-signaling.
  918. LessThan = 1, // Ordered, signaling.
  919. LessThanOrEqual = 2, // Ordered, signaling.
  920. UnorderedQ = 3, // Non-signaling.
  921. NotLessThan = 5, // Unordered, signaling.
  922. NotLessThanOrEqual = 6, // Unordered, signaling.
  923. OrderedQ = 7, // Non-signaling.
  924. // Vex.
  925. GreaterThanOrEqual = 13, // Ordered, signaling.
  926. GreaterThan = 14, // Ordered, signaling.
  927. OrderedS = 23 // Signaling.
  928. }
  929. [Flags]
  930. public enum SaturatingFlags
  931. {
  932. Scalar = 1 << 0,
  933. Signed = 1 << 1,
  934. Add = 1 << 2,
  935. Sub = 1 << 3,
  936. Accumulate = 1 << 4,
  937. ScalarSx = Scalar | Signed,
  938. ScalarZx = Scalar,
  939. VectorSx = Signed,
  940. VectorZx = 0
  941. }
  942. public static void EmitScalarSaturatingUnaryOpSx(ArmEmitterContext context, Func1I emit)
  943. {
  944. EmitSaturatingUnaryOpSx(context, emit, SaturatingFlags.ScalarSx);
  945. }
  946. public static void EmitVectorSaturatingUnaryOpSx(ArmEmitterContext context, Func1I emit)
  947. {
  948. EmitSaturatingUnaryOpSx(context, emit, SaturatingFlags.VectorSx);
  949. }
  950. private static void EmitSaturatingUnaryOpSx(ArmEmitterContext context, Func1I emit, SaturatingFlags flags)
  951. {
  952. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  953. Operand res = context.VectorZero();
  954. bool scalar = (flags & SaturatingFlags.Scalar) != 0;
  955. int elems = !scalar ? op.GetBytesCount() >> op.Size : 1;
  956. for (int index = 0; index < elems; index++)
  957. {
  958. Operand ne = EmitVectorExtractSx(context, op.Rn, index, op.Size);
  959. Operand de;
  960. if (op.Size <= 2)
  961. {
  962. de = EmitSatQ(context, emit(ne), op.Size, signedSrc: true, signedDst: true);
  963. }
  964. else /* if (op.Size == 3) */
  965. {
  966. de = EmitUnarySignedSatQAbsOrNeg(context, emit(ne));
  967. }
  968. res = EmitVectorInsert(context, res, de, index, op.Size);
  969. }
  970. context.Copy(GetVec(op.Rd), res);
  971. }
  972. public static void EmitScalarSaturatingBinaryOpSx(ArmEmitterContext context, SaturatingFlags flags)
  973. {
  974. EmitSaturatingBinaryOp(context, null, SaturatingFlags.ScalarSx | flags);
  975. }
  976. public static void EmitScalarSaturatingBinaryOpZx(ArmEmitterContext context, SaturatingFlags flags)
  977. {
  978. EmitSaturatingBinaryOp(context, null, SaturatingFlags.ScalarZx | flags);
  979. }
  980. public static void EmitVectorSaturatingBinaryOpSx(ArmEmitterContext context, SaturatingFlags flags)
  981. {
  982. EmitSaturatingBinaryOp(context, null, SaturatingFlags.VectorSx | flags);
  983. }
  984. public static void EmitVectorSaturatingBinaryOpZx(ArmEmitterContext context, SaturatingFlags flags)
  985. {
  986. EmitSaturatingBinaryOp(context, null, SaturatingFlags.VectorZx | flags);
  987. }
  988. public static void EmitSaturatingBinaryOp(ArmEmitterContext context, Func2I emit, SaturatingFlags flags)
  989. {
  990. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  991. Operand res = context.VectorZero();
  992. bool scalar = (flags & SaturatingFlags.Scalar) != 0;
  993. bool signed = (flags & SaturatingFlags.Signed) != 0;
  994. bool add = (flags & SaturatingFlags.Add) != 0;
  995. bool sub = (flags & SaturatingFlags.Sub) != 0;
  996. bool accumulate = (flags & SaturatingFlags.Accumulate) != 0;
  997. int elems = !scalar ? op.GetBytesCount() >> op.Size : 1;
  998. if (add || sub)
  999. {
  1000. OpCodeSimdReg opReg = (OpCodeSimdReg)op;
  1001. for (int index = 0; index < elems; index++)
  1002. {
  1003. Operand de;
  1004. Operand ne = EmitVectorExtract(context, opReg.Rn, index, op.Size, signed);
  1005. Operand me = EmitVectorExtract(context, opReg.Rm, index, op.Size, signed);
  1006. if (op.Size <= 2)
  1007. {
  1008. Operand temp = add ? context.Add(ne, me) : context.Subtract(ne, me);
  1009. de = EmitSatQ(context, temp, op.Size, signedSrc: true, signedDst: signed);
  1010. }
  1011. else if (add) /* if (op.Size == 3) */
  1012. {
  1013. de = EmitBinarySatQAdd(context, ne, me, signed);
  1014. }
  1015. else /* if (sub) */
  1016. {
  1017. de = EmitBinarySatQSub(context, ne, me, signed);
  1018. }
  1019. res = EmitVectorInsert(context, res, de, index, op.Size);
  1020. }
  1021. }
  1022. else if (accumulate)
  1023. {
  1024. for (int index = 0; index < elems; index++)
  1025. {
  1026. Operand de;
  1027. Operand ne = EmitVectorExtract(context, op.Rn, index, op.Size, !signed);
  1028. Operand me = EmitVectorExtract(context, op.Rd, index, op.Size, signed);
  1029. if (op.Size <= 2)
  1030. {
  1031. Operand temp = context.Add(ne, me);
  1032. de = EmitSatQ(context, temp, op.Size, signedSrc: true, signedDst: signed);
  1033. }
  1034. else /* if (op.Size == 3) */
  1035. {
  1036. de = EmitBinarySatQAccumulate(context, ne, me, signed);
  1037. }
  1038. res = EmitVectorInsert(context, res, de, index, op.Size);
  1039. }
  1040. }
  1041. else
  1042. {
  1043. OpCodeSimdReg opReg = (OpCodeSimdReg)op;
  1044. for (int index = 0; index < elems; index++)
  1045. {
  1046. Operand ne = EmitVectorExtract(context, opReg.Rn, index, op.Size, signed);
  1047. Operand me = EmitVectorExtract(context, opReg.Rm, index, op.Size, signed);
  1048. Operand de = EmitSatQ(context, emit(ne, me), op.Size, true, signed);
  1049. res = EmitVectorInsert(context, res, de, index, op.Size);
  1050. }
  1051. }
  1052. context.Copy(GetVec(op.Rd), res);
  1053. }
  1054. [Flags]
  1055. public enum SaturatingNarrowFlags
  1056. {
  1057. Scalar = 1 << 0,
  1058. SignedSrc = 1 << 1,
  1059. SignedDst = 1 << 2,
  1060. ScalarSxSx = Scalar | SignedSrc | SignedDst,
  1061. ScalarSxZx = Scalar | SignedSrc,
  1062. ScalarZxZx = Scalar,
  1063. VectorSxSx = SignedSrc | SignedDst,
  1064. VectorSxZx = SignedSrc,
  1065. VectorZxZx = 0
  1066. }
  1067. public static void EmitSaturatingNarrowOp(ArmEmitterContext context, SaturatingNarrowFlags flags)
  1068. {
  1069. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  1070. bool scalar = (flags & SaturatingNarrowFlags.Scalar) != 0;
  1071. bool signedSrc = (flags & SaturatingNarrowFlags.SignedSrc) != 0;
  1072. bool signedDst = (flags & SaturatingNarrowFlags.SignedDst) != 0;
  1073. int elems = !scalar ? 8 >> op.Size : 1;
  1074. int part = !scalar && (op.RegisterSize == RegisterSize.Simd128) ? elems : 0;
  1075. Operand d = GetVec(op.Rd);
  1076. Operand res = part == 0 ? context.VectorZero() : context.Copy(d);
  1077. for (int index = 0; index < elems; index++)
  1078. {
  1079. Operand ne = EmitVectorExtract(context, op.Rn, index, op.Size + 1, signedSrc);
  1080. Operand temp = EmitSatQ(context, ne, op.Size, signedSrc, signedDst);
  1081. res = EmitVectorInsert(context, res, temp, part + index, op.Size);
  1082. }
  1083. context.Copy(d, res);
  1084. }
  1085. // TSrc (16bit, 32bit, 64bit; signed, unsigned) > TDst (8bit, 16bit, 32bit; signed, unsigned).
  1086. public static Operand EmitSatQ(ArmEmitterContext context, Operand op, int sizeDst, bool signedSrc, bool signedDst)
  1087. {
  1088. if ((uint)sizeDst > 2u)
  1089. {
  1090. throw new ArgumentOutOfRangeException(nameof(sizeDst));
  1091. }
  1092. MethodInfo info;
  1093. if (signedSrc)
  1094. {
  1095. info = signedDst
  1096. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SignedSrcSignedDstSatQ))
  1097. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SignedSrcUnsignedDstSatQ));
  1098. }
  1099. else
  1100. {
  1101. info = signedDst
  1102. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.UnsignedSrcSignedDstSatQ))
  1103. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.UnsignedSrcUnsignedDstSatQ));
  1104. }
  1105. return context.Call(info, op, Const(sizeDst));
  1106. }
  1107. // TSrc (64bit) == TDst (64bit); signed.
  1108. public static Operand EmitUnarySignedSatQAbsOrNeg(ArmEmitterContext context, Operand op)
  1109. {
  1110. Debug.Assert(((OpCodeSimd)context.CurrOp).Size == 3, "Invalid element size.");
  1111. return context.Call(typeof(SoftFallback).GetMethod(nameof(SoftFallback.UnarySignedSatQAbsOrNeg)), op);
  1112. }
  1113. // TSrcs (64bit) == TDst (64bit); signed, unsigned.
  1114. public static Operand EmitBinarySatQAdd(ArmEmitterContext context, Operand op1, Operand op2, bool signed)
  1115. {
  1116. Debug.Assert(((OpCodeSimd)context.CurrOp).Size == 3, "Invalid element size.");
  1117. MethodInfo info = signed
  1118. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.BinarySignedSatQAdd))
  1119. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.BinaryUnsignedSatQAdd));
  1120. return context.Call(info, op1, op2);
  1121. }
  1122. // TSrcs (64bit) == TDst (64bit); signed, unsigned.
  1123. public static Operand EmitBinarySatQSub(ArmEmitterContext context, Operand op1, Operand op2, bool signed)
  1124. {
  1125. Debug.Assert(((OpCodeSimd)context.CurrOp).Size == 3, "Invalid element size.");
  1126. MethodInfo info = signed
  1127. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.BinarySignedSatQSub))
  1128. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.BinaryUnsignedSatQSub));
  1129. return context.Call(info, op1, op2);
  1130. }
  1131. // TSrcs (64bit) == TDst (64bit); signed, unsigned.
  1132. public static Operand EmitBinarySatQAccumulate(ArmEmitterContext context, Operand op1, Operand op2, bool signed)
  1133. {
  1134. Debug.Assert(((OpCodeSimd)context.CurrOp).Size == 3, "Invalid element size.");
  1135. MethodInfo info = signed
  1136. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.BinarySignedSatQAcc))
  1137. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.BinaryUnsignedSatQAcc));
  1138. return context.Call(info, op1, op2);
  1139. }
  1140. public static Operand EmitFloatAbs(ArmEmitterContext context, Operand value, bool single, bool vector)
  1141. {
  1142. Operand mask;
  1143. if (single)
  1144. {
  1145. mask = vector ? X86GetAllElements(context, -0f) : X86GetScalar(context, -0f);
  1146. }
  1147. else
  1148. {
  1149. mask = vector ? X86GetAllElements(context, -0d) : X86GetScalar(context, -0d);
  1150. }
  1151. return context.AddIntrinsic(single ? Intrinsic.X86Andnps : Intrinsic.X86Andnpd, mask, value);
  1152. }
  1153. public static Operand EmitVectorExtractSx(ArmEmitterContext context, int reg, int index, int size)
  1154. {
  1155. return EmitVectorExtract(context, reg, index, size, true);
  1156. }
  1157. public static Operand EmitVectorExtractZx(ArmEmitterContext context, int reg, int index, int size)
  1158. {
  1159. return EmitVectorExtract(context, reg, index, size, false);
  1160. }
  1161. public static Operand EmitVectorExtract(ArmEmitterContext context, int reg, int index, int size, bool signed)
  1162. {
  1163. ThrowIfInvalid(index, size);
  1164. Operand res = null;
  1165. switch (size)
  1166. {
  1167. case 0:
  1168. res = context.VectorExtract8(GetVec(reg), index);
  1169. break;
  1170. case 1:
  1171. res = context.VectorExtract16(GetVec(reg), index);
  1172. break;
  1173. case 2:
  1174. res = context.VectorExtract(OperandType.I32, GetVec(reg), index);
  1175. break;
  1176. case 3:
  1177. res = context.VectorExtract(OperandType.I64, GetVec(reg), index);
  1178. break;
  1179. }
  1180. if (signed)
  1181. {
  1182. switch (size)
  1183. {
  1184. case 0: res = context.SignExtend8 (OperandType.I64, res); break;
  1185. case 1: res = context.SignExtend16(OperandType.I64, res); break;
  1186. case 2: res = context.SignExtend32(OperandType.I64, res); break;
  1187. }
  1188. }
  1189. else
  1190. {
  1191. switch (size)
  1192. {
  1193. case 0: res = context.ZeroExtend8 (OperandType.I64, res); break;
  1194. case 1: res = context.ZeroExtend16(OperandType.I64, res); break;
  1195. case 2: res = context.ZeroExtend32(OperandType.I64, res); break;
  1196. }
  1197. }
  1198. return res;
  1199. }
  1200. public static Operand EmitVectorInsert(ArmEmitterContext context, Operand vector, Operand value, int index, int size)
  1201. {
  1202. ThrowIfInvalid(index, size);
  1203. if (size < 3 && value.Type == OperandType.I64)
  1204. {
  1205. value = context.ConvertI64ToI32(value);
  1206. }
  1207. switch (size)
  1208. {
  1209. case 0: vector = context.VectorInsert8 (vector, value, index); break;
  1210. case 1: vector = context.VectorInsert16(vector, value, index); break;
  1211. case 2: vector = context.VectorInsert (vector, value, index); break;
  1212. case 3: vector = context.VectorInsert (vector, value, index); break;
  1213. }
  1214. return vector;
  1215. }
  1216. public static void ThrowIfInvalid(int index, int size)
  1217. {
  1218. if ((uint)size > 3u)
  1219. {
  1220. throw new ArgumentOutOfRangeException(nameof(size));
  1221. }
  1222. if ((uint)index >= 16u >> size)
  1223. {
  1224. throw new ArgumentOutOfRangeException(nameof(index));
  1225. }
  1226. }
  1227. }
  1228. }