InstEmitSimdCvt.cs 56 KB

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  1. using ARMeilleure.Decoders;
  2. using ARMeilleure.IntermediateRepresentation;
  3. using ARMeilleure.State;
  4. using ARMeilleure.Translation;
  5. using System;
  6. using System.Diagnostics;
  7. using System.Reflection;
  8. using static ARMeilleure.Instructions.InstEmitHelper;
  9. using static ARMeilleure.Instructions.InstEmitSimdHelper;
  10. using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
  11. namespace ARMeilleure.Instructions
  12. {
  13. using Func1I = Func<Operand, Operand>;
  14. static partial class InstEmit
  15. {
  16. public static void Fcvt_S(ArmEmitterContext context)
  17. {
  18. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  19. if (op.Size == 0 && op.Opc == 1) // Single -> Double.
  20. {
  21. if (Optimizations.UseSse2)
  22. {
  23. Operand n = GetVec(op.Rn);
  24. Operand res = context.AddIntrinsic(Intrinsic.X86Cvtss2sd, context.VectorZero(), n);
  25. context.Copy(GetVec(op.Rd), res);
  26. }
  27. else
  28. {
  29. Operand ne = context.VectorExtract(OperandType.FP32, GetVec(op.Rn), 0);
  30. Operand res = context.ConvertToFP(OperandType.FP64, ne);
  31. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  32. }
  33. }
  34. else if (op.Size == 1 && op.Opc == 0) // Double -> Single.
  35. {
  36. if (Optimizations.UseSse2)
  37. {
  38. Operand n = GetVec(op.Rn);
  39. Operand res = context.AddIntrinsic(Intrinsic.X86Cvtsd2ss, context.VectorZero(), n);
  40. context.Copy(GetVec(op.Rd), res);
  41. }
  42. else
  43. {
  44. Operand ne = context.VectorExtract(OperandType.FP64, GetVec(op.Rn), 0);
  45. Operand res = context.ConvertToFP(OperandType.FP32, ne);
  46. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  47. }
  48. }
  49. else if (op.Size == 0 && op.Opc == 3) // Single -> Half.
  50. {
  51. if (Optimizations.UseF16c)
  52. {
  53. Debug.Assert(!Optimizations.ForceLegacySse);
  54. Operand n = GetVec(op.Rn);
  55. Operand res = context.AddIntrinsic(Intrinsic.X86Vcvtps2ph, n, Const(X86GetRoundControl(FPRoundingMode.ToNearest)));
  56. res = context.AddIntrinsic(Intrinsic.X86Pslldq, res, Const(14)); // VectorZeroUpper112()
  57. res = context.AddIntrinsic(Intrinsic.X86Psrldq, res, Const(14));
  58. context.Copy(GetVec(op.Rd), res);
  59. }
  60. else
  61. {
  62. Operand ne = context.VectorExtract(OperandType.FP32, GetVec(op.Rn), 0);
  63. Operand res = context.Call(typeof(SoftFloat32_16).GetMethod(nameof(SoftFloat32_16.FPConvert)), ne);
  64. res = context.ZeroExtend16(OperandType.I64, res);
  65. context.Copy(GetVec(op.Rd), EmitVectorInsert(context, context.VectorZero(), res, 0, 1));
  66. }
  67. }
  68. else if (op.Size == 3 && op.Opc == 0) // Half -> Single.
  69. {
  70. if (Optimizations.UseF16c)
  71. {
  72. Debug.Assert(!Optimizations.ForceLegacySse);
  73. Operand res = context.AddIntrinsic(Intrinsic.X86Vcvtph2ps, GetVec(op.Rn));
  74. res = context.VectorZeroUpper96(res);
  75. context.Copy(GetVec(op.Rd), res);
  76. }
  77. else
  78. {
  79. Operand ne = EmitVectorExtractZx(context, op.Rn, 0, 1);
  80. Operand res = context.Call(typeof(SoftFloat16_32).GetMethod(nameof(SoftFloat16_32.FPConvert)), ne);
  81. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  82. }
  83. }
  84. else if (op.Size == 1 && op.Opc == 3) // Double -> Half.
  85. {
  86. throw new NotImplementedException("Double-precision to half-precision.");
  87. }
  88. else if (op.Size == 3 && op.Opc == 1) // Double -> Half.
  89. {
  90. throw new NotImplementedException("Half-precision to double-precision.");
  91. }
  92. else // Invalid encoding.
  93. {
  94. Debug.Assert(false, $"type == {op.Size} && opc == {op.Opc}");
  95. }
  96. }
  97. public static void Fcvtas_Gp(ArmEmitterContext context)
  98. {
  99. EmitFcvt_s_Gp(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1));
  100. }
  101. public static void Fcvtas_S(ArmEmitterContext context)
  102. {
  103. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1), signed: true, scalar: true);
  104. }
  105. public static void Fcvtas_V(ArmEmitterContext context)
  106. {
  107. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1), signed: true, scalar: false);
  108. }
  109. public static void Fcvtau_Gp(ArmEmitterContext context)
  110. {
  111. EmitFcvt_u_Gp(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1));
  112. }
  113. public static void Fcvtau_S(ArmEmitterContext context)
  114. {
  115. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1), signed: false, scalar: true);
  116. }
  117. public static void Fcvtau_V(ArmEmitterContext context)
  118. {
  119. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1), signed: false, scalar: false);
  120. }
  121. public static void Fcvtl_V(ArmEmitterContext context)
  122. {
  123. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  124. int sizeF = op.Size & 1;
  125. if (Optimizations.UseSse2 && sizeF == 1)
  126. {
  127. Operand n = GetVec(op.Rn);
  128. Operand res = op.RegisterSize == RegisterSize.Simd128 ? context.AddIntrinsic(Intrinsic.X86Movhlps, n, n) : n;
  129. res = context.AddIntrinsic(Intrinsic.X86Cvtps2pd, res);
  130. context.Copy(GetVec(op.Rd), res);
  131. }
  132. else if (Optimizations.UseF16c && sizeF == 0)
  133. {
  134. Debug.Assert(!Optimizations.ForceLegacySse);
  135. Operand n = GetVec(op.Rn);
  136. Operand res = op.RegisterSize == RegisterSize.Simd128 ? context.AddIntrinsic(Intrinsic.X86Movhlps, n, n) : n;
  137. res = context.AddIntrinsic(Intrinsic.X86Vcvtph2ps, res);
  138. context.Copy(GetVec(op.Rd), res);
  139. }
  140. else
  141. {
  142. Operand res = context.VectorZero();
  143. int elems = 4 >> sizeF;
  144. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  145. for (int index = 0; index < elems; index++)
  146. {
  147. if (sizeF == 0)
  148. {
  149. Operand ne = EmitVectorExtractZx(context, op.Rn, part + index, 1);
  150. Operand e = context.Call(typeof(SoftFloat16_32).GetMethod(nameof(SoftFloat16_32.FPConvert)), ne);
  151. res = context.VectorInsert(res, e, index);
  152. }
  153. else /* if (sizeF == 1) */
  154. {
  155. Operand ne = context.VectorExtract(OperandType.FP32, GetVec(op.Rn), part + index);
  156. Operand e = context.ConvertToFP(OperandType.FP64, ne);
  157. res = context.VectorInsert(res, e, index);
  158. }
  159. }
  160. context.Copy(GetVec(op.Rd), res);
  161. }
  162. }
  163. public static void Fcvtms_Gp(ArmEmitterContext context)
  164. {
  165. if (Optimizations.UseSse41)
  166. {
  167. EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsMinusInfinity, isFixed: false);
  168. }
  169. else
  170. {
  171. EmitFcvt_s_Gp(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Floor), op1));
  172. }
  173. }
  174. public static void Fcvtmu_Gp(ArmEmitterContext context)
  175. {
  176. if (Optimizations.UseSse41)
  177. {
  178. EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsMinusInfinity, isFixed: false);
  179. }
  180. else
  181. {
  182. EmitFcvt_u_Gp(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Floor), op1));
  183. }
  184. }
  185. public static void Fcvtn_V(ArmEmitterContext context)
  186. {
  187. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  188. int sizeF = op.Size & 1;
  189. if (Optimizations.UseSse2 && sizeF == 1)
  190. {
  191. Operand d = GetVec(op.Rd);
  192. Intrinsic movInst = op.RegisterSize == RegisterSize.Simd128 ? Intrinsic.X86Movlhps : Intrinsic.X86Movhlps;
  193. Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtpd2ps, GetVec(op.Rn));
  194. nInt = context.AddIntrinsic(Intrinsic.X86Movlhps, nInt, nInt);
  195. Operand res = context.VectorZeroUpper64(d);
  196. res = context.AddIntrinsic(movInst, res, nInt);
  197. context.Copy(d, res);
  198. }
  199. else if (Optimizations.UseF16c && sizeF == 0)
  200. {
  201. Debug.Assert(!Optimizations.ForceLegacySse);
  202. Operand d = GetVec(op.Rd);
  203. Operand n = GetVec(op.Rn);
  204. Intrinsic movInst = op.RegisterSize == RegisterSize.Simd128 ? Intrinsic.X86Movlhps : Intrinsic.X86Movhlps;
  205. Operand nInt = context.AddIntrinsic(Intrinsic.X86Vcvtps2ph, n, Const(X86GetRoundControl(FPRoundingMode.ToNearest)));
  206. nInt = context.AddIntrinsic(Intrinsic.X86Movlhps, nInt, nInt);
  207. Operand res = context.VectorZeroUpper64(d);
  208. res = context.AddIntrinsic(movInst, res, nInt);
  209. context.Copy(d, res);
  210. }
  211. else
  212. {
  213. OperandType type = sizeF == 0 ? OperandType.FP32 : OperandType.FP64;
  214. int elems = 4 >> sizeF;
  215. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  216. Operand d = GetVec(op.Rd);
  217. Operand res = part == 0 ? context.VectorZero() : context.Copy(d);
  218. for (int index = 0; index < elems; index++)
  219. {
  220. Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
  221. if (sizeF == 0)
  222. {
  223. Operand e = context.Call(typeof(SoftFloat32_16).GetMethod(nameof(SoftFloat32_16.FPConvert)), ne);
  224. e = context.ZeroExtend16(OperandType.I64, e);
  225. res = EmitVectorInsert(context, res, e, part + index, 1);
  226. }
  227. else /* if (sizeF == 1) */
  228. {
  229. Operand e = context.ConvertToFP(OperandType.FP32, ne);
  230. res = context.VectorInsert(res, e, part + index);
  231. }
  232. }
  233. context.Copy(d, res);
  234. }
  235. }
  236. public static void Fcvtns_S(ArmEmitterContext context)
  237. {
  238. if (Optimizations.UseSse41)
  239. {
  240. EmitSse41FcvtsOpF(context, FPRoundingMode.ToNearest, scalar: true);
  241. }
  242. else
  243. {
  244. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1), signed: true, scalar: true);
  245. }
  246. }
  247. public static void Fcvtns_V(ArmEmitterContext context)
  248. {
  249. if (Optimizations.UseSse41)
  250. {
  251. EmitSse41FcvtsOpF(context, FPRoundingMode.ToNearest, scalar: false);
  252. }
  253. else
  254. {
  255. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1), signed: true, scalar: false);
  256. }
  257. }
  258. public static void Fcvtnu_S(ArmEmitterContext context)
  259. {
  260. if (Optimizations.UseSse41)
  261. {
  262. EmitSse41FcvtuOpF(context, FPRoundingMode.ToNearest, scalar: true);
  263. }
  264. else
  265. {
  266. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1), signed: false, scalar: true);
  267. }
  268. }
  269. public static void Fcvtnu_V(ArmEmitterContext context)
  270. {
  271. if (Optimizations.UseSse41)
  272. {
  273. EmitSse41FcvtuOpF(context, FPRoundingMode.ToNearest, scalar: false);
  274. }
  275. else
  276. {
  277. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1), signed: false, scalar: false);
  278. }
  279. }
  280. public static void Fcvtps_Gp(ArmEmitterContext context)
  281. {
  282. if (Optimizations.UseSse41)
  283. {
  284. EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsPlusInfinity, isFixed: false);
  285. }
  286. else
  287. {
  288. EmitFcvt_s_Gp(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Ceiling), op1));
  289. }
  290. }
  291. public static void Fcvtpu_Gp(ArmEmitterContext context)
  292. {
  293. if (Optimizations.UseSse41)
  294. {
  295. EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsPlusInfinity, isFixed: false);
  296. }
  297. else
  298. {
  299. EmitFcvt_u_Gp(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Ceiling), op1));
  300. }
  301. }
  302. public static void Fcvtzs_Gp(ArmEmitterContext context)
  303. {
  304. if (Optimizations.UseSse41)
  305. {
  306. EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsZero, isFixed: false);
  307. }
  308. else
  309. {
  310. EmitFcvt_s_Gp(context, (op1) => op1);
  311. }
  312. }
  313. public static void Fcvtzs_Gp_Fixed(ArmEmitterContext context)
  314. {
  315. if (Optimizations.UseSse41)
  316. {
  317. EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsZero, isFixed: true);
  318. }
  319. else
  320. {
  321. EmitFcvtzs_Gp_Fixed(context);
  322. }
  323. }
  324. public static void Fcvtzs_S(ArmEmitterContext context)
  325. {
  326. if (Optimizations.UseSse41)
  327. {
  328. EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsZero, scalar: true);
  329. }
  330. else
  331. {
  332. EmitFcvtz(context, signed: true, scalar: true);
  333. }
  334. }
  335. public static void Fcvtzs_V(ArmEmitterContext context)
  336. {
  337. if (Optimizations.UseSse41)
  338. {
  339. EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsZero, scalar: false);
  340. }
  341. else
  342. {
  343. EmitFcvtz(context, signed: true, scalar: false);
  344. }
  345. }
  346. public static void Fcvtzs_V_Fixed(ArmEmitterContext context)
  347. {
  348. if (Optimizations.UseSse41)
  349. {
  350. EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsZero, scalar: false);
  351. }
  352. else
  353. {
  354. EmitFcvtz(context, signed: true, scalar: false);
  355. }
  356. }
  357. public static void Fcvtzu_Gp(ArmEmitterContext context)
  358. {
  359. if (Optimizations.UseSse41)
  360. {
  361. EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsZero, isFixed: false);
  362. }
  363. else
  364. {
  365. EmitFcvt_u_Gp(context, (op1) => op1);
  366. }
  367. }
  368. public static void Fcvtzu_Gp_Fixed(ArmEmitterContext context)
  369. {
  370. if (Optimizations.UseSse41)
  371. {
  372. EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsZero, isFixed: true);
  373. }
  374. else
  375. {
  376. EmitFcvtzu_Gp_Fixed(context);
  377. }
  378. }
  379. public static void Fcvtzu_S(ArmEmitterContext context)
  380. {
  381. if (Optimizations.UseSse41)
  382. {
  383. EmitSse41FcvtuOpF(context, FPRoundingMode.TowardsZero, scalar: true);
  384. }
  385. else
  386. {
  387. EmitFcvtz(context, signed: false, scalar: true);
  388. }
  389. }
  390. public static void Fcvtzu_V(ArmEmitterContext context)
  391. {
  392. if (Optimizations.UseSse41)
  393. {
  394. EmitSse41FcvtuOpF(context, FPRoundingMode.TowardsZero, scalar: false);
  395. }
  396. else
  397. {
  398. EmitFcvtz(context, signed: false, scalar: false);
  399. }
  400. }
  401. public static void Fcvtzu_V_Fixed(ArmEmitterContext context)
  402. {
  403. if (Optimizations.UseSse41)
  404. {
  405. EmitSse41FcvtuOpF(context, FPRoundingMode.TowardsZero, scalar: false);
  406. }
  407. else
  408. {
  409. EmitFcvtz(context, signed: false, scalar: false);
  410. }
  411. }
  412. public static void Scvtf_Gp(ArmEmitterContext context)
  413. {
  414. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  415. Operand res = GetIntOrZR(context, op.Rn);
  416. if (op.RegisterSize == RegisterSize.Int32)
  417. {
  418. res = context.SignExtend32(OperandType.I64, res);
  419. }
  420. res = EmitFPConvert(context, res, op.Size, signed: true);
  421. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  422. }
  423. public static void Scvtf_Gp_Fixed(ArmEmitterContext context)
  424. {
  425. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  426. Operand res = GetIntOrZR(context, op.Rn);
  427. if (op.RegisterSize == RegisterSize.Int32)
  428. {
  429. res = context.SignExtend32(OperandType.I64, res);
  430. }
  431. res = EmitFPConvert(context, res, op.Size, signed: true);
  432. res = EmitI2fFBitsMul(context, res, op.FBits);
  433. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  434. }
  435. public static void Scvtf_S(ArmEmitterContext context)
  436. {
  437. if (Optimizations.UseSse2)
  438. {
  439. EmitSse2ScvtfOp(context, scalar: true);
  440. }
  441. else
  442. {
  443. EmitCvtf(context, signed: true, scalar: true);
  444. }
  445. }
  446. public static void Scvtf_S_Fixed(ArmEmitterContext context)
  447. {
  448. if (Optimizations.UseSse2)
  449. {
  450. EmitSse2ScvtfOp(context, scalar: true);
  451. }
  452. else
  453. {
  454. EmitCvtf(context, signed: true, scalar: true);
  455. }
  456. }
  457. public static void Scvtf_V(ArmEmitterContext context)
  458. {
  459. if (Optimizations.UseSse2)
  460. {
  461. EmitSse2ScvtfOp(context, scalar: false);
  462. }
  463. else
  464. {
  465. EmitCvtf(context, signed: true, scalar: false);
  466. }
  467. }
  468. public static void Scvtf_V_Fixed(ArmEmitterContext context)
  469. {
  470. if (Optimizations.UseSse2)
  471. {
  472. EmitSse2ScvtfOp(context, scalar: false);
  473. }
  474. else
  475. {
  476. EmitCvtf(context, signed: true, scalar: false);
  477. }
  478. }
  479. public static void Ucvtf_Gp(ArmEmitterContext context)
  480. {
  481. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  482. Operand res = GetIntOrZR(context, op.Rn);
  483. res = EmitFPConvert(context, res, op.Size, signed: false);
  484. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  485. }
  486. public static void Ucvtf_Gp_Fixed(ArmEmitterContext context)
  487. {
  488. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  489. Operand res = GetIntOrZR(context, op.Rn);
  490. res = EmitFPConvert(context, res, op.Size, signed: false);
  491. res = EmitI2fFBitsMul(context, res, op.FBits);
  492. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  493. }
  494. public static void Ucvtf_S(ArmEmitterContext context)
  495. {
  496. if (Optimizations.UseSse2)
  497. {
  498. EmitSse2UcvtfOp(context, scalar: true);
  499. }
  500. else
  501. {
  502. EmitCvtf(context, signed: false, scalar: true);
  503. }
  504. }
  505. public static void Ucvtf_S_Fixed(ArmEmitterContext context)
  506. {
  507. if (Optimizations.UseSse2)
  508. {
  509. EmitSse2UcvtfOp(context, scalar: true);
  510. }
  511. else
  512. {
  513. EmitCvtf(context, signed: false, scalar: true);
  514. }
  515. }
  516. public static void Ucvtf_V(ArmEmitterContext context)
  517. {
  518. if (Optimizations.UseSse2)
  519. {
  520. EmitSse2UcvtfOp(context, scalar: false);
  521. }
  522. else
  523. {
  524. EmitCvtf(context, signed: false, scalar: false);
  525. }
  526. }
  527. public static void Ucvtf_V_Fixed(ArmEmitterContext context)
  528. {
  529. if (Optimizations.UseSse2)
  530. {
  531. EmitSse2UcvtfOp(context, scalar: false);
  532. }
  533. else
  534. {
  535. EmitCvtf(context, signed: false, scalar: false);
  536. }
  537. }
  538. private static void EmitFcvt(ArmEmitterContext context, Func1I emit, bool signed, bool scalar)
  539. {
  540. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  541. Operand res = context.VectorZero();
  542. Operand n = GetVec(op.Rn);
  543. int sizeF = op.Size & 1;
  544. int sizeI = sizeF + 2;
  545. OperandType type = sizeF == 0 ? OperandType.FP32 : OperandType.FP64;
  546. int elems = !scalar ? op.GetBytesCount() >> sizeI : 1;
  547. for (int index = 0; index < elems; index++)
  548. {
  549. Operand ne = context.VectorExtract(type, n, index);
  550. Operand e = emit(ne);
  551. if (sizeF == 0)
  552. {
  553. MethodInfo info = signed
  554. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS32))
  555. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU32));
  556. e = context.Call(info, e);
  557. e = context.ZeroExtend32(OperandType.I64, e);
  558. }
  559. else /* if (sizeF == 1) */
  560. {
  561. MethodInfo info = signed
  562. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS64))
  563. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU64));
  564. e = context.Call(info, e);
  565. }
  566. res = EmitVectorInsert(context, res, e, index, sizeI);
  567. }
  568. context.Copy(GetVec(op.Rd), res);
  569. }
  570. private static void EmitFcvtz(ArmEmitterContext context, bool signed, bool scalar)
  571. {
  572. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  573. Operand res = context.VectorZero();
  574. Operand n = GetVec(op.Rn);
  575. int sizeF = op.Size & 1;
  576. int sizeI = sizeF + 2;
  577. OperandType type = sizeF == 0 ? OperandType.FP32 : OperandType.FP64;
  578. int fBits = GetFBits(context);
  579. int elems = !scalar ? op.GetBytesCount() >> sizeI : 1;
  580. for (int index = 0; index < elems; index++)
  581. {
  582. Operand ne = context.VectorExtract(type, n, index);
  583. Operand e = EmitF2iFBitsMul(context, ne, fBits);
  584. if (sizeF == 0)
  585. {
  586. MethodInfo info = signed
  587. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS32))
  588. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU32));
  589. e = context.Call(info, e);
  590. e = context.ZeroExtend32(OperandType.I64, e);
  591. }
  592. else /* if (sizeF == 1) */
  593. {
  594. MethodInfo info = signed
  595. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS64))
  596. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU64));
  597. e = context.Call(info, e);
  598. }
  599. res = EmitVectorInsert(context, res, e, index, sizeI);
  600. }
  601. context.Copy(GetVec(op.Rd), res);
  602. }
  603. private static void EmitFcvt_s_Gp(ArmEmitterContext context, Func1I emit)
  604. {
  605. EmitFcvt___Gp(context, emit, signed: true);
  606. }
  607. private static void EmitFcvt_u_Gp(ArmEmitterContext context, Func1I emit)
  608. {
  609. EmitFcvt___Gp(context, emit, signed: false);
  610. }
  611. private static void EmitFcvt___Gp(ArmEmitterContext context, Func1I emit, bool signed)
  612. {
  613. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  614. OperandType type = op.Size == 0 ? OperandType.FP32 : OperandType.FP64;
  615. Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
  616. Operand res = signed
  617. ? EmitScalarFcvts(context, emit(ne), 0)
  618. : EmitScalarFcvtu(context, emit(ne), 0);
  619. SetIntOrZR(context, op.Rd, res);
  620. }
  621. private static void EmitFcvtzs_Gp_Fixed(ArmEmitterContext context)
  622. {
  623. EmitFcvtz__Gp_Fixed(context, signed: true);
  624. }
  625. private static void EmitFcvtzu_Gp_Fixed(ArmEmitterContext context)
  626. {
  627. EmitFcvtz__Gp_Fixed(context, signed: false);
  628. }
  629. private static void EmitFcvtz__Gp_Fixed(ArmEmitterContext context, bool signed)
  630. {
  631. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  632. OperandType type = op.Size == 0 ? OperandType.FP32 : OperandType.FP64;
  633. Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
  634. Operand res = signed
  635. ? EmitScalarFcvts(context, ne, op.FBits)
  636. : EmitScalarFcvtu(context, ne, op.FBits);
  637. SetIntOrZR(context, op.Rd, res);
  638. }
  639. private static void EmitCvtf(ArmEmitterContext context, bool signed, bool scalar)
  640. {
  641. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  642. Operand res = context.VectorZero();
  643. int sizeF = op.Size & 1;
  644. int sizeI = sizeF + 2;
  645. int fBits = GetFBits(context);
  646. int elems = !scalar ? op.GetBytesCount() >> sizeI : 1;
  647. for (int index = 0; index < elems; index++)
  648. {
  649. Operand ne = EmitVectorLongExtract(context, op.Rn, index, sizeI);
  650. Operand e = EmitFPConvert(context, ne, sizeF, signed);
  651. e = EmitI2fFBitsMul(context, e, fBits);
  652. res = context.VectorInsert(res, e, index);
  653. }
  654. context.Copy(GetVec(op.Rd), res);
  655. }
  656. private static int GetFBits(ArmEmitterContext context)
  657. {
  658. if (context.CurrOp is OpCodeSimdShImm op)
  659. {
  660. return GetImmShr(op);
  661. }
  662. return 0;
  663. }
  664. private static Operand EmitFPConvert(ArmEmitterContext context, Operand value, int size, bool signed)
  665. {
  666. Debug.Assert(value.Type == OperandType.I32 || value.Type == OperandType.I64);
  667. Debug.Assert((uint)size < 2);
  668. OperandType type = size == 0 ? OperandType.FP32 : OperandType.FP64;
  669. if (signed)
  670. {
  671. return context.ConvertToFP(type, value);
  672. }
  673. else
  674. {
  675. return context.ConvertToFPUI(type, value);
  676. }
  677. }
  678. private static Operand EmitScalarFcvts(ArmEmitterContext context, Operand value, int fBits)
  679. {
  680. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  681. value = EmitF2iFBitsMul(context, value, fBits);
  682. MethodInfo info;
  683. if (context.CurrOp.RegisterSize == RegisterSize.Int32)
  684. {
  685. info = value.Type == OperandType.FP32
  686. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS32))
  687. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS32));
  688. }
  689. else
  690. {
  691. info = value.Type == OperandType.FP32
  692. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS64))
  693. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS64));
  694. }
  695. return context.Call(info, value);
  696. }
  697. private static Operand EmitScalarFcvtu(ArmEmitterContext context, Operand value, int fBits)
  698. {
  699. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  700. value = EmitF2iFBitsMul(context, value, fBits);
  701. MethodInfo info;
  702. if (context.CurrOp.RegisterSize == RegisterSize.Int32)
  703. {
  704. info = value.Type == OperandType.FP32
  705. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU32))
  706. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU32));
  707. }
  708. else
  709. {
  710. info = value.Type == OperandType.FP32
  711. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU64))
  712. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU64));
  713. }
  714. return context.Call(info, value);
  715. }
  716. private static Operand EmitF2iFBitsMul(ArmEmitterContext context, Operand value, int fBits)
  717. {
  718. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  719. if (fBits == 0)
  720. {
  721. return value;
  722. }
  723. if (value.Type == OperandType.FP32)
  724. {
  725. return context.Multiply(value, ConstF(MathF.Pow(2f, fBits)));
  726. }
  727. else /* if (value.Type == OperandType.FP64) */
  728. {
  729. return context.Multiply(value, ConstF(Math.Pow(2d, fBits)));
  730. }
  731. }
  732. private static Operand EmitI2fFBitsMul(ArmEmitterContext context, Operand value, int fBits)
  733. {
  734. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  735. if (fBits == 0)
  736. {
  737. return value;
  738. }
  739. if (value.Type == OperandType.FP32)
  740. {
  741. return context.Multiply(value, ConstF(1f / MathF.Pow(2f, fBits)));
  742. }
  743. else /* if (value.Type == OperandType.FP64) */
  744. {
  745. return context.Multiply(value, ConstF(1d / Math.Pow(2d, fBits)));
  746. }
  747. }
  748. public static Operand EmitSse2CvtDoubleToInt64OpF(ArmEmitterContext context, Operand opF, bool scalar)
  749. {
  750. Debug.Assert(opF.Type == OperandType.V128);
  751. Operand longL = context.AddIntrinsicLong (Intrinsic.X86Cvtsd2si, opF); // opFL
  752. Operand res = context.VectorCreateScalar(longL);
  753. if (!scalar)
  754. {
  755. Operand opFH = context.AddIntrinsic (Intrinsic.X86Movhlps, res, opF); // res doesn't matter.
  756. Operand longH = context.AddIntrinsicLong (Intrinsic.X86Cvtsd2si, opFH);
  757. Operand resH = context.VectorCreateScalar(longH);
  758. res = context.AddIntrinsic (Intrinsic.X86Movlhps, res, resH);
  759. }
  760. return res;
  761. }
  762. private static Operand EmitSse2CvtInt64ToDoubleOp(ArmEmitterContext context, Operand op, bool scalar)
  763. {
  764. Debug.Assert(op.Type == OperandType.V128);
  765. Operand longL = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, op); // opL
  766. Operand res = context.AddIntrinsic (Intrinsic.X86Cvtsi2sd, context.VectorZero(), longL);
  767. if (!scalar)
  768. {
  769. Operand opH = context.AddIntrinsic (Intrinsic.X86Movhlps, res, op); // res doesn't matter.
  770. Operand longH = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, opH);
  771. Operand resH = context.AddIntrinsic (Intrinsic.X86Cvtsi2sd, res, longH); // res doesn't matter.
  772. res = context.AddIntrinsic (Intrinsic.X86Movlhps, res, resH);
  773. }
  774. return res;
  775. }
  776. private static void EmitSse2ScvtfOp(ArmEmitterContext context, bool scalar)
  777. {
  778. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  779. Operand n = GetVec(op.Rn);
  780. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  781. int sizeF = op.Size & 1;
  782. if (sizeF == 0)
  783. {
  784. Operand res = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, n);
  785. if (op is OpCodeSimdShImm fixedOp)
  786. {
  787. int fBits = GetImmShr(fixedOp);
  788. // BitConverter.Int32BitsToSingle(fpScaled) == 1f / MathF.Pow(2f, fBits)
  789. int fpScaled = 0x3F800000 - fBits * 0x800000;
  790. Operand fpScaledMask = scalar
  791. ? X86GetScalar (context, fpScaled)
  792. : X86GetAllElements(context, fpScaled);
  793. res = context.AddIntrinsic(Intrinsic.X86Mulps, res, fpScaledMask);
  794. }
  795. if (scalar)
  796. {
  797. res = context.VectorZeroUpper96(res);
  798. }
  799. else if (op.RegisterSize == RegisterSize.Simd64)
  800. {
  801. res = context.VectorZeroUpper64(res);
  802. }
  803. context.Copy(GetVec(op.Rd), res);
  804. }
  805. else /* if (sizeF == 1) */
  806. {
  807. Operand res = EmitSse2CvtInt64ToDoubleOp(context, n, scalar);
  808. if (op is OpCodeSimdShImm fixedOp)
  809. {
  810. int fBits = GetImmShr(fixedOp);
  811. // BitConverter.Int64BitsToDouble(fpScaled) == 1d / Math.Pow(2d, fBits)
  812. long fpScaled = 0x3FF0000000000000L - fBits * 0x10000000000000L;
  813. Operand fpScaledMask = scalar
  814. ? X86GetScalar (context, fpScaled)
  815. : X86GetAllElements(context, fpScaled);
  816. res = context.AddIntrinsic(Intrinsic.X86Mulpd, res, fpScaledMask);
  817. }
  818. if (scalar)
  819. {
  820. res = context.VectorZeroUpper64(res);
  821. }
  822. context.Copy(GetVec(op.Rd), res);
  823. }
  824. }
  825. private static void EmitSse2UcvtfOp(ArmEmitterContext context, bool scalar)
  826. {
  827. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  828. Operand n = GetVec(op.Rn);
  829. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  830. int sizeF = op.Size & 1;
  831. if (sizeF == 0)
  832. {
  833. Operand mask = scalar // 65536.000f (1 << 16)
  834. ? X86GetScalar (context, 0x47800000)
  835. : X86GetAllElements(context, 0x47800000);
  836. Operand res = context.AddIntrinsic(Intrinsic.X86Psrld, n, Const(16));
  837. res = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res);
  838. res = context.AddIntrinsic(Intrinsic.X86Mulps, res, mask);
  839. Operand res2 = context.AddIntrinsic(Intrinsic.X86Pslld, n, Const(16));
  840. res2 = context.AddIntrinsic(Intrinsic.X86Psrld, res2, Const(16));
  841. res2 = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res2);
  842. res = context.AddIntrinsic(Intrinsic.X86Addps, res, res2);
  843. if (op is OpCodeSimdShImm fixedOp)
  844. {
  845. int fBits = GetImmShr(fixedOp);
  846. // BitConverter.Int32BitsToSingle(fpScaled) == 1f / MathF.Pow(2f, fBits)
  847. int fpScaled = 0x3F800000 - fBits * 0x800000;
  848. Operand fpScaledMask = scalar
  849. ? X86GetScalar (context, fpScaled)
  850. : X86GetAllElements(context, fpScaled);
  851. res = context.AddIntrinsic(Intrinsic.X86Mulps, res, fpScaledMask);
  852. }
  853. if (scalar)
  854. {
  855. res = context.VectorZeroUpper96(res);
  856. }
  857. else if (op.RegisterSize == RegisterSize.Simd64)
  858. {
  859. res = context.VectorZeroUpper64(res);
  860. }
  861. context.Copy(GetVec(op.Rd), res);
  862. }
  863. else /* if (sizeF == 1) */
  864. {
  865. Operand mask = scalar // 4294967296.0000000d (1L << 32)
  866. ? X86GetScalar (context, 0x41F0000000000000L)
  867. : X86GetAllElements(context, 0x41F0000000000000L);
  868. Operand res = context.AddIntrinsic (Intrinsic.X86Psrlq, n, Const(32));
  869. res = EmitSse2CvtInt64ToDoubleOp(context, res, scalar);
  870. res = context.AddIntrinsic (Intrinsic.X86Mulpd, res, mask);
  871. Operand res2 = context.AddIntrinsic (Intrinsic.X86Psllq, n, Const(32));
  872. res2 = context.AddIntrinsic (Intrinsic.X86Psrlq, res2, Const(32));
  873. res2 = EmitSse2CvtInt64ToDoubleOp(context, res2, scalar);
  874. res = context.AddIntrinsic(Intrinsic.X86Addpd, res, res2);
  875. if (op is OpCodeSimdShImm fixedOp)
  876. {
  877. int fBits = GetImmShr(fixedOp);
  878. // BitConverter.Int64BitsToDouble(fpScaled) == 1d / Math.Pow(2d, fBits)
  879. long fpScaled = 0x3FF0000000000000L - fBits * 0x10000000000000L;
  880. Operand fpScaledMask = scalar
  881. ? X86GetScalar (context, fpScaled)
  882. : X86GetAllElements(context, fpScaled);
  883. res = context.AddIntrinsic(Intrinsic.X86Mulpd, res, fpScaledMask);
  884. }
  885. if (scalar)
  886. {
  887. res = context.VectorZeroUpper64(res);
  888. }
  889. context.Copy(GetVec(op.Rd), res);
  890. }
  891. }
  892. private static void EmitSse41FcvtsOpF(ArmEmitterContext context, FPRoundingMode roundMode, bool scalar)
  893. {
  894. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  895. Operand n = GetVec(op.Rn);
  896. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  897. int sizeF = op.Size & 1;
  898. if (sizeF == 0)
  899. {
  900. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, n, n, Const((int)CmpCondition.OrderedQ));
  901. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  902. if (op is OpCodeSimdShImm fixedOp)
  903. {
  904. int fBits = GetImmShr(fixedOp);
  905. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, fBits)
  906. int fpScaled = 0x3F800000 + fBits * 0x800000;
  907. Operand fpScaledMask = scalar
  908. ? X86GetScalar (context, fpScaled)
  909. : X86GetAllElements(context, fpScaled);
  910. nRes = context.AddIntrinsic(Intrinsic.X86Mulps, nRes, fpScaledMask);
  911. }
  912. nRes = context.AddIntrinsic(Intrinsic.X86Roundps, nRes, Const(X86GetRoundControl(roundMode)));
  913. Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes);
  914. Operand fpMaxValMask = scalar // 2.14748365E9f (2147483648)
  915. ? X86GetScalar (context, 0x4F000000)
  916. : X86GetAllElements(context, 0x4F000000);
  917. nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  918. Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nInt, nRes);
  919. if (scalar)
  920. {
  921. dRes = context.VectorZeroUpper96(dRes);
  922. }
  923. else if (op.RegisterSize == RegisterSize.Simd64)
  924. {
  925. dRes = context.VectorZeroUpper64(dRes);
  926. }
  927. context.Copy(GetVec(op.Rd), dRes);
  928. }
  929. else /* if (sizeF == 1) */
  930. {
  931. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, n, n, Const((int)CmpCondition.OrderedQ));
  932. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  933. if (op is OpCodeSimdShImm fixedOp)
  934. {
  935. int fBits = GetImmShr(fixedOp);
  936. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, fBits)
  937. long fpScaled = 0x3FF0000000000000L + fBits * 0x10000000000000L;
  938. Operand fpScaledMask = scalar
  939. ? X86GetScalar (context, fpScaled)
  940. : X86GetAllElements(context, fpScaled);
  941. nRes = context.AddIntrinsic(Intrinsic.X86Mulpd, nRes, fpScaledMask);
  942. }
  943. nRes = context.AddIntrinsic(Intrinsic.X86Roundpd, nRes, Const(X86GetRoundControl(roundMode)));
  944. Operand nLong = EmitSse2CvtDoubleToInt64OpF(context, nRes, scalar);
  945. Operand fpMaxValMask = scalar // 9.2233720368547760E18d (9223372036854775808)
  946. ? X86GetScalar (context, 0x43E0000000000000L)
  947. : X86GetAllElements(context, 0x43E0000000000000L);
  948. nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  949. Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nLong, nRes);
  950. if (scalar)
  951. {
  952. dRes = context.VectorZeroUpper64(dRes);
  953. }
  954. context.Copy(GetVec(op.Rd), dRes);
  955. }
  956. }
  957. private static void EmitSse41FcvtuOpF(ArmEmitterContext context, FPRoundingMode roundMode, bool scalar)
  958. {
  959. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  960. Operand n = GetVec(op.Rn);
  961. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  962. int sizeF = op.Size & 1;
  963. if (sizeF == 0)
  964. {
  965. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, n, n, Const((int)CmpCondition.OrderedQ));
  966. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  967. if (op is OpCodeSimdShImm fixedOp)
  968. {
  969. int fBits = GetImmShr(fixedOp);
  970. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, fBits)
  971. int fpScaled = 0x3F800000 + fBits * 0x800000;
  972. Operand fpScaledMask = scalar
  973. ? X86GetScalar (context, fpScaled)
  974. : X86GetAllElements(context, fpScaled);
  975. nRes = context.AddIntrinsic(Intrinsic.X86Mulps, nRes, fpScaledMask);
  976. }
  977. nRes = context.AddIntrinsic(Intrinsic.X86Roundps, nRes, Const(X86GetRoundControl(roundMode)));
  978. Operand zero = context.VectorZero();
  979. Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  980. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  981. Operand fpMaxValMask = scalar // 2.14748365E9f (2147483648)
  982. ? X86GetScalar (context, 0x4F000000)
  983. : X86GetAllElements(context, 0x4F000000);
  984. Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes);
  985. nRes = context.AddIntrinsic(Intrinsic.X86Subps, nRes, fpMaxValMask);
  986. nCmp = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  987. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  988. Operand nInt2 = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes);
  989. nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  990. Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nInt2, nRes);
  991. dRes = context.AddIntrinsic(Intrinsic.X86Paddd, dRes, nInt);
  992. if (scalar)
  993. {
  994. dRes = context.VectorZeroUpper96(dRes);
  995. }
  996. else if (op.RegisterSize == RegisterSize.Simd64)
  997. {
  998. dRes = context.VectorZeroUpper64(dRes);
  999. }
  1000. context.Copy(GetVec(op.Rd), dRes);
  1001. }
  1002. else /* if (sizeF == 1) */
  1003. {
  1004. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, n, n, Const((int)CmpCondition.OrderedQ));
  1005. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1006. if (op is OpCodeSimdShImm fixedOp)
  1007. {
  1008. int fBits = GetImmShr(fixedOp);
  1009. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, fBits)
  1010. long fpScaled = 0x3FF0000000000000L + fBits * 0x10000000000000L;
  1011. Operand fpScaledMask = scalar
  1012. ? X86GetScalar (context, fpScaled)
  1013. : X86GetAllElements(context, fpScaled);
  1014. nRes = context.AddIntrinsic(Intrinsic.X86Mulpd, nRes, fpScaledMask);
  1015. }
  1016. nRes = context.AddIntrinsic(Intrinsic.X86Roundpd, nRes, Const(X86GetRoundControl(roundMode)));
  1017. Operand zero = context.VectorZero();
  1018. Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1019. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1020. Operand fpMaxValMask = scalar // 9.2233720368547760E18d (9223372036854775808)
  1021. ? X86GetScalar (context, 0x43E0000000000000L)
  1022. : X86GetAllElements(context, 0x43E0000000000000L);
  1023. Operand nLong = EmitSse2CvtDoubleToInt64OpF(context, nRes, scalar);
  1024. nRes = context.AddIntrinsic(Intrinsic.X86Subpd, nRes, fpMaxValMask);
  1025. nCmp = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1026. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1027. Operand nLong2 = EmitSse2CvtDoubleToInt64OpF(context, nRes, scalar);
  1028. nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1029. Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nLong2, nRes);
  1030. dRes = context.AddIntrinsic(Intrinsic.X86Paddq, dRes, nLong);
  1031. if (scalar)
  1032. {
  1033. dRes = context.VectorZeroUpper64(dRes);
  1034. }
  1035. context.Copy(GetVec(op.Rd), dRes);
  1036. }
  1037. }
  1038. private static void EmitSse41Fcvts_Gp(ArmEmitterContext context, FPRoundingMode roundMode, bool isFixed)
  1039. {
  1040. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  1041. Operand n = GetVec(op.Rn);
  1042. if (op.Size == 0)
  1043. {
  1044. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, n, n, Const((int)CmpCondition.OrderedQ));
  1045. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1046. if (isFixed)
  1047. {
  1048. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, op.FBits)
  1049. int fpScaled = 0x3F800000 + op.FBits * 0x800000;
  1050. Operand fpScaledMask = X86GetScalar(context, fpScaled);
  1051. nRes = context.AddIntrinsic(Intrinsic.X86Mulss, nRes, fpScaledMask);
  1052. }
  1053. nRes = context.AddIntrinsic(Intrinsic.X86Roundss, nRes, Const(X86GetRoundControl(roundMode)));
  1054. Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
  1055. ? context.AddIntrinsicInt (Intrinsic.X86Cvtss2si, nRes)
  1056. : context.AddIntrinsicLong(Intrinsic.X86Cvtss2si, nRes);
  1057. int fpMaxVal = op.RegisterSize == RegisterSize.Int32
  1058. ? 0x4F000000 // 2.14748365E9f (2147483648)
  1059. : 0x5F000000; // 9.223372E18f (9223372036854775808)
  1060. Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
  1061. nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1062. Operand nInt = context.AddIntrinsicInt(Intrinsic.X86Cvtsi2si, nRes);
  1063. if (op.RegisterSize == RegisterSize.Int64)
  1064. {
  1065. nInt = context.SignExtend32(OperandType.I64, nInt);
  1066. }
  1067. Operand dRes = context.BitwiseExclusiveOr(nIntOrLong, nInt);
  1068. SetIntOrZR(context, op.Rd, dRes);
  1069. }
  1070. else /* if (op.Size == 1) */
  1071. {
  1072. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, n, n, Const((int)CmpCondition.OrderedQ));
  1073. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1074. if (isFixed)
  1075. {
  1076. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, op.FBits)
  1077. long fpScaled = 0x3FF0000000000000L + op.FBits * 0x10000000000000L;
  1078. Operand fpScaledMask = X86GetScalar(context, fpScaled);
  1079. nRes = context.AddIntrinsic(Intrinsic.X86Mulsd, nRes, fpScaledMask);
  1080. }
  1081. nRes = context.AddIntrinsic(Intrinsic.X86Roundsd, nRes, Const(X86GetRoundControl(roundMode)));
  1082. Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
  1083. ? context.AddIntrinsicInt (Intrinsic.X86Cvtsd2si, nRes)
  1084. : context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRes);
  1085. long fpMaxVal = op.RegisterSize == RegisterSize.Int32
  1086. ? 0x41E0000000000000L // 2147483648.0000000d (2147483648)
  1087. : 0x43E0000000000000L; // 9.2233720368547760E18d (9223372036854775808)
  1088. Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
  1089. nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1090. Operand nLong = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, nRes);
  1091. if (op.RegisterSize == RegisterSize.Int32)
  1092. {
  1093. nLong = context.ConvertI64ToI32(nLong);
  1094. }
  1095. Operand dRes = context.BitwiseExclusiveOr(nIntOrLong, nLong);
  1096. SetIntOrZR(context, op.Rd, dRes);
  1097. }
  1098. }
  1099. private static void EmitSse41Fcvtu_Gp(ArmEmitterContext context, FPRoundingMode roundMode, bool isFixed)
  1100. {
  1101. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  1102. Operand n = GetVec(op.Rn);
  1103. if (op.Size == 0)
  1104. {
  1105. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, n, n, Const((int)CmpCondition.OrderedQ));
  1106. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1107. if (isFixed)
  1108. {
  1109. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, op.FBits)
  1110. int fpScaled = 0x3F800000 + op.FBits * 0x800000;
  1111. Operand fpScaledMask = X86GetScalar(context, fpScaled);
  1112. nRes = context.AddIntrinsic(Intrinsic.X86Mulss, nRes, fpScaledMask);
  1113. }
  1114. nRes = context.AddIntrinsic(Intrinsic.X86Roundss, nRes, Const(X86GetRoundControl(roundMode)));
  1115. Operand zero = context.VectorZero();
  1116. Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1117. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1118. int fpMaxVal = op.RegisterSize == RegisterSize.Int32
  1119. ? 0x4F000000 // 2.14748365E9f (2147483648)
  1120. : 0x5F000000; // 9.223372E18f (9223372036854775808)
  1121. Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
  1122. Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
  1123. ? context.AddIntrinsicInt (Intrinsic.X86Cvtss2si, nRes)
  1124. : context.AddIntrinsicLong(Intrinsic.X86Cvtss2si, nRes);
  1125. nRes = context.AddIntrinsic(Intrinsic.X86Subss, nRes, fpMaxValMask);
  1126. nCmp = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1127. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1128. Operand nIntOrLong2 = op.RegisterSize == RegisterSize.Int32
  1129. ? context.AddIntrinsicInt (Intrinsic.X86Cvtss2si, nRes)
  1130. : context.AddIntrinsicLong(Intrinsic.X86Cvtss2si, nRes);
  1131. nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1132. Operand nInt = context.AddIntrinsicInt(Intrinsic.X86Cvtsi2si, nRes);
  1133. if (op.RegisterSize == RegisterSize.Int64)
  1134. {
  1135. nInt = context.SignExtend32(OperandType.I64, nInt);
  1136. }
  1137. Operand dRes = context.BitwiseExclusiveOr(nIntOrLong2, nInt);
  1138. dRes = context.Add(dRes, nIntOrLong);
  1139. SetIntOrZR(context, op.Rd, dRes);
  1140. }
  1141. else /* if (op.Size == 1) */
  1142. {
  1143. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, n, n, Const((int)CmpCondition.OrderedQ));
  1144. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1145. if (isFixed)
  1146. {
  1147. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, op.FBits)
  1148. long fpScaled = 0x3FF0000000000000L + op.FBits * 0x10000000000000L;
  1149. Operand fpScaledMask = X86GetScalar(context, fpScaled);
  1150. nRes = context.AddIntrinsic(Intrinsic.X86Mulsd, nRes, fpScaledMask);
  1151. }
  1152. nRes = context.AddIntrinsic(Intrinsic.X86Roundsd, nRes, Const(X86GetRoundControl(roundMode)));
  1153. Operand zero = context.VectorZero();
  1154. Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1155. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1156. long fpMaxVal = op.RegisterSize == RegisterSize.Int32
  1157. ? 0x41E0000000000000L // 2147483648.0000000d (2147483648)
  1158. : 0x43E0000000000000L; // 9.2233720368547760E18d (9223372036854775808)
  1159. Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
  1160. Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
  1161. ? context.AddIntrinsicInt (Intrinsic.X86Cvtsd2si, nRes)
  1162. : context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRes);
  1163. nRes = context.AddIntrinsic(Intrinsic.X86Subsd, nRes, fpMaxValMask);
  1164. nCmp = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1165. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1166. Operand nIntOrLong2 = op.RegisterSize == RegisterSize.Int32
  1167. ? context.AddIntrinsicInt (Intrinsic.X86Cvtsd2si, nRes)
  1168. : context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRes);
  1169. nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1170. Operand nLong = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, nRes);
  1171. if (op.RegisterSize == RegisterSize.Int32)
  1172. {
  1173. nLong = context.ConvertI64ToI32(nLong);
  1174. }
  1175. Operand dRes = context.BitwiseExclusiveOr(nIntOrLong2, nLong);
  1176. dRes = context.Add(dRes, nIntOrLong);
  1177. SetIntOrZR(context, op.Rd, dRes);
  1178. }
  1179. }
  1180. private static Operand EmitVectorLongExtract(ArmEmitterContext context, int reg, int index, int size)
  1181. {
  1182. OperandType type = size == 3 ? OperandType.I64 : OperandType.I32;
  1183. return context.VectorExtract(type, GetVec(reg), index);
  1184. }
  1185. }
  1186. }