Arm32Register.cs 1.8 KB

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  1. namespace Ryujinx.Tests.Unicorn.Native
  2. {
  3. public enum Arm32Register
  4. {
  5. INVALID = 0,
  6. APSR,
  7. APSR_NZCV,
  8. CPSR,
  9. FPEXC,
  10. FPINST,
  11. FPSCR,
  12. FPSCR_NZCV,
  13. FPSID,
  14. ITSTATE,
  15. LR,
  16. PC,
  17. SP,
  18. SPSR,
  19. D0,
  20. D1,
  21. D2,
  22. D3,
  23. D4,
  24. D5,
  25. D6,
  26. D7,
  27. D8,
  28. D9,
  29. D10,
  30. D11,
  31. D12,
  32. D13,
  33. D14,
  34. D15,
  35. D16,
  36. D17,
  37. D18,
  38. D19,
  39. D20,
  40. D21,
  41. D22,
  42. D23,
  43. D24,
  44. D25,
  45. D26,
  46. D27,
  47. D28,
  48. D29,
  49. D30,
  50. D31,
  51. FPINST2,
  52. MVFR0,
  53. MVFR1,
  54. MVFR2,
  55. Q0,
  56. Q1,
  57. Q2,
  58. Q3,
  59. Q4,
  60. Q5,
  61. Q6,
  62. Q7,
  63. Q8,
  64. Q9,
  65. Q10,
  66. Q11,
  67. Q12,
  68. Q13,
  69. Q14,
  70. Q15,
  71. R0,
  72. R1,
  73. R2,
  74. R3,
  75. R4,
  76. R5,
  77. R6,
  78. R7,
  79. R8,
  80. R9,
  81. R10,
  82. R11,
  83. R12,
  84. S0,
  85. S1,
  86. S2,
  87. S3,
  88. S4,
  89. S5,
  90. S6,
  91. S7,
  92. S8,
  93. S9,
  94. S10,
  95. S11,
  96. S12,
  97. S13,
  98. S14,
  99. S15,
  100. S16,
  101. S17,
  102. S18,
  103. S19,
  104. S20,
  105. S21,
  106. S22,
  107. S23,
  108. S24,
  109. S25,
  110. S26,
  111. S27,
  112. S28,
  113. S29,
  114. S30,
  115. S31,
  116. C1_C0_2,
  117. C13_C0_2,
  118. C13_C0_3,
  119. IPSR,
  120. MSP,
  121. PSP,
  122. CONTROL,
  123. ENDING,
  124. // Alias registers.
  125. R13 = SP,
  126. R14 = LR,
  127. R15 = PC,
  128. SB = R9,
  129. SL = R10,
  130. FP = R11,
  131. IP = R12,
  132. }
  133. }