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Aarch32Mode.cs
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a731ab3a2a
Add a new JIT compiler for CPU code (#693)
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6 lat temu |
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ExecutionContext.cs
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cf6cd71488
IPC refactor part 2: Use ReplyAndReceive on HLE services and remove special handling from kernel (#1458)
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5 lat temu |
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ExecutionMode.cs
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dc0adb533d
PPTC & Pool Enhancements. (#1968)
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5 lat temu |
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FPCR.cs
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e36e97c64d
CPU: This PR fixes Fpscr, among other things. (#1433)
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5 lat temu |
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FPException.cs
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a731ab3a2a
Add a new JIT compiler for CPU code (#693)
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6 lat temu |
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FPRoundingMode.cs
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a731ab3a2a
Add a new JIT compiler for CPU code (#693)
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6 lat temu |
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FPSR.cs
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e36e97c64d
CPU: This PR fixes Fpscr, among other things. (#1433)
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5 lat temu |
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FPState.cs
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e36e97c64d
CPU: This PR fixes Fpscr, among other things. (#1433)
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5 lat temu |
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FPType.cs
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a731ab3a2a
Add a new JIT compiler for CPU code (#693)
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6 lat temu |
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InstExceptionEventArgs.cs
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a731ab3a2a
Add a new JIT compiler for CPU code (#693)
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6 lat temu |
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InstUndefinedEventArgs.cs
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a731ab3a2a
Add a new JIT compiler for CPU code (#693)
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6 lat temu |
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NativeContext.cs
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9878fc2d3c
Implement inline memory load/store exclusive and ordered (#1413)
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5 lat temu |
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PState.cs
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e36e97c64d
CPU: This PR fixes Fpscr, among other things. (#1433)
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5 lat temu |
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RegisterAlias.cs
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b1b6f294f2
Add most of the A32 instruction set to ARMeilleure (#897)
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6 lat temu |
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RegisterConsts.cs
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b1b6f294f2
Add most of the A32 instruction set to ARMeilleure (#897)
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6 lat temu |
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V128.cs
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430ba6da65
CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)
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5 lat temu |
LDj3SNuD
dc0adb533d
PPTC & Pool Enhancements. (#1968)