CpuTestAlu.cs 2.1 KB

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  1. using ChocolArm64.State;
  2. using NUnit.Framework;
  3. namespace Ryujinx.Tests.Cpu
  4. {
  5. [TestFixture]
  6. public partial class CpuTest
  7. {
  8. [Test]
  9. public void Add()
  10. {
  11. // ADD X0, X1, X2
  12. ARegisters Registers = SingleOpcode(0x8B020020, X1: 1, X2: 2);
  13. Assert.AreEqual(3, Registers.X0);
  14. }
  15. [Test]
  16. public void Ands()
  17. {
  18. // ANDS W0, W1, W2
  19. uint Opcode = 0x6A020020;
  20. var tests = new[]
  21. {
  22. new { W1 = 0xFFFFFFFFul, W2 = 0xFFFFFFFFul, Result = 0xFFFFFFFFul, Negative = true, Zero = false },
  23. new { W1 = 0xFFFFFFFFul, W2 = 0x00000000ul, Result = 0x00000000ul, Negative = false, Zero = true },
  24. new { W1 = 0x12345678ul, W2 = 0x7324A993ul, Result = 0x12240010ul, Negative = false, Zero = false },
  25. };
  26. foreach (var test in tests)
  27. {
  28. ARegisters Registers = SingleOpcode(Opcode, X1: test.W1, X2: test.W2);
  29. Assert.AreEqual(test.Result, Registers.X0);
  30. Assert.AreEqual(test.Negative, Registers.Negative);
  31. Assert.AreEqual(test.Zero, Registers.Zero);
  32. }
  33. }
  34. [Test]
  35. public void OrrBitmasks()
  36. {
  37. // ORR W0, WZR, #0x01010101
  38. Assert.AreEqual(0x01010101, SingleOpcode(0x3200C3E0).X0);
  39. // ORR W1, WZR, #0x00F000F0
  40. Assert.AreEqual(0x00F000F0, SingleOpcode(0x320C8FE1).X1);
  41. // ORR W2, WZR, #1
  42. Assert.AreEqual(0x00000001, SingleOpcode(0x320003E2).X2);
  43. }
  44. [Test]
  45. public void RevX0X0()
  46. {
  47. // REV X0, X0
  48. ARegisters Registers = SingleOpcode(0xDAC00C00, X0: 0xAABBCCDDEEFF1100);
  49. Assert.AreEqual(0x0011FFEEDDCCBBAA, Registers.X0);
  50. }
  51. [Test]
  52. public void RevW1W1()
  53. {
  54. // REV W1, W1
  55. ARegisters Registers = SingleOpcode(0x5AC00821, X1: 0x12345678);
  56. Assert.AreEqual(0x78563412, Registers.X1);
  57. }
  58. }
  59. }