InstEmitSimdHelper.cs 57 KB

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  1. using ARMeilleure.Decoders;
  2. using ARMeilleure.IntermediateRepresentation;
  3. using ARMeilleure.State;
  4. using ARMeilleure.Translation;
  5. using System;
  6. using System.Diagnostics;
  7. using System.Reflection;
  8. using static ARMeilleure.Instructions.InstEmitHelper;
  9. using static ARMeilleure.IntermediateRepresentation.OperandHelper;
  10. namespace ARMeilleure.Instructions
  11. {
  12. using Func1I = Func<Operand, Operand>;
  13. using Func2I = Func<Operand, Operand, Operand>;
  14. using Func3I = Func<Operand, Operand, Operand, Operand>;
  15. static class InstEmitSimdHelper
  16. {
  17. #region "Masks"
  18. public static readonly long[] EvenMasks = new long[]
  19. {
  20. 14L << 56 | 12L << 48 | 10L << 40 | 08L << 32 | 06L << 24 | 04L << 16 | 02L << 8 | 00L << 0, // B
  21. 13L << 56 | 12L << 48 | 09L << 40 | 08L << 32 | 05L << 24 | 04L << 16 | 01L << 8 | 00L << 0, // H
  22. 11L << 56 | 10L << 48 | 09L << 40 | 08L << 32 | 03L << 24 | 02L << 16 | 01L << 8 | 00L << 0 // S
  23. };
  24. public static readonly long[] OddMasks = new long[]
  25. {
  26. 15L << 56 | 13L << 48 | 11L << 40 | 09L << 32 | 07L << 24 | 05L << 16 | 03L << 8 | 01L << 0, // B
  27. 15L << 56 | 14L << 48 | 11L << 40 | 10L << 32 | 07L << 24 | 06L << 16 | 03L << 8 | 02L << 0, // H
  28. 15L << 56 | 14L << 48 | 13L << 40 | 12L << 32 | 07L << 24 | 06L << 16 | 05L << 8 | 04L << 0 // S
  29. };
  30. public static readonly long ZeroMask = 128L << 56 | 128L << 48 | 128L << 40 | 128L << 32 | 128L << 24 | 128L << 16 | 128L << 8 | 128L << 0;
  31. #endregion
  32. #region "X86 SSE Intrinsics"
  33. public static readonly Intrinsic[] X86PaddInstruction = new Intrinsic[]
  34. {
  35. Intrinsic.X86Paddb,
  36. Intrinsic.X86Paddw,
  37. Intrinsic.X86Paddd,
  38. Intrinsic.X86Paddq
  39. };
  40. public static readonly Intrinsic[] X86PcmpeqInstruction = new Intrinsic[]
  41. {
  42. Intrinsic.X86Pcmpeqb,
  43. Intrinsic.X86Pcmpeqw,
  44. Intrinsic.X86Pcmpeqd,
  45. Intrinsic.X86Pcmpeqq
  46. };
  47. public static readonly Intrinsic[] X86PcmpgtInstruction = new Intrinsic[]
  48. {
  49. Intrinsic.X86Pcmpgtb,
  50. Intrinsic.X86Pcmpgtw,
  51. Intrinsic.X86Pcmpgtd,
  52. Intrinsic.X86Pcmpgtq
  53. };
  54. public static readonly Intrinsic[] X86PmaxsInstruction = new Intrinsic[]
  55. {
  56. Intrinsic.X86Pmaxsb,
  57. Intrinsic.X86Pmaxsw,
  58. Intrinsic.X86Pmaxsd
  59. };
  60. public static readonly Intrinsic[] X86PmaxuInstruction = new Intrinsic[]
  61. {
  62. Intrinsic.X86Pmaxub,
  63. Intrinsic.X86Pmaxuw,
  64. Intrinsic.X86Pmaxud
  65. };
  66. public static readonly Intrinsic[] X86PminsInstruction = new Intrinsic[]
  67. {
  68. Intrinsic.X86Pminsb,
  69. Intrinsic.X86Pminsw,
  70. Intrinsic.X86Pminsd
  71. };
  72. public static readonly Intrinsic[] X86PminuInstruction = new Intrinsic[]
  73. {
  74. Intrinsic.X86Pminub,
  75. Intrinsic.X86Pminuw,
  76. Intrinsic.X86Pminud
  77. };
  78. public static readonly Intrinsic[] X86PmovsxInstruction = new Intrinsic[]
  79. {
  80. Intrinsic.X86Pmovsxbw,
  81. Intrinsic.X86Pmovsxwd,
  82. Intrinsic.X86Pmovsxdq
  83. };
  84. public static readonly Intrinsic[] X86PmovzxInstruction = new Intrinsic[]
  85. {
  86. Intrinsic.X86Pmovzxbw,
  87. Intrinsic.X86Pmovzxwd,
  88. Intrinsic.X86Pmovzxdq
  89. };
  90. public static readonly Intrinsic[] X86PsllInstruction = new Intrinsic[]
  91. {
  92. 0,
  93. Intrinsic.X86Psllw,
  94. Intrinsic.X86Pslld,
  95. Intrinsic.X86Psllq
  96. };
  97. public static readonly Intrinsic[] X86PsraInstruction = new Intrinsic[]
  98. {
  99. 0,
  100. Intrinsic.X86Psraw,
  101. Intrinsic.X86Psrad
  102. };
  103. public static readonly Intrinsic[] X86PsrlInstruction = new Intrinsic[]
  104. {
  105. 0,
  106. Intrinsic.X86Psrlw,
  107. Intrinsic.X86Psrld,
  108. Intrinsic.X86Psrlq
  109. };
  110. public static readonly Intrinsic[] X86PsubInstruction = new Intrinsic[]
  111. {
  112. Intrinsic.X86Psubb,
  113. Intrinsic.X86Psubw,
  114. Intrinsic.X86Psubd,
  115. Intrinsic.X86Psubq
  116. };
  117. public static readonly Intrinsic[] X86PunpckhInstruction = new Intrinsic[]
  118. {
  119. Intrinsic.X86Punpckhbw,
  120. Intrinsic.X86Punpckhwd,
  121. Intrinsic.X86Punpckhdq,
  122. Intrinsic.X86Punpckhqdq
  123. };
  124. public static readonly Intrinsic[] X86PunpcklInstruction = new Intrinsic[]
  125. {
  126. Intrinsic.X86Punpcklbw,
  127. Intrinsic.X86Punpcklwd,
  128. Intrinsic.X86Punpckldq,
  129. Intrinsic.X86Punpcklqdq
  130. };
  131. #endregion
  132. public static int GetImmShl(OpCodeSimdShImm op)
  133. {
  134. return op.Imm - (8 << op.Size);
  135. }
  136. public static int GetImmShr(OpCodeSimdShImm op)
  137. {
  138. return (8 << (op.Size + 1)) - op.Imm;
  139. }
  140. public static Operand X86GetScalar(ArmEmitterContext context, float value)
  141. {
  142. return X86GetScalar(context, BitConverter.SingleToInt32Bits(value));
  143. }
  144. public static Operand X86GetScalar(ArmEmitterContext context, double value)
  145. {
  146. return X86GetScalar(context, BitConverter.DoubleToInt64Bits(value));
  147. }
  148. public static Operand X86GetScalar(ArmEmitterContext context, int value)
  149. {
  150. return context.VectorCreateScalar(Const(value));
  151. }
  152. public static Operand X86GetScalar(ArmEmitterContext context, long value)
  153. {
  154. return context.VectorCreateScalar(Const(value));
  155. }
  156. public static Operand X86GetAllElements(ArmEmitterContext context, float value)
  157. {
  158. return X86GetAllElements(context, BitConverter.SingleToInt32Bits(value));
  159. }
  160. public static Operand X86GetAllElements(ArmEmitterContext context, double value)
  161. {
  162. return X86GetAllElements(context, BitConverter.DoubleToInt64Bits(value));
  163. }
  164. public static Operand X86GetAllElements(ArmEmitterContext context, int value)
  165. {
  166. Operand vector = context.VectorCreateScalar(Const(value));
  167. vector = context.AddIntrinsic(Intrinsic.X86Shufps, vector, vector, Const(0));
  168. return vector;
  169. }
  170. public static Operand X86GetAllElements(ArmEmitterContext context, long value)
  171. {
  172. Operand vector = context.VectorCreateScalar(Const(value));
  173. vector = context.AddIntrinsic(Intrinsic.X86Movlhps, vector, vector);
  174. return vector;
  175. }
  176. public static Operand X86GetElements(ArmEmitterContext context, long e1, long e0)
  177. {
  178. Operand vector0 = context.VectorCreateScalar(Const(e0));
  179. Operand vector1 = context.VectorCreateScalar(Const(e1));
  180. return context.AddIntrinsic(Intrinsic.X86Punpcklqdq, vector0, vector1);
  181. }
  182. public static int X86GetRoundControl(FPRoundingMode roundMode)
  183. {
  184. switch (roundMode)
  185. {
  186. case FPRoundingMode.ToNearest: return 8 | 0; // even
  187. case FPRoundingMode.TowardsPlusInfinity: return 8 | 2;
  188. case FPRoundingMode.TowardsMinusInfinity: return 8 | 1;
  189. case FPRoundingMode.TowardsZero: return 8 | 3;
  190. }
  191. throw new ArgumentException($"Invalid rounding mode \"{roundMode}\".");
  192. }
  193. public static void EmitScalarUnaryOpF(ArmEmitterContext context, Intrinsic inst32, Intrinsic inst64)
  194. {
  195. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  196. Operand n = GetVec(op.Rn);
  197. Intrinsic inst = (op.Size & 1) != 0 ? inst64 : inst32;
  198. Operand res = context.AddIntrinsic(inst, n);
  199. if ((op.Size & 1) != 0)
  200. {
  201. res = context.VectorZeroUpper64(res);
  202. }
  203. else
  204. {
  205. res = context.VectorZeroUpper96(res);
  206. }
  207. context.Copy(GetVec(op.Rd), res);
  208. }
  209. public static void EmitScalarBinaryOpF(ArmEmitterContext context, Intrinsic inst32, Intrinsic inst64)
  210. {
  211. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  212. Operand n = GetVec(op.Rn);
  213. Operand m = GetVec(op.Rm);
  214. Intrinsic inst = (op.Size & 1) != 0 ? inst64 : inst32;
  215. Operand res = context.AddIntrinsic(inst, n, m);
  216. if ((op.Size & 1) != 0)
  217. {
  218. res = context.VectorZeroUpper64(res);
  219. }
  220. else
  221. {
  222. res = context.VectorZeroUpper96(res);
  223. }
  224. context.Copy(GetVec(op.Rd), res);
  225. }
  226. public static void EmitVectorUnaryOpF(ArmEmitterContext context, Intrinsic inst32, Intrinsic inst64)
  227. {
  228. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  229. Operand n = GetVec(op.Rn);
  230. Intrinsic inst = (op.Size & 1) != 0 ? inst64 : inst32;
  231. Operand res = context.AddIntrinsic(inst, n);
  232. if (op.RegisterSize == RegisterSize.Simd64)
  233. {
  234. res = context.VectorZeroUpper64(res);
  235. }
  236. context.Copy(GetVec(op.Rd), res);
  237. }
  238. public static void EmitVectorBinaryOpF(ArmEmitterContext context, Intrinsic inst32, Intrinsic inst64)
  239. {
  240. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  241. Operand n = GetVec(op.Rn);
  242. Operand m = GetVec(op.Rm);
  243. Intrinsic inst = (op.Size & 1) != 0 ? inst64 : inst32;
  244. Operand res = context.AddIntrinsic(inst, n, m);
  245. if (op.RegisterSize == RegisterSize.Simd64)
  246. {
  247. res = context.VectorZeroUpper64(res);
  248. }
  249. context.Copy(GetVec(op.Rd), res);
  250. }
  251. public static Operand EmitUnaryMathCall(ArmEmitterContext context, string name, Operand n)
  252. {
  253. IOpCodeSimd op = (IOpCodeSimd)context.CurrOp;
  254. MethodInfo info = (op.Size & 1) == 0
  255. ? typeof(MathF).GetMethod(name, new Type[] { typeof(float) })
  256. : typeof(Math). GetMethod(name, new Type[] { typeof(double) });
  257. return context.Call(info, n);
  258. }
  259. public static Operand EmitRoundMathCall(ArmEmitterContext context, MidpointRounding roundMode, Operand n)
  260. {
  261. IOpCodeSimd op = (IOpCodeSimd)context.CurrOp;
  262. string name = nameof(Math.Round);
  263. MethodInfo info = (op.Size & 1) == 0
  264. ? typeof(MathF).GetMethod(name, new Type[] { typeof(float), typeof(MidpointRounding) })
  265. : typeof(Math). GetMethod(name, new Type[] { typeof(double), typeof(MidpointRounding) });
  266. return context.Call(info, n, Const((int)roundMode));
  267. }
  268. public static Operand EmitSoftFloatCall(ArmEmitterContext context, string name, params Operand[] callArgs)
  269. {
  270. IOpCodeSimd op = (IOpCodeSimd)context.CurrOp;
  271. MethodInfo info = (op.Size & 1) == 0
  272. ? typeof(SoftFloat32).GetMethod(name)
  273. : typeof(SoftFloat64).GetMethod(name);
  274. return context.Call(info, callArgs);
  275. }
  276. public static void EmitScalarBinaryOpByElemF(ArmEmitterContext context, Func2I emit)
  277. {
  278. OpCodeSimdRegElemF op = (OpCodeSimdRegElemF)context.CurrOp;
  279. OperandType type = (op.Size & 1) != 0 ? OperandType.FP64 : OperandType.FP32;
  280. Operand n = context.VectorExtract(type, GetVec(op.Rn), 0);
  281. Operand m = context.VectorExtract(type, GetVec(op.Rm), op.Index);
  282. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), emit(n, m), 0));
  283. }
  284. public static void EmitScalarTernaryOpByElemF(ArmEmitterContext context, Func3I emit)
  285. {
  286. OpCodeSimdRegElemF op = (OpCodeSimdRegElemF)context.CurrOp;
  287. OperandType type = (op.Size & 1) != 0 ? OperandType.FP64 : OperandType.FP32;
  288. Operand d = context.VectorExtract(type, GetVec(op.Rd), 0);
  289. Operand n = context.VectorExtract(type, GetVec(op.Rn), 0);
  290. Operand m = context.VectorExtract(type, GetVec(op.Rm), op.Index);
  291. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), emit(d, n, m), 0));
  292. }
  293. public static void EmitScalarUnaryOpSx(ArmEmitterContext context, Func1I emit)
  294. {
  295. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  296. Operand n = EmitVectorExtractSx(context, op.Rn, 0, op.Size);
  297. Operand d = EmitVectorInsert(context, context.VectorZero(), emit(n), 0, op.Size);
  298. context.Copy(GetVec(op.Rd), d);
  299. }
  300. public static void EmitScalarBinaryOpSx(ArmEmitterContext context, Func2I emit)
  301. {
  302. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  303. Operand n = EmitVectorExtractSx(context, op.Rn, 0, op.Size);
  304. Operand m = EmitVectorExtractSx(context, op.Rm, 0, op.Size);
  305. Operand d = EmitVectorInsert(context, context.VectorZero(), emit(n, m), 0, op.Size);
  306. context.Copy(GetVec(op.Rd), d);
  307. }
  308. public static void EmitScalarUnaryOpZx(ArmEmitterContext context, Func1I emit)
  309. {
  310. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  311. Operand n = EmitVectorExtractZx(context, op.Rn, 0, op.Size);
  312. Operand d = EmitVectorInsert(context, context.VectorZero(), emit(n), 0, op.Size);
  313. context.Copy(GetVec(op.Rd), d);
  314. }
  315. public static void EmitScalarBinaryOpZx(ArmEmitterContext context, Func2I emit)
  316. {
  317. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  318. Operand n = EmitVectorExtractZx(context, op.Rn, 0, op.Size);
  319. Operand m = EmitVectorExtractZx(context, op.Rm, 0, op.Size);
  320. Operand d = EmitVectorInsert(context, context.VectorZero(), emit(n, m), 0, op.Size);
  321. context.Copy(GetVec(op.Rd), d);
  322. }
  323. public static void EmitScalarTernaryOpZx(ArmEmitterContext context, Func3I emit)
  324. {
  325. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  326. Operand d = EmitVectorExtractZx(context, op.Rd, 0, op.Size);
  327. Operand n = EmitVectorExtractZx(context, op.Rn, 0, op.Size);
  328. Operand m = EmitVectorExtractZx(context, op.Rm, 0, op.Size);
  329. d = EmitVectorInsert(context, context.VectorZero(), emit(d, n, m), 0, op.Size);
  330. context.Copy(GetVec(op.Rd), d);
  331. }
  332. public static void EmitScalarUnaryOpF(ArmEmitterContext context, Func1I emit)
  333. {
  334. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  335. OperandType type = (op.Size & 1) != 0 ? OperandType.FP64 : OperandType.FP32;
  336. Operand n = context.VectorExtract(type, GetVec(op.Rn), 0);
  337. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), emit(n), 0));
  338. }
  339. public static void EmitScalarBinaryOpF(ArmEmitterContext context, Func2I emit)
  340. {
  341. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  342. OperandType type = (op.Size & 1) != 0 ? OperandType.FP64 : OperandType.FP32;
  343. Operand n = context.VectorExtract(type, GetVec(op.Rn), 0);
  344. Operand m = context.VectorExtract(type, GetVec(op.Rm), 0);
  345. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), emit(n, m), 0));
  346. }
  347. public static void EmitScalarTernaryRaOpF(ArmEmitterContext context, Func3I emit)
  348. {
  349. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  350. OperandType type = (op.Size & 1) != 0 ? OperandType.FP64 : OperandType.FP32;
  351. Operand a = context.VectorExtract(type, GetVec(op.Ra), 0);
  352. Operand n = context.VectorExtract(type, GetVec(op.Rn), 0);
  353. Operand m = context.VectorExtract(type, GetVec(op.Rm), 0);
  354. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), emit(a, n, m), 0));
  355. }
  356. public static void EmitVectorUnaryOpF(ArmEmitterContext context, Func1I emit)
  357. {
  358. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  359. Operand res = context.VectorZero();
  360. int sizeF = op.Size & 1;
  361. OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
  362. int elems = op.GetBytesCount() >> sizeF + 2;
  363. for (int index = 0; index < elems; index++)
  364. {
  365. Operand ne = context.VectorExtract(type, GetVec(op.Rn), index);
  366. res = context.VectorInsert(res, emit(ne), index);
  367. }
  368. context.Copy(GetVec(op.Rd), res);
  369. }
  370. public static void EmitVectorBinaryOpF(ArmEmitterContext context, Func2I emit)
  371. {
  372. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  373. Operand res = context.VectorZero();
  374. int sizeF = op.Size & 1;
  375. OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
  376. int elems = op.GetBytesCount() >> sizeF + 2;
  377. for (int index = 0; index < elems; index++)
  378. {
  379. Operand ne = context.VectorExtract(type, GetVec(op.Rn), index);
  380. Operand me = context.VectorExtract(type, GetVec(op.Rm), index);
  381. res = context.VectorInsert(res, emit(ne, me), index);
  382. }
  383. context.Copy(GetVec(op.Rd), res);
  384. }
  385. public static void EmitVectorTernaryOpF(ArmEmitterContext context, Func3I emit)
  386. {
  387. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  388. Operand res = context.VectorZero();
  389. int sizeF = op.Size & 1;
  390. OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
  391. int elems = op.GetBytesCount() >> sizeF + 2;
  392. for (int index = 0; index < elems; index++)
  393. {
  394. Operand de = context.VectorExtract(type, GetVec(op.Rd), index);
  395. Operand ne = context.VectorExtract(type, GetVec(op.Rn), index);
  396. Operand me = context.VectorExtract(type, GetVec(op.Rm), index);
  397. res = context.VectorInsert(res, emit(de, ne, me), index);
  398. }
  399. context.Copy(GetVec(op.Rd), res);
  400. }
  401. public static void EmitVectorBinaryOpByElemF(ArmEmitterContext context, Func2I emit)
  402. {
  403. OpCodeSimdRegElemF op = (OpCodeSimdRegElemF)context.CurrOp;
  404. Operand res = context.VectorZero();
  405. int sizeF = op.Size & 1;
  406. OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
  407. int elems = op.GetBytesCount() >> sizeF + 2;
  408. for (int index = 0; index < elems; index++)
  409. {
  410. Operand ne = context.VectorExtract(type, GetVec(op.Rn), index);
  411. Operand me = context.VectorExtract(type, GetVec(op.Rm), op.Index);
  412. res = context.VectorInsert(res, emit(ne, me), index);
  413. }
  414. context.Copy(GetVec(op.Rd), res);
  415. }
  416. public static void EmitVectorTernaryOpByElemF(ArmEmitterContext context, Func3I emit)
  417. {
  418. OpCodeSimdRegElemF op = (OpCodeSimdRegElemF)context.CurrOp;
  419. Operand res = context.VectorZero();
  420. int sizeF = op.Size & 1;
  421. OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
  422. int elems = op.GetBytesCount() >> sizeF + 2;
  423. for (int index = 0; index < elems; index++)
  424. {
  425. Operand de = context.VectorExtract(type, GetVec(op.Rd), index);
  426. Operand ne = context.VectorExtract(type, GetVec(op.Rn), index);
  427. Operand me = context.VectorExtract(type, GetVec(op.Rm), op.Index);
  428. res = context.VectorInsert(res, emit(de, ne, me), index);
  429. }
  430. context.Copy(GetVec(op.Rd), res);
  431. }
  432. public static void EmitVectorUnaryOpSx(ArmEmitterContext context, Func1I emit)
  433. {
  434. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  435. Operand res = context.VectorZero();
  436. int elems = op.GetBytesCount() >> op.Size;
  437. for (int index = 0; index < elems; index++)
  438. {
  439. Operand ne = EmitVectorExtractSx(context, op.Rn, index, op.Size);
  440. res = EmitVectorInsert(context, res, emit(ne), index, op.Size);
  441. }
  442. context.Copy(GetVec(op.Rd), res);
  443. }
  444. public static void EmitVectorBinaryOpSx(ArmEmitterContext context, Func2I emit)
  445. {
  446. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  447. Operand res = context.VectorZero();
  448. int elems = op.GetBytesCount() >> op.Size;
  449. for (int index = 0; index < elems; index++)
  450. {
  451. Operand ne = EmitVectorExtractSx(context, op.Rn, index, op.Size);
  452. Operand me = EmitVectorExtractSx(context, op.Rm, index, op.Size);
  453. res = EmitVectorInsert(context, res, emit(ne, me), index, op.Size);
  454. }
  455. context.Copy(GetVec(op.Rd), res);
  456. }
  457. public static void EmitVectorTernaryOpSx(ArmEmitterContext context, Func3I emit)
  458. {
  459. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  460. Operand res = context.VectorZero();
  461. int elems = op.GetBytesCount() >> op.Size;
  462. for (int index = 0; index < elems; index++)
  463. {
  464. Operand de = EmitVectorExtractSx(context, op.Rd, index, op.Size);
  465. Operand ne = EmitVectorExtractSx(context, op.Rn, index, op.Size);
  466. Operand me = EmitVectorExtractSx(context, op.Rm, index, op.Size);
  467. res = EmitVectorInsert(context, res, emit(de, ne, me), index, op.Size);
  468. }
  469. context.Copy(GetVec(op.Rd), res);
  470. }
  471. public static void EmitVectorUnaryOpZx(ArmEmitterContext context, Func1I emit)
  472. {
  473. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  474. Operand res = context.VectorZero();
  475. int elems = op.GetBytesCount() >> op.Size;
  476. for (int index = 0; index < elems; index++)
  477. {
  478. Operand ne = EmitVectorExtractZx(context, op.Rn, index, op.Size);
  479. res = EmitVectorInsert(context, res, emit(ne), index, op.Size);
  480. }
  481. context.Copy(GetVec(op.Rd), res);
  482. }
  483. public static void EmitVectorBinaryOpZx(ArmEmitterContext context, Func2I emit)
  484. {
  485. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  486. Operand res = context.VectorZero();
  487. int elems = op.GetBytesCount() >> op.Size;
  488. for (int index = 0; index < elems; index++)
  489. {
  490. Operand ne = EmitVectorExtractZx(context, op.Rn, index, op.Size);
  491. Operand me = EmitVectorExtractZx(context, op.Rm, index, op.Size);
  492. res = EmitVectorInsert(context, res, emit(ne, me), index, op.Size);
  493. }
  494. context.Copy(GetVec(op.Rd), res);
  495. }
  496. public static void EmitVectorTernaryOpZx(ArmEmitterContext context, Func3I emit)
  497. {
  498. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  499. Operand res = context.VectorZero();
  500. int elems = op.GetBytesCount() >> op.Size;
  501. for (int index = 0; index < elems; index++)
  502. {
  503. Operand de = EmitVectorExtractZx(context, op.Rd, index, op.Size);
  504. Operand ne = EmitVectorExtractZx(context, op.Rn, index, op.Size);
  505. Operand me = EmitVectorExtractZx(context, op.Rm, index, op.Size);
  506. res = EmitVectorInsert(context, res, emit(de, ne, me), index, op.Size);
  507. }
  508. context.Copy(GetVec(op.Rd), res);
  509. }
  510. public static void EmitVectorBinaryOpByElemSx(ArmEmitterContext context, Func2I emit)
  511. {
  512. OpCodeSimdRegElem op = (OpCodeSimdRegElem)context.CurrOp;
  513. Operand res = context.VectorZero();
  514. Operand me = EmitVectorExtractSx(context, op.Rm, op.Index, op.Size);
  515. int elems = op.GetBytesCount() >> op.Size;
  516. for (int index = 0; index < elems; index++)
  517. {
  518. Operand ne = EmitVectorExtractSx(context, op.Rn, index, op.Size);
  519. res = EmitVectorInsert(context, res, emit(ne, me), index, op.Size);
  520. }
  521. context.Copy(GetVec(op.Rd), res);
  522. }
  523. public static void EmitVectorBinaryOpByElemZx(ArmEmitterContext context, Func2I emit)
  524. {
  525. OpCodeSimdRegElem op = (OpCodeSimdRegElem)context.CurrOp;
  526. Operand res = context.VectorZero();
  527. Operand me = EmitVectorExtractZx(context, op.Rm, op.Index, op.Size);
  528. int elems = op.GetBytesCount() >> op.Size;
  529. for (int index = 0; index < elems; index++)
  530. {
  531. Operand ne = EmitVectorExtractZx(context, op.Rn, index, op.Size);
  532. res = EmitVectorInsert(context, res, emit(ne, me), index, op.Size);
  533. }
  534. context.Copy(GetVec(op.Rd), res);
  535. }
  536. public static void EmitVectorTernaryOpByElemZx(ArmEmitterContext context, Func3I emit)
  537. {
  538. OpCodeSimdRegElem op = (OpCodeSimdRegElem)context.CurrOp;
  539. Operand res = context.VectorZero();
  540. Operand me = EmitVectorExtractZx(context, op.Rm, op.Index, op.Size);
  541. int elems = op.GetBytesCount() >> op.Size;
  542. for (int index = 0; index < elems; index++)
  543. {
  544. Operand de = EmitVectorExtractZx(context, op.Rd, index, op.Size);
  545. Operand ne = EmitVectorExtractZx(context, op.Rn, index, op.Size);
  546. res = EmitVectorInsert(context, res, emit(de, ne, me), index, op.Size);
  547. }
  548. context.Copy(GetVec(op.Rd), res);
  549. }
  550. public static void EmitVectorImmUnaryOp(ArmEmitterContext context, Func1I emit)
  551. {
  552. OpCodeSimdImm op = (OpCodeSimdImm)context.CurrOp;
  553. Operand imm = Const(op.Immediate);
  554. Operand res = context.VectorZero();
  555. int elems = op.GetBytesCount() >> op.Size;
  556. for (int index = 0; index < elems; index++)
  557. {
  558. res = EmitVectorInsert(context, res, emit(imm), index, op.Size);
  559. }
  560. context.Copy(GetVec(op.Rd), res);
  561. }
  562. public static void EmitVectorImmBinaryOp(ArmEmitterContext context, Func2I emit)
  563. {
  564. OpCodeSimdImm op = (OpCodeSimdImm)context.CurrOp;
  565. Operand imm = Const(op.Immediate);
  566. Operand res = context.VectorZero();
  567. int elems = op.GetBytesCount() >> op.Size;
  568. for (int index = 0; index < elems; index++)
  569. {
  570. Operand de = EmitVectorExtractZx(context, op.Rd, index, op.Size);
  571. res = EmitVectorInsert(context, res, emit(de, imm), index, op.Size);
  572. }
  573. context.Copy(GetVec(op.Rd), res);
  574. }
  575. public static void EmitVectorWidenRmBinaryOpSx(ArmEmitterContext context, Func2I emit)
  576. {
  577. EmitVectorWidenRmBinaryOp(context, emit, signed: true);
  578. }
  579. public static void EmitVectorWidenRmBinaryOpZx(ArmEmitterContext context, Func2I emit)
  580. {
  581. EmitVectorWidenRmBinaryOp(context, emit, signed: false);
  582. }
  583. private static void EmitVectorWidenRmBinaryOp(ArmEmitterContext context, Func2I emit, bool signed)
  584. {
  585. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  586. Operand res = context.VectorZero();
  587. int elems = 8 >> op.Size;
  588. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  589. for (int index = 0; index < elems; index++)
  590. {
  591. Operand ne = EmitVectorExtract(context, op.Rn, index, op.Size + 1, signed);
  592. Operand me = EmitVectorExtract(context, op.Rm, part + index, op.Size, signed);
  593. res = EmitVectorInsert(context, res, emit(ne, me), index, op.Size + 1);
  594. }
  595. context.Copy(GetVec(op.Rd), res);
  596. }
  597. public static void EmitVectorWidenRnRmBinaryOpSx(ArmEmitterContext context, Func2I emit)
  598. {
  599. EmitVectorWidenRnRmBinaryOp(context, emit, signed: true);
  600. }
  601. public static void EmitVectorWidenRnRmBinaryOpZx(ArmEmitterContext context, Func2I emit)
  602. {
  603. EmitVectorWidenRnRmBinaryOp(context, emit, signed: false);
  604. }
  605. private static void EmitVectorWidenRnRmBinaryOp(ArmEmitterContext context, Func2I emit, bool signed)
  606. {
  607. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  608. Operand res = context.VectorZero();
  609. int elems = 8 >> op.Size;
  610. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  611. for (int index = 0; index < elems; index++)
  612. {
  613. Operand ne = EmitVectorExtract(context, op.Rn, part + index, op.Size, signed);
  614. Operand me = EmitVectorExtract(context, op.Rm, part + index, op.Size, signed);
  615. res = EmitVectorInsert(context, res, emit(ne, me), index, op.Size + 1);
  616. }
  617. context.Copy(GetVec(op.Rd), res);
  618. }
  619. public static void EmitVectorWidenRnRmTernaryOpSx(ArmEmitterContext context, Func3I emit)
  620. {
  621. EmitVectorWidenRnRmTernaryOp(context, emit, signed: true);
  622. }
  623. public static void EmitVectorWidenRnRmTernaryOpZx(ArmEmitterContext context, Func3I emit)
  624. {
  625. EmitVectorWidenRnRmTernaryOp(context, emit, signed: false);
  626. }
  627. private static void EmitVectorWidenRnRmTernaryOp(ArmEmitterContext context, Func3I emit, bool signed)
  628. {
  629. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  630. Operand res = context.VectorZero();
  631. int elems = 8 >> op.Size;
  632. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  633. for (int index = 0; index < elems; index++)
  634. {
  635. Operand de = EmitVectorExtract(context, op.Rd, index, op.Size + 1, signed);
  636. Operand ne = EmitVectorExtract(context, op.Rn, part + index, op.Size, signed);
  637. Operand me = EmitVectorExtract(context, op.Rm, part + index, op.Size, signed);
  638. res = EmitVectorInsert(context, res, emit(de, ne, me), index, op.Size + 1);
  639. }
  640. context.Copy(GetVec(op.Rd), res);
  641. }
  642. public static void EmitVectorWidenBinaryOpByElemSx(ArmEmitterContext context, Func2I emit)
  643. {
  644. EmitVectorWidenBinaryOpByElem(context, emit, signed: true);
  645. }
  646. public static void EmitVectorWidenBinaryOpByElemZx(ArmEmitterContext context, Func2I emit)
  647. {
  648. EmitVectorWidenBinaryOpByElem(context, emit, signed: false);
  649. }
  650. private static void EmitVectorWidenBinaryOpByElem(ArmEmitterContext context, Func2I emit, bool signed)
  651. {
  652. OpCodeSimdRegElem op = (OpCodeSimdRegElem)context.CurrOp;
  653. Operand res = context.VectorZero();
  654. Operand me = EmitVectorExtract(context, op.Rm, op.Index, op.Size, signed);
  655. int elems = 8 >> op.Size;
  656. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  657. for (int index = 0; index < elems; index++)
  658. {
  659. Operand ne = EmitVectorExtract(context, op.Rn, part + index, op.Size, signed);
  660. res = EmitVectorInsert(context, res, emit(ne, me), index, op.Size + 1);
  661. }
  662. context.Copy(GetVec(op.Rd), res);
  663. }
  664. public static void EmitVectorWidenTernaryOpByElemSx(ArmEmitterContext context, Func3I emit)
  665. {
  666. EmitVectorWidenTernaryOpByElem(context, emit, signed: true);
  667. }
  668. public static void EmitVectorWidenTernaryOpByElemZx(ArmEmitterContext context, Func3I emit)
  669. {
  670. EmitVectorWidenTernaryOpByElem(context, emit, signed: false);
  671. }
  672. private static void EmitVectorWidenTernaryOpByElem(ArmEmitterContext context, Func3I emit, bool signed)
  673. {
  674. OpCodeSimdRegElem op = (OpCodeSimdRegElem)context.CurrOp;
  675. Operand res = context.VectorZero();
  676. Operand me = EmitVectorExtract(context, op.Rm, op.Index, op.Size, signed);
  677. int elems = 8 >> op.Size;
  678. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  679. for (int index = 0; index < elems; index++)
  680. {
  681. Operand de = EmitVectorExtract(context, op.Rd, index, op.Size + 1, signed);
  682. Operand ne = EmitVectorExtract(context, op.Rn, part + index, op.Size, signed);
  683. res = EmitVectorInsert(context, res, emit(de, ne, me), index, op.Size + 1);
  684. }
  685. context.Copy(GetVec(op.Rd), res);
  686. }
  687. public static void EmitVectorPairwiseOpSx(ArmEmitterContext context, Func2I emit)
  688. {
  689. EmitVectorPairwiseOp(context, emit, signed: true);
  690. }
  691. public static void EmitVectorPairwiseOpZx(ArmEmitterContext context, Func2I emit)
  692. {
  693. EmitVectorPairwiseOp(context, emit, signed: false);
  694. }
  695. private static void EmitVectorPairwiseOp(ArmEmitterContext context, Func2I emit, bool signed)
  696. {
  697. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  698. Operand res = context.VectorZero();
  699. int pairs = op.GetPairsCount() >> op.Size;
  700. for (int index = 0; index < pairs; index++)
  701. {
  702. int pairIndex = index << 1;
  703. Operand n0 = EmitVectorExtract(context, op.Rn, pairIndex, op.Size, signed);
  704. Operand n1 = EmitVectorExtract(context, op.Rn, pairIndex + 1, op.Size, signed);
  705. Operand m0 = EmitVectorExtract(context, op.Rm, pairIndex, op.Size, signed);
  706. Operand m1 = EmitVectorExtract(context, op.Rm, pairIndex + 1, op.Size, signed);
  707. res = EmitVectorInsert(context, res, emit(n0, n1), index, op.Size);
  708. res = EmitVectorInsert(context, res, emit(m0, m1), pairs + index, op.Size);
  709. }
  710. context.Copy(GetVec(op.Rd), res);
  711. }
  712. public static void EmitSsse3VectorPairwiseOp(ArmEmitterContext context, Intrinsic[] inst)
  713. {
  714. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  715. Operand n = GetVec(op.Rn);
  716. Operand m = GetVec(op.Rm);
  717. if (op.RegisterSize == RegisterSize.Simd64)
  718. {
  719. Operand zeroEvenMask = X86GetElements(context, ZeroMask, EvenMasks[op.Size]);
  720. Operand zeroOddMask = X86GetElements(context, ZeroMask, OddMasks [op.Size]);
  721. Operand mN = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, n, m); // m:n
  722. Operand left = context.AddIntrinsic(Intrinsic.X86Pshufb, mN, zeroEvenMask); // 0:even from m:n
  723. Operand right = context.AddIntrinsic(Intrinsic.X86Pshufb, mN, zeroOddMask); // 0:odd from m:n
  724. context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst[op.Size], left, right));
  725. }
  726. else if (op.Size < 3)
  727. {
  728. Operand oddEvenMask = X86GetElements(context, OddMasks[op.Size], EvenMasks[op.Size]);
  729. Operand oddEvenN = context.AddIntrinsic(Intrinsic.X86Pshufb, n, oddEvenMask); // odd:even from n
  730. Operand oddEvenM = context.AddIntrinsic(Intrinsic.X86Pshufb, m, oddEvenMask); // odd:even from m
  731. Operand left = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, oddEvenN, oddEvenM);
  732. Operand right = context.AddIntrinsic(Intrinsic.X86Punpckhqdq, oddEvenN, oddEvenM);
  733. context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst[op.Size], left, right));
  734. }
  735. else
  736. {
  737. Operand left = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, n, m);
  738. Operand right = context.AddIntrinsic(Intrinsic.X86Punpckhqdq, n, m);
  739. context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst[3], left, right));
  740. }
  741. }
  742. public static void EmitVectorAcrossVectorOpSx(ArmEmitterContext context, Func2I emit)
  743. {
  744. EmitVectorAcrossVectorOp(context, emit, signed: true, isLong: false);
  745. }
  746. public static void EmitVectorAcrossVectorOpZx(ArmEmitterContext context, Func2I emit)
  747. {
  748. EmitVectorAcrossVectorOp(context, emit, signed: false, isLong: false);
  749. }
  750. public static void EmitVectorLongAcrossVectorOpSx(ArmEmitterContext context, Func2I emit)
  751. {
  752. EmitVectorAcrossVectorOp(context, emit, signed: true, isLong: true);
  753. }
  754. public static void EmitVectorLongAcrossVectorOpZx(ArmEmitterContext context, Func2I emit)
  755. {
  756. EmitVectorAcrossVectorOp(context, emit, signed: false, isLong: true);
  757. }
  758. private static void EmitVectorAcrossVectorOp(
  759. ArmEmitterContext context,
  760. Func2I emit,
  761. bool signed,
  762. bool isLong)
  763. {
  764. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  765. int elems = op.GetBytesCount() >> op.Size;
  766. Operand res = EmitVectorExtract(context, op.Rn, 0, op.Size, signed);
  767. for (int index = 1; index < elems; index++)
  768. {
  769. Operand n = EmitVectorExtract(context, op.Rn, index, op.Size, signed);
  770. res = emit(res, n);
  771. }
  772. int size = isLong ? op.Size + 1 : op.Size;
  773. Operand d = EmitVectorInsert(context, context.VectorZero(), res, 0, size);
  774. context.Copy(GetVec(op.Rd), d);
  775. }
  776. public static void EmitVectorAcrossVectorOpF(ArmEmitterContext context, Func2I emit)
  777. {
  778. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  779. Debug.Assert((op.Size & 1) == 0 && op.RegisterSize == RegisterSize.Simd128);
  780. Operand res = context.VectorExtract(OperandType.FP32, GetVec(op.Rn), 0);
  781. for (int index = 1; index < 4; index++)
  782. {
  783. Operand n = context.VectorExtract(OperandType.FP32, GetVec(op.Rn), index);
  784. res = emit(res, n);
  785. }
  786. Operand d = context.VectorInsert(context.VectorZero(), res, 0);
  787. context.Copy(GetVec(op.Rd), d);
  788. }
  789. public static void EmitSse2VectorAcrossVectorOpF(ArmEmitterContext context, Func2I emit)
  790. {
  791. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  792. Debug.Assert((op.Size & 1) == 0 && op.RegisterSize == RegisterSize.Simd128);
  793. const int sm0 = 0 << 6 | 0 << 4 | 0 << 2 | 0 << 0;
  794. const int sm1 = 1 << 6 | 1 << 4 | 1 << 2 | 1 << 0;
  795. const int sm2 = 2 << 6 | 2 << 4 | 2 << 2 | 2 << 0;
  796. const int sm3 = 3 << 6 | 3 << 4 | 3 << 2 | 3 << 0;
  797. Operand nCopy = context.Copy(GetVec(op.Rn));
  798. Operand part0 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, nCopy, Const(sm0));
  799. Operand part1 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, nCopy, Const(sm1));
  800. Operand part2 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, nCopy, Const(sm2));
  801. Operand part3 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, nCopy, Const(sm3));
  802. Operand res = emit(emit(part0, part1), emit(part2, part3));
  803. context.Copy(GetVec(op.Rd), context.VectorZeroUpper96(res));
  804. }
  805. public static void EmitVectorPairwiseOpF(ArmEmitterContext context, Func2I emit)
  806. {
  807. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  808. Operand res = context.VectorZero();
  809. int sizeF = op.Size & 1;
  810. OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
  811. int pairs = op.GetPairsCount() >> sizeF + 2;
  812. for (int index = 0; index < pairs; index++)
  813. {
  814. int pairIndex = index << 1;
  815. Operand n0 = context.VectorExtract(type, GetVec(op.Rn), pairIndex);
  816. Operand n1 = context.VectorExtract(type, GetVec(op.Rn), pairIndex + 1);
  817. Operand m0 = context.VectorExtract(type, GetVec(op.Rm), pairIndex);
  818. Operand m1 = context.VectorExtract(type, GetVec(op.Rm), pairIndex + 1);
  819. res = context.VectorInsert(res, emit(n0, n1), index);
  820. res = context.VectorInsert(res, emit(m0, m1), pairs + index);
  821. }
  822. context.Copy(GetVec(op.Rd), res);
  823. }
  824. public static void EmitSse2VectorPairwiseOpF(ArmEmitterContext context, Func2I emit)
  825. {
  826. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  827. Operand nCopy = context.Copy(GetVec(op.Rn));
  828. Operand mCopy = context.Copy(GetVec(op.Rm));
  829. int sizeF = op.Size & 1;
  830. if (sizeF == 0)
  831. {
  832. if (op.RegisterSize == RegisterSize.Simd64)
  833. {
  834. Operand unpck = context.AddIntrinsic(Intrinsic.X86Unpcklps, nCopy, mCopy);
  835. Operand zero = context.VectorZero();
  836. Operand part0 = context.AddIntrinsic(Intrinsic.X86Movlhps, unpck, zero);
  837. Operand part1 = context.AddIntrinsic(Intrinsic.X86Movhlps, zero, unpck);
  838. context.Copy(GetVec(op.Rd), emit(part0, part1));
  839. }
  840. else /* if (op.RegisterSize == RegisterSize.Simd128) */
  841. {
  842. const int sm0 = 2 << 6 | 0 << 4 | 2 << 2 | 0 << 0;
  843. const int sm1 = 3 << 6 | 1 << 4 | 3 << 2 | 1 << 0;
  844. Operand part0 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, mCopy, Const(sm0));
  845. Operand part1 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, mCopy, Const(sm1));
  846. context.Copy(GetVec(op.Rd), emit(part0, part1));
  847. }
  848. }
  849. else /* if (sizeF == 1) */
  850. {
  851. Operand part0 = context.AddIntrinsic(Intrinsic.X86Unpcklpd, nCopy, mCopy);
  852. Operand part1 = context.AddIntrinsic(Intrinsic.X86Unpckhpd, nCopy, mCopy);
  853. context.Copy(GetVec(op.Rd), emit(part0, part1));
  854. }
  855. }
  856. [Flags]
  857. public enum Mxcsr
  858. {
  859. Ftz = 1 << 15, // Flush To Zero.
  860. Um = 1 << 11, // Underflow Mask.
  861. Dm = 1 << 8, // Denormal Mask.
  862. Daz = 1 << 6 // Denormals Are Zero.
  863. }
  864. public static void EmitSseOrAvxEnterFtzAndDazModesOpF(ArmEmitterContext context, out Operand isTrue)
  865. {
  866. isTrue = context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetFpcrFz)));
  867. Operand lblTrue = Label();
  868. context.BranchIfFalse(lblTrue, isTrue);
  869. context.AddIntrinsicNoRet(Intrinsic.X86Mxcsrmb, Const((int)(Mxcsr.Ftz | Mxcsr.Um | Mxcsr.Dm | Mxcsr.Daz)));
  870. context.MarkLabel(lblTrue);
  871. }
  872. public static void EmitSseOrAvxExitFtzAndDazModesOpF(ArmEmitterContext context, Operand isTrue = null)
  873. {
  874. isTrue ??= context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetFpcrFz)));
  875. Operand lblTrue = Label();
  876. context.BranchIfFalse(lblTrue, isTrue);
  877. context.AddIntrinsicNoRet(Intrinsic.X86Mxcsrub, Const((int)(Mxcsr.Ftz | Mxcsr.Daz)));
  878. context.MarkLabel(lblTrue);
  879. }
  880. public enum CmpCondition
  881. {
  882. // Legacy Sse.
  883. Equal = 0, // Ordered, non-signaling.
  884. LessThan = 1, // Ordered, signaling.
  885. LessThanOrEqual = 2, // Ordered, signaling.
  886. UnorderedQ = 3, // Non-signaling.
  887. NotLessThan = 5, // Unordered, signaling.
  888. NotLessThanOrEqual = 6, // Unordered, signaling.
  889. OrderedQ = 7, // Non-signaling.
  890. // Vex.
  891. GreaterThanOrEqual = 13, // Ordered, signaling.
  892. GreaterThan = 14, // Ordered, signaling.
  893. OrderedS = 23 // Signaling.
  894. }
  895. [Flags]
  896. public enum SaturatingFlags
  897. {
  898. Scalar = 1 << 0,
  899. Signed = 1 << 1,
  900. Add = 1 << 2,
  901. Sub = 1 << 3,
  902. Accumulate = 1 << 4,
  903. ScalarSx = Scalar | Signed,
  904. ScalarZx = Scalar,
  905. VectorSx = Signed,
  906. VectorZx = 0
  907. }
  908. public static void EmitScalarSaturatingUnaryOpSx(ArmEmitterContext context, Func1I emit)
  909. {
  910. EmitSaturatingUnaryOpSx(context, emit, SaturatingFlags.ScalarSx);
  911. }
  912. public static void EmitVectorSaturatingUnaryOpSx(ArmEmitterContext context, Func1I emit)
  913. {
  914. EmitSaturatingUnaryOpSx(context, emit, SaturatingFlags.VectorSx);
  915. }
  916. private static void EmitSaturatingUnaryOpSx(ArmEmitterContext context, Func1I emit, SaturatingFlags flags)
  917. {
  918. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  919. Operand res = context.VectorZero();
  920. bool scalar = (flags & SaturatingFlags.Scalar) != 0;
  921. int elems = !scalar ? op.GetBytesCount() >> op.Size : 1;
  922. for (int index = 0; index < elems; index++)
  923. {
  924. Operand ne = EmitVectorExtractSx(context, op.Rn, index, op.Size);
  925. Operand de;
  926. if (op.Size <= 2)
  927. {
  928. de = EmitSatQ(context, emit(ne), op.Size, signedSrc: true, signedDst: true);
  929. }
  930. else /* if (op.Size == 3) */
  931. {
  932. de = EmitUnarySignedSatQAbsOrNeg(context, emit(ne));
  933. }
  934. res = EmitVectorInsert(context, res, de, index, op.Size);
  935. }
  936. context.Copy(GetVec(op.Rd), res);
  937. }
  938. public static void EmitScalarSaturatingBinaryOpSx(ArmEmitterContext context, SaturatingFlags flags)
  939. {
  940. EmitSaturatingBinaryOp(context, null, SaturatingFlags.ScalarSx | flags);
  941. }
  942. public static void EmitScalarSaturatingBinaryOpZx(ArmEmitterContext context, SaturatingFlags flags)
  943. {
  944. EmitSaturatingBinaryOp(context, null, SaturatingFlags.ScalarZx | flags);
  945. }
  946. public static void EmitVectorSaturatingBinaryOpSx(ArmEmitterContext context, SaturatingFlags flags)
  947. {
  948. EmitSaturatingBinaryOp(context, null, SaturatingFlags.VectorSx | flags);
  949. }
  950. public static void EmitVectorSaturatingBinaryOpZx(ArmEmitterContext context, SaturatingFlags flags)
  951. {
  952. EmitSaturatingBinaryOp(context, null, SaturatingFlags.VectorZx | flags);
  953. }
  954. public static void EmitSaturatingBinaryOp(ArmEmitterContext context, Func2I emit, SaturatingFlags flags)
  955. {
  956. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  957. Operand res = context.VectorZero();
  958. bool scalar = (flags & SaturatingFlags.Scalar) != 0;
  959. bool signed = (flags & SaturatingFlags.Signed) != 0;
  960. bool add = (flags & SaturatingFlags.Add) != 0;
  961. bool sub = (flags & SaturatingFlags.Sub) != 0;
  962. bool accumulate = (flags & SaturatingFlags.Accumulate) != 0;
  963. int elems = !scalar ? op.GetBytesCount() >> op.Size : 1;
  964. if (add || sub)
  965. {
  966. OpCodeSimdReg opReg = (OpCodeSimdReg)op;
  967. for (int index = 0; index < elems; index++)
  968. {
  969. Operand de;
  970. Operand ne = EmitVectorExtract(context, opReg.Rn, index, op.Size, signed);
  971. Operand me = EmitVectorExtract(context, opReg.Rm, index, op.Size, signed);
  972. if (op.Size <= 2)
  973. {
  974. Operand temp = add ? context.Add(ne, me) : context.Subtract(ne, me);
  975. de = EmitSatQ(context, temp, op.Size, signedSrc: true, signedDst: signed);
  976. }
  977. else if (add) /* if (op.Size == 3) */
  978. {
  979. de = EmitBinarySatQAdd(context, ne, me, signed);
  980. }
  981. else /* if (sub) */
  982. {
  983. de = EmitBinarySatQSub(context, ne, me, signed);
  984. }
  985. res = EmitVectorInsert(context, res, de, index, op.Size);
  986. }
  987. }
  988. else if (accumulate)
  989. {
  990. for (int index = 0; index < elems; index++)
  991. {
  992. Operand de;
  993. Operand ne = EmitVectorExtract(context, op.Rn, index, op.Size, !signed);
  994. Operand me = EmitVectorExtract(context, op.Rd, index, op.Size, signed);
  995. if (op.Size <= 2)
  996. {
  997. Operand temp = context.Add(ne, me);
  998. de = EmitSatQ(context, temp, op.Size, signedSrc: true, signedDst: signed);
  999. }
  1000. else /* if (op.Size == 3) */
  1001. {
  1002. de = EmitBinarySatQAccumulate(context, ne, me, signed);
  1003. }
  1004. res = EmitVectorInsert(context, res, de, index, op.Size);
  1005. }
  1006. }
  1007. else
  1008. {
  1009. OpCodeSimdReg opReg = (OpCodeSimdReg)op;
  1010. for (int index = 0; index < elems; index++)
  1011. {
  1012. Operand ne = EmitVectorExtract(context, opReg.Rn, index, op.Size, signed);
  1013. Operand me = EmitVectorExtract(context, opReg.Rm, index, op.Size, signed);
  1014. Operand de = EmitSatQ(context, emit(ne, me), op.Size, true, signed);
  1015. res = EmitVectorInsert(context, res, de, index, op.Size);
  1016. }
  1017. }
  1018. context.Copy(GetVec(op.Rd), res);
  1019. }
  1020. [Flags]
  1021. public enum SaturatingNarrowFlags
  1022. {
  1023. Scalar = 1 << 0,
  1024. SignedSrc = 1 << 1,
  1025. SignedDst = 1 << 2,
  1026. ScalarSxSx = Scalar | SignedSrc | SignedDst,
  1027. ScalarSxZx = Scalar | SignedSrc,
  1028. ScalarZxZx = Scalar,
  1029. VectorSxSx = SignedSrc | SignedDst,
  1030. VectorSxZx = SignedSrc,
  1031. VectorZxZx = 0
  1032. }
  1033. public static void EmitSaturatingNarrowOp(ArmEmitterContext context, SaturatingNarrowFlags flags)
  1034. {
  1035. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  1036. bool scalar = (flags & SaturatingNarrowFlags.Scalar) != 0;
  1037. bool signedSrc = (flags & SaturatingNarrowFlags.SignedSrc) != 0;
  1038. bool signedDst = (flags & SaturatingNarrowFlags.SignedDst) != 0;
  1039. int elems = !scalar ? 8 >> op.Size : 1;
  1040. int part = !scalar && (op.RegisterSize == RegisterSize.Simd128) ? elems : 0;
  1041. Operand d = GetVec(op.Rd);
  1042. Operand res = part == 0 ? context.VectorZero() : context.Copy(d);
  1043. for (int index = 0; index < elems; index++)
  1044. {
  1045. Operand ne = EmitVectorExtract(context, op.Rn, index, op.Size + 1, signedSrc);
  1046. Operand temp = EmitSatQ(context, ne, op.Size, signedSrc, signedDst);
  1047. res = EmitVectorInsert(context, res, temp, part + index, op.Size);
  1048. }
  1049. context.Copy(d, res);
  1050. }
  1051. // TSrc (16bit, 32bit, 64bit; signed, unsigned) > TDst (8bit, 16bit, 32bit; signed, unsigned).
  1052. public static Operand EmitSatQ(ArmEmitterContext context, Operand op, int sizeDst, bool signedSrc, bool signedDst)
  1053. {
  1054. if ((uint)sizeDst > 2u)
  1055. {
  1056. throw new ArgumentOutOfRangeException(nameof(sizeDst));
  1057. }
  1058. MethodInfo info;
  1059. if (signedSrc)
  1060. {
  1061. info = signedDst
  1062. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SignedSrcSignedDstSatQ))
  1063. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SignedSrcUnsignedDstSatQ));
  1064. }
  1065. else
  1066. {
  1067. info = signedDst
  1068. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.UnsignedSrcSignedDstSatQ))
  1069. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.UnsignedSrcUnsignedDstSatQ));
  1070. }
  1071. return context.Call(info, op, Const(sizeDst));
  1072. }
  1073. // TSrc (64bit) == TDst (64bit); signed.
  1074. public static Operand EmitUnarySignedSatQAbsOrNeg(ArmEmitterContext context, Operand op)
  1075. {
  1076. Debug.Assert(((OpCodeSimd)context.CurrOp).Size == 3, "Invalid element size.");
  1077. return context.Call(typeof(SoftFallback).GetMethod(nameof(SoftFallback.UnarySignedSatQAbsOrNeg)), op);
  1078. }
  1079. // TSrcs (64bit) == TDst (64bit); signed, unsigned.
  1080. public static Operand EmitBinarySatQAdd(ArmEmitterContext context, Operand op1, Operand op2, bool signed)
  1081. {
  1082. Debug.Assert(((OpCodeSimd)context.CurrOp).Size == 3, "Invalid element size.");
  1083. MethodInfo info = signed
  1084. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.BinarySignedSatQAdd))
  1085. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.BinaryUnsignedSatQAdd));
  1086. return context.Call(info, op1, op2);
  1087. }
  1088. // TSrcs (64bit) == TDst (64bit); signed, unsigned.
  1089. public static Operand EmitBinarySatQSub(ArmEmitterContext context, Operand op1, Operand op2, bool signed)
  1090. {
  1091. Debug.Assert(((OpCodeSimd)context.CurrOp).Size == 3, "Invalid element size.");
  1092. MethodInfo info = signed
  1093. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.BinarySignedSatQSub))
  1094. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.BinaryUnsignedSatQSub));
  1095. return context.Call(info, op1, op2);
  1096. }
  1097. // TSrcs (64bit) == TDst (64bit); signed, unsigned.
  1098. public static Operand EmitBinarySatQAccumulate(ArmEmitterContext context, Operand op1, Operand op2, bool signed)
  1099. {
  1100. Debug.Assert(((OpCodeSimd)context.CurrOp).Size == 3, "Invalid element size.");
  1101. MethodInfo info = signed
  1102. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.BinarySignedSatQAcc))
  1103. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.BinaryUnsignedSatQAcc));
  1104. return context.Call(info, op1, op2);
  1105. }
  1106. public static Operand EmitFloatAbs(ArmEmitterContext context, Operand value, bool single, bool vector)
  1107. {
  1108. Operand mask;
  1109. if (single)
  1110. {
  1111. mask = vector ? X86GetAllElements(context, -0f) : X86GetScalar(context, -0f);
  1112. }
  1113. else
  1114. {
  1115. mask = vector ? X86GetAllElements(context, -0d) : X86GetScalar(context, -0d);
  1116. }
  1117. return context.AddIntrinsic(single ? Intrinsic.X86Andnps : Intrinsic.X86Andnpd, mask, value);
  1118. }
  1119. public static Operand EmitVectorExtractSx(ArmEmitterContext context, int reg, int index, int size)
  1120. {
  1121. return EmitVectorExtract(context, reg, index, size, true);
  1122. }
  1123. public static Operand EmitVectorExtractZx(ArmEmitterContext context, int reg, int index, int size)
  1124. {
  1125. return EmitVectorExtract(context, reg, index, size, false);
  1126. }
  1127. public static Operand EmitVectorExtract(ArmEmitterContext context, int reg, int index, int size, bool signed)
  1128. {
  1129. ThrowIfInvalid(index, size);
  1130. Operand res = null;
  1131. switch (size)
  1132. {
  1133. case 0:
  1134. res = context.VectorExtract8(GetVec(reg), index);
  1135. break;
  1136. case 1:
  1137. res = context.VectorExtract16(GetVec(reg), index);
  1138. break;
  1139. case 2:
  1140. res = context.VectorExtract(OperandType.I32, GetVec(reg), index);
  1141. break;
  1142. case 3:
  1143. res = context.VectorExtract(OperandType.I64, GetVec(reg), index);
  1144. break;
  1145. }
  1146. if (signed)
  1147. {
  1148. switch (size)
  1149. {
  1150. case 0: res = context.SignExtend8 (OperandType.I64, res); break;
  1151. case 1: res = context.SignExtend16(OperandType.I64, res); break;
  1152. case 2: res = context.SignExtend32(OperandType.I64, res); break;
  1153. }
  1154. }
  1155. else
  1156. {
  1157. switch (size)
  1158. {
  1159. case 0: res = context.ZeroExtend8 (OperandType.I64, res); break;
  1160. case 1: res = context.ZeroExtend16(OperandType.I64, res); break;
  1161. case 2: res = context.ZeroExtend32(OperandType.I64, res); break;
  1162. }
  1163. }
  1164. return res;
  1165. }
  1166. public static Operand EmitVectorInsert(ArmEmitterContext context, Operand vector, Operand value, int index, int size)
  1167. {
  1168. ThrowIfInvalid(index, size);
  1169. if (size < 3 && value.Type == OperandType.I64)
  1170. {
  1171. value = context.ConvertI64ToI32(value);
  1172. }
  1173. switch (size)
  1174. {
  1175. case 0: vector = context.VectorInsert8 (vector, value, index); break;
  1176. case 1: vector = context.VectorInsert16(vector, value, index); break;
  1177. case 2: vector = context.VectorInsert (vector, value, index); break;
  1178. case 3: vector = context.VectorInsert (vector, value, index); break;
  1179. }
  1180. return vector;
  1181. }
  1182. public static void ThrowIfInvalid(int index, int size)
  1183. {
  1184. if ((uint)size > 3u)
  1185. {
  1186. throw new ArgumentOutOfRangeException(nameof(size));
  1187. }
  1188. if ((uint)index >= 16u >> size)
  1189. {
  1190. throw new ArgumentOutOfRangeException(nameof(index));
  1191. }
  1192. }
  1193. }
  1194. }