CpuTestBfm.cs 8.6 KB

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  1. //#define Bfm
  2. using ChocolArm64.State;
  3. using NUnit.Framework;
  4. namespace Ryujinx.Tests.Cpu
  5. {
  6. using Tester;
  7. using Tester.Types;
  8. [Category("Bfm"), Ignore("Tested: first half of 2018.")]
  9. public sealed class CpuTestBfm : CpuTest
  10. {
  11. #if Bfm
  12. [SetUp]
  13. public void SetupTester()
  14. {
  15. AArch64.TakeReset(false);
  16. }
  17. [Test, Description("BFM <Xd>, <Xn>, #<immr>, #<imms>")]
  18. public void Bfm_64bit([Values(0u, 31u)] uint Rd,
  19. [Values(1u, 31u)] uint Rn,
  20. [Random(2)] ulong _Xd,
  21. [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
  22. 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn,
  23. [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr,
  24. [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint imms)
  25. {
  26. uint Opcode = 0xB3400000; // BFM X0, X0, #0, #0
  27. Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
  28. Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
  29. ulong _X31 = TestContext.CurrentContext.Random.NextULong();
  30. AThreadState ThreadState = SingleOpcode(Opcode, X0: _Xd, X1: Xn, X31: _X31);
  31. if (Rd != 31)
  32. {
  33. Bits Op = new Bits(Opcode);
  34. AArch64.X((int)Rd, new Bits(_Xd));
  35. AArch64.X((int)Rn, new Bits(Xn));
  36. Base.Bfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
  37. ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
  38. Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
  39. }
  40. else
  41. {
  42. Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
  43. }
  44. }
  45. [Test, Description("BFM <Wd>, <Wn>, #<immr>, #<imms>")]
  46. public void Bfm_32bit([Values(0u, 31u)] uint Rd,
  47. [Values(1u, 31u)] uint Rn,
  48. [Random(2)] uint _Wd,
  49. [Values(0x00000000u, 0x7FFFFFFFu,
  50. 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn,
  51. [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr,
  52. [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint imms)
  53. {
  54. uint Opcode = 0x33000000; // BFM W0, W0, #0, #0
  55. Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
  56. Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
  57. uint _W31 = TestContext.CurrentContext.Random.NextUInt();
  58. AThreadState ThreadState = SingleOpcode(Opcode, X0: _Wd, X1: Wn, X31: _W31);
  59. if (Rd != 31)
  60. {
  61. Bits Op = new Bits(Opcode);
  62. AArch64.X((int)Rd, new Bits(_Wd));
  63. AArch64.X((int)Rn, new Bits(Wn));
  64. Base.Bfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
  65. uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
  66. Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
  67. }
  68. else
  69. {
  70. Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
  71. }
  72. }
  73. [Test, Description("SBFM <Xd>, <Xn>, #<immr>, #<imms>")]
  74. public void Sbfm_64bit([Values(0u, 31u)] uint Rd,
  75. [Values(1u, 31u)] uint Rn,
  76. [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
  77. 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn,
  78. [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr,
  79. [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint imms)
  80. {
  81. uint Opcode = 0x93400000; // SBFM X0, X0, #0, #0
  82. Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
  83. Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
  84. ulong _X31 = TestContext.CurrentContext.Random.NextULong();
  85. AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
  86. if (Rd != 31)
  87. {
  88. Bits Op = new Bits(Opcode);
  89. AArch64.X((int)Rn, new Bits(Xn));
  90. Base.Sbfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
  91. ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
  92. Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
  93. }
  94. else
  95. {
  96. Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
  97. }
  98. }
  99. [Test, Description("SBFM <Wd>, <Wn>, #<immr>, #<imms>")]
  100. public void Sbfm_32bit([Values(0u, 31u)] uint Rd,
  101. [Values(1u, 31u)] uint Rn,
  102. [Values(0x00000000u, 0x7FFFFFFFu,
  103. 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn,
  104. [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr,
  105. [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint imms)
  106. {
  107. uint Opcode = 0x13000000; // SBFM W0, W0, #0, #0
  108. Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
  109. Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
  110. uint _W31 = TestContext.CurrentContext.Random.NextUInt();
  111. AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
  112. if (Rd != 31)
  113. {
  114. Bits Op = new Bits(Opcode);
  115. AArch64.X((int)Rn, new Bits(Wn));
  116. Base.Sbfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
  117. uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
  118. Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
  119. }
  120. else
  121. {
  122. Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
  123. }
  124. }
  125. [Test, Description("UBFM <Xd>, <Xn>, #<immr>, #<imms>")]
  126. public void Ubfm_64bit([Values(0u, 31u)] uint Rd,
  127. [Values(1u, 31u)] uint Rn,
  128. [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
  129. 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn,
  130. [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr,
  131. [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint imms)
  132. {
  133. uint Opcode = 0xD3400000; // UBFM X0, X0, #0, #0
  134. Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
  135. Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
  136. ulong _X31 = TestContext.CurrentContext.Random.NextULong();
  137. AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
  138. if (Rd != 31)
  139. {
  140. Bits Op = new Bits(Opcode);
  141. AArch64.X((int)Rn, new Bits(Xn));
  142. Base.Ubfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
  143. ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
  144. Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
  145. }
  146. else
  147. {
  148. Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
  149. }
  150. }
  151. [Test, Description("UBFM <Wd>, <Wn>, #<immr>, #<imms>")]
  152. public void Ubfm_32bit([Values(0u, 31u)] uint Rd,
  153. [Values(1u, 31u)] uint Rn,
  154. [Values(0x00000000u, 0x7FFFFFFFu,
  155. 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn,
  156. [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr,
  157. [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint imms)
  158. {
  159. uint Opcode = 0x53000000; // UBFM W0, W0, #0, #0
  160. Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
  161. Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
  162. uint _W31 = TestContext.CurrentContext.Random.NextUInt();
  163. AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
  164. if (Rd != 31)
  165. {
  166. Bits Op = new Bits(Opcode);
  167. AArch64.X((int)Rn, new Bits(Wn));
  168. Base.Ubfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
  169. uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
  170. Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
  171. }
  172. else
  173. {
  174. Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
  175. }
  176. }
  177. #endif
  178. }
  179. }