CpuTestAlu.cs 12 KB

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  1. //#define Alu
  2. using ChocolArm64.State;
  3. using NUnit.Framework;
  4. namespace Ryujinx.Tests.Cpu
  5. {
  6. using Tester;
  7. using Tester.Types;
  8. [Category("Alu"), Ignore("Tested: first half of 2018.")]
  9. public sealed class CpuTestAlu : CpuTest
  10. {
  11. #if Alu
  12. [SetUp]
  13. public void SetupTester()
  14. {
  15. AArch64.TakeReset(false);
  16. }
  17. [Test, Description("CLS <Xd>, <Xn>")]
  18. public void Cls_64bit([Values(0u, 31u)] uint Rd,
  19. [Values(1u, 31u)] uint Rn,
  20. [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
  21. 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn)
  22. {
  23. uint Opcode = 0xDAC01400; // CLS X0, X0
  24. Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
  25. ulong _X31 = TestContext.CurrentContext.Random.NextULong();
  26. AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
  27. if (Rd != 31)
  28. {
  29. Bits Op = new Bits(Opcode);
  30. AArch64.X((int)Rn, new Bits(Xn));
  31. Base.Cls(Op[31], Op[9, 5], Op[4, 0]);
  32. ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
  33. Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
  34. }
  35. else
  36. {
  37. Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
  38. }
  39. }
  40. [Test, Description("CLS <Wd>, <Wn>")]
  41. public void Cls_32bit([Values(0u, 31u)] uint Rd,
  42. [Values(1u, 31u)] uint Rn,
  43. [Values(0x00000000u, 0x7FFFFFFFu,
  44. 0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn)
  45. {
  46. uint Opcode = 0x5AC01400; // CLS W0, W0
  47. Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
  48. uint _W31 = TestContext.CurrentContext.Random.NextUInt();
  49. AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
  50. if (Rd != 31)
  51. {
  52. Bits Op = new Bits(Opcode);
  53. AArch64.X((int)Rn, new Bits(Wn));
  54. Base.Cls(Op[31], Op[9, 5], Op[4, 0]);
  55. uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
  56. Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
  57. }
  58. else
  59. {
  60. Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
  61. }
  62. }
  63. [Test, Description("CLZ <Xd>, <Xn>")]
  64. public void Clz_64bit([Values(0u, 31u)] uint Rd,
  65. [Values(1u, 31u)] uint Rn,
  66. [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
  67. 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn)
  68. {
  69. uint Opcode = 0xDAC01000; // CLZ X0, X0
  70. Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
  71. ulong _X31 = TestContext.CurrentContext.Random.NextULong();
  72. AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
  73. if (Rd != 31)
  74. {
  75. Bits Op = new Bits(Opcode);
  76. AArch64.X((int)Rn, new Bits(Xn));
  77. Base.Clz(Op[31], Op[9, 5], Op[4, 0]);
  78. ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
  79. Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
  80. }
  81. else
  82. {
  83. Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
  84. }
  85. }
  86. [Test, Description("CLZ <Wd>, <Wn>")]
  87. public void Clz_32bit([Values(0u, 31u)] uint Rd,
  88. [Values(1u, 31u)] uint Rn,
  89. [Values(0x00000000u, 0x7FFFFFFFu,
  90. 0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn)
  91. {
  92. uint Opcode = 0x5AC01000; // CLZ W0, W0
  93. Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
  94. uint _W31 = TestContext.CurrentContext.Random.NextUInt();
  95. AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
  96. if (Rd != 31)
  97. {
  98. Bits Op = new Bits(Opcode);
  99. AArch64.X((int)Rn, new Bits(Wn));
  100. Base.Clz(Op[31], Op[9, 5], Op[4, 0]);
  101. uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
  102. Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
  103. }
  104. else
  105. {
  106. Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
  107. }
  108. }
  109. [Test, Description("RBIT <Xd>, <Xn>")]
  110. public void Rbit_64bit([Values(0u, 31u)] uint Rd,
  111. [Values(1u, 31u)] uint Rn,
  112. [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
  113. 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn)
  114. {
  115. uint Opcode = 0xDAC00000; // RBIT X0, X0
  116. Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
  117. ulong _X31 = TestContext.CurrentContext.Random.NextULong();
  118. AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
  119. if (Rd != 31)
  120. {
  121. Bits Op = new Bits(Opcode);
  122. AArch64.X((int)Rn, new Bits(Xn));
  123. Base.Rbit(Op[31], Op[9, 5], Op[4, 0]);
  124. ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
  125. Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
  126. }
  127. else
  128. {
  129. Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
  130. }
  131. }
  132. [Test, Description("RBIT <Wd>, <Wn>")]
  133. public void Rbit_32bit([Values(0u, 31u)] uint Rd,
  134. [Values(1u, 31u)] uint Rn,
  135. [Values(0x00000000u, 0x7FFFFFFFu,
  136. 0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn)
  137. {
  138. uint Opcode = 0x5AC00000; // RBIT W0, W0
  139. Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
  140. uint _W31 = TestContext.CurrentContext.Random.NextUInt();
  141. AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
  142. if (Rd != 31)
  143. {
  144. Bits Op = new Bits(Opcode);
  145. AArch64.X((int)Rn, new Bits(Wn));
  146. Base.Rbit(Op[31], Op[9, 5], Op[4, 0]);
  147. uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
  148. Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
  149. }
  150. else
  151. {
  152. Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
  153. }
  154. }
  155. [Test, Description("REV16 <Xd>, <Xn>")]
  156. public void Rev16_64bit([Values(0u, 31u)] uint Rd,
  157. [Values(1u, 31u)] uint Rn,
  158. [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
  159. 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn)
  160. {
  161. uint Opcode = 0xDAC00400; // REV16 X0, X0
  162. Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
  163. ulong _X31 = TestContext.CurrentContext.Random.NextULong();
  164. AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
  165. if (Rd != 31)
  166. {
  167. Bits Op = new Bits(Opcode);
  168. AArch64.X((int)Rn, new Bits(Xn));
  169. Base.Rev16(Op[31], Op[9, 5], Op[4, 0]);
  170. ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
  171. Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
  172. }
  173. else
  174. {
  175. Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
  176. }
  177. }
  178. [Test, Description("REV16 <Wd>, <Wn>")]
  179. public void Rev16_32bit([Values(0u, 31u)] uint Rd,
  180. [Values(1u, 31u)] uint Rn,
  181. [Values(0x00000000u, 0x7FFFFFFFu,
  182. 0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn)
  183. {
  184. uint Opcode = 0x5AC00400; // REV16 W0, W0
  185. Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
  186. uint _W31 = TestContext.CurrentContext.Random.NextUInt();
  187. AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
  188. if (Rd != 31)
  189. {
  190. Bits Op = new Bits(Opcode);
  191. AArch64.X((int)Rn, new Bits(Wn));
  192. Base.Rev16(Op[31], Op[9, 5], Op[4, 0]);
  193. uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
  194. Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
  195. }
  196. else
  197. {
  198. Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
  199. }
  200. }
  201. [Test, Description("REV32 <Xd>, <Xn>")]
  202. public void Rev32_64bit([Values(0u, 31u)] uint Rd,
  203. [Values(1u, 31u)] uint Rn,
  204. [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
  205. 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn)
  206. {
  207. uint Opcode = 0xDAC00800; // REV32 X0, X0
  208. Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
  209. ulong _X31 = TestContext.CurrentContext.Random.NextULong();
  210. AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
  211. if (Rd != 31)
  212. {
  213. Bits Op = new Bits(Opcode);
  214. AArch64.X((int)Rn, new Bits(Xn));
  215. Base.Rev32(Op[31], Op[9, 5], Op[4, 0]);
  216. ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
  217. Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
  218. }
  219. else
  220. {
  221. Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
  222. }
  223. }
  224. [Test, Description("REV <Wd>, <Wn>")]
  225. public void Rev32_32bit([Values(0u, 31u)] uint Rd,
  226. [Values(1u, 31u)] uint Rn,
  227. [Values(0x00000000u, 0x7FFFFFFFu,
  228. 0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn)
  229. {
  230. uint Opcode = 0x5AC00800; // REV W0, W0
  231. Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
  232. uint _W31 = TestContext.CurrentContext.Random.NextUInt();
  233. AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
  234. if (Rd != 31)
  235. {
  236. Bits Op = new Bits(Opcode);
  237. AArch64.X((int)Rn, new Bits(Wn));
  238. Base.Rev32(Op[31], Op[9, 5], Op[4, 0]);
  239. uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
  240. Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
  241. }
  242. else
  243. {
  244. Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
  245. }
  246. }
  247. [Test, Description("REV64 <Xd>, <Xn>")]
  248. public void Rev64_64bit([Values(0u, 31u)] uint Rd,
  249. [Values(1u, 31u)] uint Rn,
  250. [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
  251. 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn)
  252. {
  253. uint Opcode = 0xDAC00C00; // REV64 X0, X0
  254. Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
  255. ulong _X31 = TestContext.CurrentContext.Random.NextULong();
  256. AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
  257. if (Rd != 31)
  258. {
  259. Bits Op = new Bits(Opcode);
  260. AArch64.X((int)Rn, new Bits(Xn));
  261. Base.Rev64(Op[9, 5], Op[4, 0]);
  262. ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
  263. Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
  264. }
  265. else
  266. {
  267. Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
  268. }
  269. }
  270. #endif
  271. }
  272. }