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Aarch32Mode.cs
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a731ab3a2a
Add a new JIT compiler for CPU code (#693)
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6 lat temu |
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ExceptionCallback.cs
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0c87bf9ea4
Refactor CPU interface to allow the implementation of other CPU emulators (#3362)
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3 lat temu |
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ExecutionContext.cs
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814f75142e
Fpsr and Fpcr freed. (#3701)
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3 lat temu |
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ExecutionMode.cs
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dc0adb533d
PPTC & Pool Enhancements. (#1968)
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5 lat temu |
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FPCR.cs
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814f75142e
Fpsr and Fpcr freed. (#3701)
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3 lat temu |
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FPException.cs
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a731ab3a2a
Add a new JIT compiler for CPU code (#693)
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6 lat temu |
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FPRoundingMode.cs
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5af8ce7c38
A64: Add fast path for Fcvtas_Gp/S/V, Fcvtau_Gp/S/V and Frinta_S/V in… (#3712)
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3 lat temu |
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FPSCR.cs
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814f75142e
Fpsr and Fpcr freed. (#3701)
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3 lat temu |
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FPSR.cs
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814f75142e
Fpsr and Fpcr freed. (#3701)
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3 lat temu |
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FPState.cs
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814f75142e
Fpsr and Fpcr freed. (#3701)
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3 lat temu |
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FPType.cs
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a731ab3a2a
Add a new JIT compiler for CPU code (#693)
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6 lat temu |
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ICounter.cs
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0c87bf9ea4
Refactor CPU interface to allow the implementation of other CPU emulators (#3362)
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3 lat temu |
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NativeContext.cs
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814f75142e
Fpsr and Fpcr freed. (#3701)
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3 lat temu |
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PState.cs
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8e119a1e96
Implement PLD and SUB (imm16) on T32, plus UADD8, SADD8, USUB8 and SSUB8 on both A32 and T32 (#3693)
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3 lat temu |
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RegisterAlias.cs
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b1b6f294f2
Add most of the A32 instruction set to ARMeilleure (#897)
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6 lat temu |
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RegisterConsts.cs
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b1b6f294f2
Add most of the A32 instruction set to ARMeilleure (#897)
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6 lat temu |
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V128.cs
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430ba6da65
CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)
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5 lat temu |
LDj3SNuD
5af8ce7c38
A64: Add fast path for Fcvtas_Gp/S/V, Fcvtau_Gp/S/V and Frinta_S/V in… (#3712)