InstEmitSimdCvt.cs 62 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717
  1. using ARMeilleure.Decoders;
  2. using ARMeilleure.IntermediateRepresentation;
  3. using ARMeilleure.State;
  4. using ARMeilleure.Translation;
  5. using System;
  6. using System.Diagnostics;
  7. using System.Reflection;
  8. using static ARMeilleure.Instructions.InstEmitHelper;
  9. using static ARMeilleure.Instructions.InstEmitSimdHelper;
  10. using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
  11. namespace ARMeilleure.Instructions
  12. {
  13. using Func1I = Func<Operand, Operand>;
  14. static partial class InstEmit
  15. {
  16. public static void Fcvt_S(ArmEmitterContext context)
  17. {
  18. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  19. if (op.Size == 0 && op.Opc == 1) // Single -> Double.
  20. {
  21. if (Optimizations.UseSse2)
  22. {
  23. Operand n = GetVec(op.Rn);
  24. Operand res = context.AddIntrinsic(Intrinsic.X86Cvtss2sd, context.VectorZero(), n);
  25. context.Copy(GetVec(op.Rd), res);
  26. }
  27. else
  28. {
  29. Operand ne = context.VectorExtract(OperandType.FP32, GetVec(op.Rn), 0);
  30. Operand res = context.ConvertToFP(OperandType.FP64, ne);
  31. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  32. }
  33. }
  34. else if (op.Size == 1 && op.Opc == 0) // Double -> Single.
  35. {
  36. if (Optimizations.UseSse2)
  37. {
  38. Operand n = GetVec(op.Rn);
  39. Operand res = context.AddIntrinsic(Intrinsic.X86Cvtsd2ss, context.VectorZero(), n);
  40. context.Copy(GetVec(op.Rd), res);
  41. }
  42. else
  43. {
  44. Operand ne = context.VectorExtract(OperandType.FP64, GetVec(op.Rn), 0);
  45. Operand res = context.ConvertToFP(OperandType.FP32, ne);
  46. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  47. }
  48. }
  49. else if (op.Size == 0 && op.Opc == 3) // Single -> Half.
  50. {
  51. if (Optimizations.UseF16c)
  52. {
  53. Debug.Assert(!Optimizations.ForceLegacySse);
  54. Operand n = GetVec(op.Rn);
  55. Operand res = context.AddIntrinsic(Intrinsic.X86Vcvtps2ph, n, Const(X86GetRoundControl(FPRoundingMode.ToNearest)));
  56. res = context.AddIntrinsic(Intrinsic.X86Pslldq, res, Const(14)); // VectorZeroUpper112()
  57. res = context.AddIntrinsic(Intrinsic.X86Psrldq, res, Const(14));
  58. context.Copy(GetVec(op.Rd), res);
  59. }
  60. else
  61. {
  62. Operand ne = context.VectorExtract(OperandType.FP32, GetVec(op.Rn), 0);
  63. context.StoreToContext();
  64. Operand res = context.Call(typeof(SoftFloat32_16).GetMethod(nameof(SoftFloat32_16.FPConvert)), ne);
  65. context.LoadFromContext();
  66. res = context.ZeroExtend16(OperandType.I64, res);
  67. context.Copy(GetVec(op.Rd), EmitVectorInsert(context, context.VectorZero(), res, 0, 1));
  68. }
  69. }
  70. else if (op.Size == 3 && op.Opc == 0) // Half -> Single.
  71. {
  72. if (Optimizations.UseF16c)
  73. {
  74. Debug.Assert(!Optimizations.ForceLegacySse);
  75. Operand res = context.AddIntrinsic(Intrinsic.X86Vcvtph2ps, GetVec(op.Rn));
  76. res = context.VectorZeroUpper96(res);
  77. context.Copy(GetVec(op.Rd), res);
  78. }
  79. else
  80. {
  81. Operand ne = EmitVectorExtractZx(context, op.Rn, 0, 1);
  82. context.StoreToContext();
  83. Operand res = context.Call(typeof(SoftFloat16_32).GetMethod(nameof(SoftFloat16_32.FPConvert)), ne);
  84. context.LoadFromContext();
  85. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  86. }
  87. }
  88. else if (op.Size == 1 && op.Opc == 3) // Double -> Half.
  89. {
  90. if (Optimizations.UseF16c)
  91. {
  92. Debug.Assert(!Optimizations.ForceLegacySse);
  93. Operand n = GetVec(op.Rn);
  94. Operand res = context.AddIntrinsic(Intrinsic.X86Cvtsd2ss, context.VectorZero(), n);
  95. res = context.AddIntrinsic(Intrinsic.X86Vcvtps2ph, res, Const(X86GetRoundControl(FPRoundingMode.ToNearest)));
  96. context.Copy(GetVec(op.Rd), res);
  97. }
  98. else
  99. {
  100. Operand ne = context.VectorExtract(OperandType.FP64, GetVec(op.Rn), 0);
  101. context.StoreToContext();
  102. Operand res = context.Call(typeof(SoftFloat64_16).GetMethod(nameof(SoftFloat64_16.FPConvert)), ne);
  103. context.LoadFromContext();
  104. res = context.ZeroExtend16(OperandType.I64, res);
  105. context.Copy(GetVec(op.Rd), EmitVectorInsert(context, context.VectorZero(), res, 0, 1));
  106. }
  107. }
  108. else if (op.Size == 3 && op.Opc == 1) // Half -> Double.
  109. {
  110. if (Optimizations.UseF16c)
  111. {
  112. Operand n = GetVec(op.Rn);
  113. Operand res = context.AddIntrinsic(Intrinsic.X86Vcvtph2ps, GetVec(op.Rn));
  114. res = context.AddIntrinsic(Intrinsic.X86Cvtss2sd, context.VectorZero(), res);
  115. res = context.VectorZeroUpper64(res);
  116. context.Copy(GetVec(op.Rd), res);
  117. }
  118. else
  119. {
  120. Operand ne = EmitVectorExtractZx(context, op.Rn, 0, 1);
  121. context.StoreToContext();
  122. Operand res = context.Call(typeof(SoftFloat16_64).GetMethod(nameof(SoftFloat16_64.FPConvert)), ne);
  123. context.LoadFromContext();
  124. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  125. }
  126. }
  127. else // Invalid encoding.
  128. {
  129. Debug.Assert(false, $"type == {op.Size} && opc == {op.Opc}");
  130. }
  131. }
  132. public static void Fcvtas_Gp(ArmEmitterContext context)
  133. {
  134. if (Optimizations.UseSse41)
  135. {
  136. EmitSse41Fcvts_Gp(context, FPRoundingMode.ToNearestAway, isFixed: false);
  137. }
  138. else
  139. {
  140. EmitFcvt_s_Gp(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1));
  141. }
  142. }
  143. public static void Fcvtas_S(ArmEmitterContext context)
  144. {
  145. if (Optimizations.UseSse41)
  146. {
  147. EmitSse41FcvtsOpF(context, FPRoundingMode.ToNearestAway, scalar: true);
  148. }
  149. else
  150. {
  151. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1), signed: true, scalar: true);
  152. }
  153. }
  154. public static void Fcvtas_V(ArmEmitterContext context)
  155. {
  156. if (Optimizations.UseSse41)
  157. {
  158. EmitSse41FcvtsOpF(context, FPRoundingMode.ToNearestAway, scalar: false);
  159. }
  160. else
  161. {
  162. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1), signed: true, scalar: false);
  163. }
  164. }
  165. public static void Fcvtau_Gp(ArmEmitterContext context)
  166. {
  167. if (Optimizations.UseSse41)
  168. {
  169. EmitSse41Fcvtu_Gp(context, FPRoundingMode.ToNearestAway, isFixed: false);
  170. }
  171. else
  172. {
  173. EmitFcvt_u_Gp(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1));
  174. }
  175. }
  176. public static void Fcvtau_S(ArmEmitterContext context)
  177. {
  178. if (Optimizations.UseSse41)
  179. {
  180. EmitSse41FcvtuOpF(context, FPRoundingMode.ToNearestAway, scalar: true);
  181. }
  182. else
  183. {
  184. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1), signed: false, scalar: true);
  185. }
  186. }
  187. public static void Fcvtau_V(ArmEmitterContext context)
  188. {
  189. if (Optimizations.UseSse41)
  190. {
  191. EmitSse41FcvtuOpF(context, FPRoundingMode.ToNearestAway, scalar: false);
  192. }
  193. else
  194. {
  195. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1), signed: false, scalar: false);
  196. }
  197. }
  198. public static void Fcvtl_V(ArmEmitterContext context)
  199. {
  200. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  201. int sizeF = op.Size & 1;
  202. if (Optimizations.UseSse2 && sizeF == 1)
  203. {
  204. Operand n = GetVec(op.Rn);
  205. Operand res = op.RegisterSize == RegisterSize.Simd128 ? context.AddIntrinsic(Intrinsic.X86Movhlps, n, n) : n;
  206. res = context.AddIntrinsic(Intrinsic.X86Cvtps2pd, res);
  207. context.Copy(GetVec(op.Rd), res);
  208. }
  209. else if (Optimizations.UseF16c && sizeF == 0)
  210. {
  211. Debug.Assert(!Optimizations.ForceLegacySse);
  212. Operand n = GetVec(op.Rn);
  213. Operand res = op.RegisterSize == RegisterSize.Simd128 ? context.AddIntrinsic(Intrinsic.X86Movhlps, n, n) : n;
  214. res = context.AddIntrinsic(Intrinsic.X86Vcvtph2ps, res);
  215. context.Copy(GetVec(op.Rd), res);
  216. }
  217. else
  218. {
  219. Operand res = context.VectorZero();
  220. int elems = 4 >> sizeF;
  221. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  222. for (int index = 0; index < elems; index++)
  223. {
  224. if (sizeF == 0)
  225. {
  226. Operand ne = EmitVectorExtractZx(context, op.Rn, part + index, 1);
  227. context.StoreToContext();
  228. Operand e = context.Call(typeof(SoftFloat16_32).GetMethod(nameof(SoftFloat16_32.FPConvert)), ne);
  229. context.LoadFromContext();
  230. res = context.VectorInsert(res, e, index);
  231. }
  232. else /* if (sizeF == 1) */
  233. {
  234. Operand ne = context.VectorExtract(OperandType.FP32, GetVec(op.Rn), part + index);
  235. Operand e = context.ConvertToFP(OperandType.FP64, ne);
  236. res = context.VectorInsert(res, e, index);
  237. }
  238. }
  239. context.Copy(GetVec(op.Rd), res);
  240. }
  241. }
  242. public static void Fcvtms_Gp(ArmEmitterContext context)
  243. {
  244. if (Optimizations.UseSse41)
  245. {
  246. EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsMinusInfinity, isFixed: false);
  247. }
  248. else
  249. {
  250. EmitFcvt_s_Gp(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Floor), op1));
  251. }
  252. }
  253. public static void Fcvtms_V(ArmEmitterContext context)
  254. {
  255. if (Optimizations.UseSse41)
  256. {
  257. EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsMinusInfinity, scalar: false);
  258. }
  259. else
  260. {
  261. EmitFcvt(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Floor), op1), signed: true, scalar: false);
  262. }
  263. }
  264. public static void Fcvtmu_Gp(ArmEmitterContext context)
  265. {
  266. if (Optimizations.UseSse41)
  267. {
  268. EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsMinusInfinity, isFixed: false);
  269. }
  270. else
  271. {
  272. EmitFcvt_u_Gp(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Floor), op1));
  273. }
  274. }
  275. public static void Fcvtn_V(ArmEmitterContext context)
  276. {
  277. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  278. int sizeF = op.Size & 1;
  279. if (Optimizations.UseSse2 && sizeF == 1)
  280. {
  281. Operand d = GetVec(op.Rd);
  282. Intrinsic movInst = op.RegisterSize == RegisterSize.Simd128 ? Intrinsic.X86Movlhps : Intrinsic.X86Movhlps;
  283. Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtpd2ps, GetVec(op.Rn));
  284. nInt = context.AddIntrinsic(Intrinsic.X86Movlhps, nInt, nInt);
  285. Operand res = context.VectorZeroUpper64(d);
  286. res = context.AddIntrinsic(movInst, res, nInt);
  287. context.Copy(d, res);
  288. }
  289. else if (Optimizations.UseF16c && sizeF == 0)
  290. {
  291. Debug.Assert(!Optimizations.ForceLegacySse);
  292. Operand d = GetVec(op.Rd);
  293. Operand n = GetVec(op.Rn);
  294. Intrinsic movInst = op.RegisterSize == RegisterSize.Simd128 ? Intrinsic.X86Movlhps : Intrinsic.X86Movhlps;
  295. Operand nInt = context.AddIntrinsic(Intrinsic.X86Vcvtps2ph, n, Const(X86GetRoundControl(FPRoundingMode.ToNearest)));
  296. nInt = context.AddIntrinsic(Intrinsic.X86Movlhps, nInt, nInt);
  297. Operand res = context.VectorZeroUpper64(d);
  298. res = context.AddIntrinsic(movInst, res, nInt);
  299. context.Copy(d, res);
  300. }
  301. else
  302. {
  303. OperandType type = sizeF == 0 ? OperandType.FP32 : OperandType.FP64;
  304. int elems = 4 >> sizeF;
  305. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  306. Operand d = GetVec(op.Rd);
  307. Operand res = part == 0 ? context.VectorZero() : context.Copy(d);
  308. for (int index = 0; index < elems; index++)
  309. {
  310. Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
  311. if (sizeF == 0)
  312. {
  313. context.StoreToContext();
  314. Operand e = context.Call(typeof(SoftFloat32_16).GetMethod(nameof(SoftFloat32_16.FPConvert)), ne);
  315. context.LoadFromContext();
  316. e = context.ZeroExtend16(OperandType.I64, e);
  317. res = EmitVectorInsert(context, res, e, part + index, 1);
  318. }
  319. else /* if (sizeF == 1) */
  320. {
  321. Operand e = context.ConvertToFP(OperandType.FP32, ne);
  322. res = context.VectorInsert(res, e, part + index);
  323. }
  324. }
  325. context.Copy(d, res);
  326. }
  327. }
  328. public static void Fcvtns_Gp(ArmEmitterContext context)
  329. {
  330. if (Optimizations.UseSse41)
  331. {
  332. EmitSse41Fcvts_Gp(context, FPRoundingMode.ToNearest, isFixed: false);
  333. }
  334. else
  335. {
  336. EmitFcvt_s_Gp(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1));
  337. }
  338. }
  339. public static void Fcvtns_S(ArmEmitterContext context)
  340. {
  341. if (Optimizations.UseSse41)
  342. {
  343. EmitSse41FcvtsOpF(context, FPRoundingMode.ToNearest, scalar: true);
  344. }
  345. else
  346. {
  347. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1), signed: true, scalar: true);
  348. }
  349. }
  350. public static void Fcvtns_V(ArmEmitterContext context)
  351. {
  352. if (Optimizations.UseSse41)
  353. {
  354. EmitSse41FcvtsOpF(context, FPRoundingMode.ToNearest, scalar: false);
  355. }
  356. else
  357. {
  358. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1), signed: true, scalar: false);
  359. }
  360. }
  361. public static void Fcvtnu_S(ArmEmitterContext context)
  362. {
  363. if (Optimizations.UseSse41)
  364. {
  365. EmitSse41FcvtuOpF(context, FPRoundingMode.ToNearest, scalar: true);
  366. }
  367. else
  368. {
  369. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1), signed: false, scalar: true);
  370. }
  371. }
  372. public static void Fcvtnu_V(ArmEmitterContext context)
  373. {
  374. if (Optimizations.UseSse41)
  375. {
  376. EmitSse41FcvtuOpF(context, FPRoundingMode.ToNearest, scalar: false);
  377. }
  378. else
  379. {
  380. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1), signed: false, scalar: false);
  381. }
  382. }
  383. public static void Fcvtps_Gp(ArmEmitterContext context)
  384. {
  385. if (Optimizations.UseSse41)
  386. {
  387. EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsPlusInfinity, isFixed: false);
  388. }
  389. else
  390. {
  391. EmitFcvt_s_Gp(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Ceiling), op1));
  392. }
  393. }
  394. public static void Fcvtpu_Gp(ArmEmitterContext context)
  395. {
  396. if (Optimizations.UseSse41)
  397. {
  398. EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsPlusInfinity, isFixed: false);
  399. }
  400. else
  401. {
  402. EmitFcvt_u_Gp(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Ceiling), op1));
  403. }
  404. }
  405. public static void Fcvtzs_Gp(ArmEmitterContext context)
  406. {
  407. if (Optimizations.UseSse41)
  408. {
  409. EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsZero, isFixed: false);
  410. }
  411. else
  412. {
  413. EmitFcvt_s_Gp(context, (op1) => op1);
  414. }
  415. }
  416. public static void Fcvtzs_Gp_Fixed(ArmEmitterContext context)
  417. {
  418. if (Optimizations.UseSse41)
  419. {
  420. EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsZero, isFixed: true);
  421. }
  422. else
  423. {
  424. EmitFcvtzs_Gp_Fixed(context);
  425. }
  426. }
  427. public static void Fcvtzs_S(ArmEmitterContext context)
  428. {
  429. if (Optimizations.UseSse41)
  430. {
  431. EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsZero, scalar: true);
  432. }
  433. else
  434. {
  435. EmitFcvtz(context, signed: true, scalar: true);
  436. }
  437. }
  438. public static void Fcvtzs_V(ArmEmitterContext context)
  439. {
  440. if (Optimizations.UseSse41)
  441. {
  442. EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsZero, scalar: false);
  443. }
  444. else
  445. {
  446. EmitFcvtz(context, signed: true, scalar: false);
  447. }
  448. }
  449. public static void Fcvtzs_V_Fixed(ArmEmitterContext context)
  450. {
  451. if (Optimizations.UseSse41)
  452. {
  453. EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsZero, scalar: false);
  454. }
  455. else
  456. {
  457. EmitFcvtz(context, signed: true, scalar: false);
  458. }
  459. }
  460. public static void Fcvtzu_Gp(ArmEmitterContext context)
  461. {
  462. if (Optimizations.UseSse41)
  463. {
  464. EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsZero, isFixed: false);
  465. }
  466. else
  467. {
  468. EmitFcvt_u_Gp(context, (op1) => op1);
  469. }
  470. }
  471. public static void Fcvtzu_Gp_Fixed(ArmEmitterContext context)
  472. {
  473. if (Optimizations.UseSse41)
  474. {
  475. EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsZero, isFixed: true);
  476. }
  477. else
  478. {
  479. EmitFcvtzu_Gp_Fixed(context);
  480. }
  481. }
  482. public static void Fcvtzu_S(ArmEmitterContext context)
  483. {
  484. if (Optimizations.UseSse41)
  485. {
  486. EmitSse41FcvtuOpF(context, FPRoundingMode.TowardsZero, scalar: true);
  487. }
  488. else
  489. {
  490. EmitFcvtz(context, signed: false, scalar: true);
  491. }
  492. }
  493. public static void Fcvtzu_V(ArmEmitterContext context)
  494. {
  495. if (Optimizations.UseSse41)
  496. {
  497. EmitSse41FcvtuOpF(context, FPRoundingMode.TowardsZero, scalar: false);
  498. }
  499. else
  500. {
  501. EmitFcvtz(context, signed: false, scalar: false);
  502. }
  503. }
  504. public static void Fcvtzu_V_Fixed(ArmEmitterContext context)
  505. {
  506. if (Optimizations.UseSse41)
  507. {
  508. EmitSse41FcvtuOpF(context, FPRoundingMode.TowardsZero, scalar: false);
  509. }
  510. else
  511. {
  512. EmitFcvtz(context, signed: false, scalar: false);
  513. }
  514. }
  515. public static void Scvtf_Gp(ArmEmitterContext context)
  516. {
  517. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  518. Operand res = GetIntOrZR(context, op.Rn);
  519. if (op.RegisterSize == RegisterSize.Int32)
  520. {
  521. res = context.SignExtend32(OperandType.I64, res);
  522. }
  523. res = EmitFPConvert(context, res, op.Size, signed: true);
  524. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  525. }
  526. public static void Scvtf_Gp_Fixed(ArmEmitterContext context)
  527. {
  528. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  529. Operand res = GetIntOrZR(context, op.Rn);
  530. if (op.RegisterSize == RegisterSize.Int32)
  531. {
  532. res = context.SignExtend32(OperandType.I64, res);
  533. }
  534. res = EmitFPConvert(context, res, op.Size, signed: true);
  535. res = EmitI2fFBitsMul(context, res, op.FBits);
  536. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  537. }
  538. public static void Scvtf_S(ArmEmitterContext context)
  539. {
  540. if (Optimizations.UseSse2)
  541. {
  542. EmitSse2ScvtfOp(context, scalar: true);
  543. }
  544. else
  545. {
  546. EmitCvtf(context, signed: true, scalar: true);
  547. }
  548. }
  549. public static void Scvtf_S_Fixed(ArmEmitterContext context)
  550. {
  551. if (Optimizations.UseSse2)
  552. {
  553. EmitSse2ScvtfOp(context, scalar: true);
  554. }
  555. else
  556. {
  557. EmitCvtf(context, signed: true, scalar: true);
  558. }
  559. }
  560. public static void Scvtf_V(ArmEmitterContext context)
  561. {
  562. if (Optimizations.UseSse2)
  563. {
  564. EmitSse2ScvtfOp(context, scalar: false);
  565. }
  566. else
  567. {
  568. EmitCvtf(context, signed: true, scalar: false);
  569. }
  570. }
  571. public static void Scvtf_V_Fixed(ArmEmitterContext context)
  572. {
  573. if (Optimizations.UseSse2)
  574. {
  575. EmitSse2ScvtfOp(context, scalar: false);
  576. }
  577. else
  578. {
  579. EmitCvtf(context, signed: true, scalar: false);
  580. }
  581. }
  582. public static void Ucvtf_Gp(ArmEmitterContext context)
  583. {
  584. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  585. Operand res = GetIntOrZR(context, op.Rn);
  586. res = EmitFPConvert(context, res, op.Size, signed: false);
  587. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  588. }
  589. public static void Ucvtf_Gp_Fixed(ArmEmitterContext context)
  590. {
  591. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  592. Operand res = GetIntOrZR(context, op.Rn);
  593. res = EmitFPConvert(context, res, op.Size, signed: false);
  594. res = EmitI2fFBitsMul(context, res, op.FBits);
  595. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  596. }
  597. public static void Ucvtf_S(ArmEmitterContext context)
  598. {
  599. if (Optimizations.UseSse2)
  600. {
  601. EmitSse2UcvtfOp(context, scalar: true);
  602. }
  603. else
  604. {
  605. EmitCvtf(context, signed: false, scalar: true);
  606. }
  607. }
  608. public static void Ucvtf_S_Fixed(ArmEmitterContext context)
  609. {
  610. if (Optimizations.UseSse2)
  611. {
  612. EmitSse2UcvtfOp(context, scalar: true);
  613. }
  614. else
  615. {
  616. EmitCvtf(context, signed: false, scalar: true);
  617. }
  618. }
  619. public static void Ucvtf_V(ArmEmitterContext context)
  620. {
  621. if (Optimizations.UseSse2)
  622. {
  623. EmitSse2UcvtfOp(context, scalar: false);
  624. }
  625. else
  626. {
  627. EmitCvtf(context, signed: false, scalar: false);
  628. }
  629. }
  630. public static void Ucvtf_V_Fixed(ArmEmitterContext context)
  631. {
  632. if (Optimizations.UseSse2)
  633. {
  634. EmitSse2UcvtfOp(context, scalar: false);
  635. }
  636. else
  637. {
  638. EmitCvtf(context, signed: false, scalar: false);
  639. }
  640. }
  641. private static void EmitFcvt(ArmEmitterContext context, Func1I emit, bool signed, bool scalar)
  642. {
  643. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  644. Operand res = context.VectorZero();
  645. Operand n = GetVec(op.Rn);
  646. int sizeF = op.Size & 1;
  647. int sizeI = sizeF + 2;
  648. OperandType type = sizeF == 0 ? OperandType.FP32 : OperandType.FP64;
  649. int elems = !scalar ? op.GetBytesCount() >> sizeI : 1;
  650. for (int index = 0; index < elems; index++)
  651. {
  652. Operand ne = context.VectorExtract(type, n, index);
  653. Operand e = emit(ne);
  654. if (sizeF == 0)
  655. {
  656. MethodInfo info = signed
  657. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS32))
  658. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU32));
  659. e = context.Call(info, e);
  660. e = context.ZeroExtend32(OperandType.I64, e);
  661. }
  662. else /* if (sizeF == 1) */
  663. {
  664. MethodInfo info = signed
  665. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS64))
  666. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU64));
  667. e = context.Call(info, e);
  668. }
  669. res = EmitVectorInsert(context, res, e, index, sizeI);
  670. }
  671. context.Copy(GetVec(op.Rd), res);
  672. }
  673. private static void EmitFcvtz(ArmEmitterContext context, bool signed, bool scalar)
  674. {
  675. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  676. Operand res = context.VectorZero();
  677. Operand n = GetVec(op.Rn);
  678. int sizeF = op.Size & 1;
  679. int sizeI = sizeF + 2;
  680. OperandType type = sizeF == 0 ? OperandType.FP32 : OperandType.FP64;
  681. int fBits = GetFBits(context);
  682. int elems = !scalar ? op.GetBytesCount() >> sizeI : 1;
  683. for (int index = 0; index < elems; index++)
  684. {
  685. Operand ne = context.VectorExtract(type, n, index);
  686. Operand e = EmitF2iFBitsMul(context, ne, fBits);
  687. if (sizeF == 0)
  688. {
  689. MethodInfo info = signed
  690. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS32))
  691. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU32));
  692. e = context.Call(info, e);
  693. e = context.ZeroExtend32(OperandType.I64, e);
  694. }
  695. else /* if (sizeF == 1) */
  696. {
  697. MethodInfo info = signed
  698. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS64))
  699. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU64));
  700. e = context.Call(info, e);
  701. }
  702. res = EmitVectorInsert(context, res, e, index, sizeI);
  703. }
  704. context.Copy(GetVec(op.Rd), res);
  705. }
  706. private static void EmitFcvt_s_Gp(ArmEmitterContext context, Func1I emit)
  707. {
  708. EmitFcvt___Gp(context, emit, signed: true);
  709. }
  710. private static void EmitFcvt_u_Gp(ArmEmitterContext context, Func1I emit)
  711. {
  712. EmitFcvt___Gp(context, emit, signed: false);
  713. }
  714. private static void EmitFcvt___Gp(ArmEmitterContext context, Func1I emit, bool signed)
  715. {
  716. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  717. OperandType type = op.Size == 0 ? OperandType.FP32 : OperandType.FP64;
  718. Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
  719. Operand res = signed
  720. ? EmitScalarFcvts(context, emit(ne), 0)
  721. : EmitScalarFcvtu(context, emit(ne), 0);
  722. SetIntOrZR(context, op.Rd, res);
  723. }
  724. private static void EmitFcvtzs_Gp_Fixed(ArmEmitterContext context)
  725. {
  726. EmitFcvtz__Gp_Fixed(context, signed: true);
  727. }
  728. private static void EmitFcvtzu_Gp_Fixed(ArmEmitterContext context)
  729. {
  730. EmitFcvtz__Gp_Fixed(context, signed: false);
  731. }
  732. private static void EmitFcvtz__Gp_Fixed(ArmEmitterContext context, bool signed)
  733. {
  734. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  735. OperandType type = op.Size == 0 ? OperandType.FP32 : OperandType.FP64;
  736. Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
  737. Operand res = signed
  738. ? EmitScalarFcvts(context, ne, op.FBits)
  739. : EmitScalarFcvtu(context, ne, op.FBits);
  740. SetIntOrZR(context, op.Rd, res);
  741. }
  742. private static void EmitCvtf(ArmEmitterContext context, bool signed, bool scalar)
  743. {
  744. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  745. Operand res = context.VectorZero();
  746. int sizeF = op.Size & 1;
  747. int sizeI = sizeF + 2;
  748. int fBits = GetFBits(context);
  749. int elems = !scalar ? op.GetBytesCount() >> sizeI : 1;
  750. for (int index = 0; index < elems; index++)
  751. {
  752. Operand ne = EmitVectorLongExtract(context, op.Rn, index, sizeI);
  753. Operand e = EmitFPConvert(context, ne, sizeF, signed);
  754. e = EmitI2fFBitsMul(context, e, fBits);
  755. res = context.VectorInsert(res, e, index);
  756. }
  757. context.Copy(GetVec(op.Rd), res);
  758. }
  759. private static int GetFBits(ArmEmitterContext context)
  760. {
  761. if (context.CurrOp is OpCodeSimdShImm op)
  762. {
  763. return GetImmShr(op);
  764. }
  765. return 0;
  766. }
  767. private static Operand EmitFPConvert(ArmEmitterContext context, Operand value, int size, bool signed)
  768. {
  769. Debug.Assert(value.Type == OperandType.I32 || value.Type == OperandType.I64);
  770. Debug.Assert((uint)size < 2);
  771. OperandType type = size == 0 ? OperandType.FP32 : OperandType.FP64;
  772. if (signed)
  773. {
  774. return context.ConvertToFP(type, value);
  775. }
  776. else
  777. {
  778. return context.ConvertToFPUI(type, value);
  779. }
  780. }
  781. private static Operand EmitScalarFcvts(ArmEmitterContext context, Operand value, int fBits)
  782. {
  783. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  784. value = EmitF2iFBitsMul(context, value, fBits);
  785. MethodInfo info;
  786. if (context.CurrOp.RegisterSize == RegisterSize.Int32)
  787. {
  788. info = value.Type == OperandType.FP32
  789. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS32))
  790. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS32));
  791. }
  792. else
  793. {
  794. info = value.Type == OperandType.FP32
  795. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS64))
  796. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS64));
  797. }
  798. return context.Call(info, value);
  799. }
  800. private static Operand EmitScalarFcvtu(ArmEmitterContext context, Operand value, int fBits)
  801. {
  802. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  803. value = EmitF2iFBitsMul(context, value, fBits);
  804. MethodInfo info;
  805. if (context.CurrOp.RegisterSize == RegisterSize.Int32)
  806. {
  807. info = value.Type == OperandType.FP32
  808. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU32))
  809. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU32));
  810. }
  811. else
  812. {
  813. info = value.Type == OperandType.FP32
  814. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU64))
  815. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU64));
  816. }
  817. return context.Call(info, value);
  818. }
  819. private static Operand EmitF2iFBitsMul(ArmEmitterContext context, Operand value, int fBits)
  820. {
  821. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  822. if (fBits == 0)
  823. {
  824. return value;
  825. }
  826. if (value.Type == OperandType.FP32)
  827. {
  828. return context.Multiply(value, ConstF(MathF.Pow(2f, fBits)));
  829. }
  830. else /* if (value.Type == OperandType.FP64) */
  831. {
  832. return context.Multiply(value, ConstF(Math.Pow(2d, fBits)));
  833. }
  834. }
  835. private static Operand EmitI2fFBitsMul(ArmEmitterContext context, Operand value, int fBits)
  836. {
  837. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  838. if (fBits == 0)
  839. {
  840. return value;
  841. }
  842. if (value.Type == OperandType.FP32)
  843. {
  844. return context.Multiply(value, ConstF(1f / MathF.Pow(2f, fBits)));
  845. }
  846. else /* if (value.Type == OperandType.FP64) */
  847. {
  848. return context.Multiply(value, ConstF(1d / Math.Pow(2d, fBits)));
  849. }
  850. }
  851. public static Operand EmitSse2CvtDoubleToInt64OpF(ArmEmitterContext context, Operand opF, bool scalar)
  852. {
  853. Debug.Assert(opF.Type == OperandType.V128);
  854. Operand longL = context.AddIntrinsicLong (Intrinsic.X86Cvtsd2si, opF); // opFL
  855. Operand res = context.VectorCreateScalar(longL);
  856. if (!scalar)
  857. {
  858. Operand opFH = context.AddIntrinsic (Intrinsic.X86Movhlps, res, opF); // res doesn't matter.
  859. Operand longH = context.AddIntrinsicLong (Intrinsic.X86Cvtsd2si, opFH);
  860. Operand resH = context.VectorCreateScalar(longH);
  861. res = context.AddIntrinsic (Intrinsic.X86Movlhps, res, resH);
  862. }
  863. return res;
  864. }
  865. private static Operand EmitSse2CvtInt64ToDoubleOp(ArmEmitterContext context, Operand op, bool scalar)
  866. {
  867. Debug.Assert(op.Type == OperandType.V128);
  868. Operand longL = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, op); // opL
  869. Operand res = context.AddIntrinsic (Intrinsic.X86Cvtsi2sd, context.VectorZero(), longL);
  870. if (!scalar)
  871. {
  872. Operand opH = context.AddIntrinsic (Intrinsic.X86Movhlps, res, op); // res doesn't matter.
  873. Operand longH = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, opH);
  874. Operand resH = context.AddIntrinsic (Intrinsic.X86Cvtsi2sd, res, longH); // res doesn't matter.
  875. res = context.AddIntrinsic (Intrinsic.X86Movlhps, res, resH);
  876. }
  877. return res;
  878. }
  879. private static void EmitSse2ScvtfOp(ArmEmitterContext context, bool scalar)
  880. {
  881. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  882. Operand n = GetVec(op.Rn);
  883. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  884. int sizeF = op.Size & 1;
  885. if (sizeF == 0)
  886. {
  887. Operand res = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, n);
  888. if (op is OpCodeSimdShImm fixedOp)
  889. {
  890. int fBits = GetImmShr(fixedOp);
  891. // BitConverter.Int32BitsToSingle(fpScaled) == 1f / MathF.Pow(2f, fBits)
  892. int fpScaled = 0x3F800000 - fBits * 0x800000;
  893. Operand fpScaledMask = scalar
  894. ? X86GetScalar (context, fpScaled)
  895. : X86GetAllElements(context, fpScaled);
  896. res = context.AddIntrinsic(Intrinsic.X86Mulps, res, fpScaledMask);
  897. }
  898. if (scalar)
  899. {
  900. res = context.VectorZeroUpper96(res);
  901. }
  902. else if (op.RegisterSize == RegisterSize.Simd64)
  903. {
  904. res = context.VectorZeroUpper64(res);
  905. }
  906. context.Copy(GetVec(op.Rd), res);
  907. }
  908. else /* if (sizeF == 1) */
  909. {
  910. Operand res = EmitSse2CvtInt64ToDoubleOp(context, n, scalar);
  911. if (op is OpCodeSimdShImm fixedOp)
  912. {
  913. int fBits = GetImmShr(fixedOp);
  914. // BitConverter.Int64BitsToDouble(fpScaled) == 1d / Math.Pow(2d, fBits)
  915. long fpScaled = 0x3FF0000000000000L - fBits * 0x10000000000000L;
  916. Operand fpScaledMask = scalar
  917. ? X86GetScalar (context, fpScaled)
  918. : X86GetAllElements(context, fpScaled);
  919. res = context.AddIntrinsic(Intrinsic.X86Mulpd, res, fpScaledMask);
  920. }
  921. if (scalar)
  922. {
  923. res = context.VectorZeroUpper64(res);
  924. }
  925. context.Copy(GetVec(op.Rd), res);
  926. }
  927. }
  928. private static void EmitSse2UcvtfOp(ArmEmitterContext context, bool scalar)
  929. {
  930. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  931. Operand n = GetVec(op.Rn);
  932. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  933. int sizeF = op.Size & 1;
  934. if (sizeF == 0)
  935. {
  936. Operand mask = scalar // 65536.000f (1 << 16)
  937. ? X86GetScalar (context, 0x47800000)
  938. : X86GetAllElements(context, 0x47800000);
  939. Operand res = context.AddIntrinsic(Intrinsic.X86Psrld, n, Const(16));
  940. res = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res);
  941. res = context.AddIntrinsic(Intrinsic.X86Mulps, res, mask);
  942. Operand res2 = context.AddIntrinsic(Intrinsic.X86Pslld, n, Const(16));
  943. res2 = context.AddIntrinsic(Intrinsic.X86Psrld, res2, Const(16));
  944. res2 = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res2);
  945. res = context.AddIntrinsic(Intrinsic.X86Addps, res, res2);
  946. if (op is OpCodeSimdShImm fixedOp)
  947. {
  948. int fBits = GetImmShr(fixedOp);
  949. // BitConverter.Int32BitsToSingle(fpScaled) == 1f / MathF.Pow(2f, fBits)
  950. int fpScaled = 0x3F800000 - fBits * 0x800000;
  951. Operand fpScaledMask = scalar
  952. ? X86GetScalar (context, fpScaled)
  953. : X86GetAllElements(context, fpScaled);
  954. res = context.AddIntrinsic(Intrinsic.X86Mulps, res, fpScaledMask);
  955. }
  956. if (scalar)
  957. {
  958. res = context.VectorZeroUpper96(res);
  959. }
  960. else if (op.RegisterSize == RegisterSize.Simd64)
  961. {
  962. res = context.VectorZeroUpper64(res);
  963. }
  964. context.Copy(GetVec(op.Rd), res);
  965. }
  966. else /* if (sizeF == 1) */
  967. {
  968. Operand mask = scalar // 4294967296.0000000d (1L << 32)
  969. ? X86GetScalar (context, 0x41F0000000000000L)
  970. : X86GetAllElements(context, 0x41F0000000000000L);
  971. Operand res = context.AddIntrinsic (Intrinsic.X86Psrlq, n, Const(32));
  972. res = EmitSse2CvtInt64ToDoubleOp(context, res, scalar);
  973. res = context.AddIntrinsic (Intrinsic.X86Mulpd, res, mask);
  974. Operand res2 = context.AddIntrinsic (Intrinsic.X86Psllq, n, Const(32));
  975. res2 = context.AddIntrinsic (Intrinsic.X86Psrlq, res2, Const(32));
  976. res2 = EmitSse2CvtInt64ToDoubleOp(context, res2, scalar);
  977. res = context.AddIntrinsic(Intrinsic.X86Addpd, res, res2);
  978. if (op is OpCodeSimdShImm fixedOp)
  979. {
  980. int fBits = GetImmShr(fixedOp);
  981. // BitConverter.Int64BitsToDouble(fpScaled) == 1d / Math.Pow(2d, fBits)
  982. long fpScaled = 0x3FF0000000000000L - fBits * 0x10000000000000L;
  983. Operand fpScaledMask = scalar
  984. ? X86GetScalar (context, fpScaled)
  985. : X86GetAllElements(context, fpScaled);
  986. res = context.AddIntrinsic(Intrinsic.X86Mulpd, res, fpScaledMask);
  987. }
  988. if (scalar)
  989. {
  990. res = context.VectorZeroUpper64(res);
  991. }
  992. context.Copy(GetVec(op.Rd), res);
  993. }
  994. }
  995. private static void EmitSse41FcvtsOpF(ArmEmitterContext context, FPRoundingMode roundMode, bool scalar)
  996. {
  997. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  998. Operand n = GetVec(op.Rn);
  999. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  1000. int sizeF = op.Size & 1;
  1001. if (sizeF == 0)
  1002. {
  1003. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, n, n, Const((int)CmpCondition.OrderedQ));
  1004. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1005. if (op is OpCodeSimdShImm fixedOp)
  1006. {
  1007. int fBits = GetImmShr(fixedOp);
  1008. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, fBits)
  1009. int fpScaled = 0x3F800000 + fBits * 0x800000;
  1010. Operand fpScaledMask = scalar
  1011. ? X86GetScalar (context, fpScaled)
  1012. : X86GetAllElements(context, fpScaled);
  1013. nRes = context.AddIntrinsic(Intrinsic.X86Mulps, nRes, fpScaledMask);
  1014. }
  1015. if (roundMode != FPRoundingMode.ToNearestAway)
  1016. {
  1017. nRes = context.AddIntrinsic(Intrinsic.X86Roundps, nRes, Const(X86GetRoundControl(roundMode)));
  1018. }
  1019. else
  1020. {
  1021. nRes = EmitSse41RoundToNearestWithTiesToAwayOpF(context, nRes, scalar);
  1022. }
  1023. Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes);
  1024. Operand fpMaxValMask = scalar // 2.14748365E9f (2147483648)
  1025. ? X86GetScalar (context, 0x4F000000)
  1026. : X86GetAllElements(context, 0x4F000000);
  1027. nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1028. Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nInt, nRes);
  1029. if (scalar)
  1030. {
  1031. dRes = context.VectorZeroUpper96(dRes);
  1032. }
  1033. else if (op.RegisterSize == RegisterSize.Simd64)
  1034. {
  1035. dRes = context.VectorZeroUpper64(dRes);
  1036. }
  1037. context.Copy(GetVec(op.Rd), dRes);
  1038. }
  1039. else /* if (sizeF == 1) */
  1040. {
  1041. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, n, n, Const((int)CmpCondition.OrderedQ));
  1042. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1043. if (op is OpCodeSimdShImm fixedOp)
  1044. {
  1045. int fBits = GetImmShr(fixedOp);
  1046. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, fBits)
  1047. long fpScaled = 0x3FF0000000000000L + fBits * 0x10000000000000L;
  1048. Operand fpScaledMask = scalar
  1049. ? X86GetScalar (context, fpScaled)
  1050. : X86GetAllElements(context, fpScaled);
  1051. nRes = context.AddIntrinsic(Intrinsic.X86Mulpd, nRes, fpScaledMask);
  1052. }
  1053. if (roundMode != FPRoundingMode.ToNearestAway)
  1054. {
  1055. nRes = context.AddIntrinsic(Intrinsic.X86Roundpd, nRes, Const(X86GetRoundControl(roundMode)));
  1056. }
  1057. else
  1058. {
  1059. nRes = EmitSse41RoundToNearestWithTiesToAwayOpF(context, nRes, scalar);
  1060. }
  1061. Operand nLong = EmitSse2CvtDoubleToInt64OpF(context, nRes, scalar);
  1062. Operand fpMaxValMask = scalar // 9.2233720368547760E18d (9223372036854775808)
  1063. ? X86GetScalar (context, 0x43E0000000000000L)
  1064. : X86GetAllElements(context, 0x43E0000000000000L);
  1065. nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1066. Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nLong, nRes);
  1067. if (scalar)
  1068. {
  1069. dRes = context.VectorZeroUpper64(dRes);
  1070. }
  1071. context.Copy(GetVec(op.Rd), dRes);
  1072. }
  1073. }
  1074. private static void EmitSse41FcvtuOpF(ArmEmitterContext context, FPRoundingMode roundMode, bool scalar)
  1075. {
  1076. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  1077. Operand n = GetVec(op.Rn);
  1078. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  1079. int sizeF = op.Size & 1;
  1080. if (sizeF == 0)
  1081. {
  1082. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, n, n, Const((int)CmpCondition.OrderedQ));
  1083. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1084. if (op is OpCodeSimdShImm fixedOp)
  1085. {
  1086. int fBits = GetImmShr(fixedOp);
  1087. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, fBits)
  1088. int fpScaled = 0x3F800000 + fBits * 0x800000;
  1089. Operand fpScaledMask = scalar
  1090. ? X86GetScalar (context, fpScaled)
  1091. : X86GetAllElements(context, fpScaled);
  1092. nRes = context.AddIntrinsic(Intrinsic.X86Mulps, nRes, fpScaledMask);
  1093. }
  1094. if (roundMode != FPRoundingMode.ToNearestAway)
  1095. {
  1096. nRes = context.AddIntrinsic(Intrinsic.X86Roundps, nRes, Const(X86GetRoundControl(roundMode)));
  1097. }
  1098. else
  1099. {
  1100. nRes = EmitSse41RoundToNearestWithTiesToAwayOpF(context, nRes, scalar);
  1101. }
  1102. Operand zero = context.VectorZero();
  1103. Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1104. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1105. Operand fpMaxValMask = scalar // 2.14748365E9f (2147483648)
  1106. ? X86GetScalar (context, 0x4F000000)
  1107. : X86GetAllElements(context, 0x4F000000);
  1108. Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes);
  1109. nRes = context.AddIntrinsic(Intrinsic.X86Subps, nRes, fpMaxValMask);
  1110. nCmp = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1111. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1112. Operand nInt2 = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes);
  1113. nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1114. Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nInt2, nRes);
  1115. dRes = context.AddIntrinsic(Intrinsic.X86Paddd, dRes, nInt);
  1116. if (scalar)
  1117. {
  1118. dRes = context.VectorZeroUpper96(dRes);
  1119. }
  1120. else if (op.RegisterSize == RegisterSize.Simd64)
  1121. {
  1122. dRes = context.VectorZeroUpper64(dRes);
  1123. }
  1124. context.Copy(GetVec(op.Rd), dRes);
  1125. }
  1126. else /* if (sizeF == 1) */
  1127. {
  1128. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, n, n, Const((int)CmpCondition.OrderedQ));
  1129. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1130. if (op is OpCodeSimdShImm fixedOp)
  1131. {
  1132. int fBits = GetImmShr(fixedOp);
  1133. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, fBits)
  1134. long fpScaled = 0x3FF0000000000000L + fBits * 0x10000000000000L;
  1135. Operand fpScaledMask = scalar
  1136. ? X86GetScalar (context, fpScaled)
  1137. : X86GetAllElements(context, fpScaled);
  1138. nRes = context.AddIntrinsic(Intrinsic.X86Mulpd, nRes, fpScaledMask);
  1139. }
  1140. if (roundMode != FPRoundingMode.ToNearestAway)
  1141. {
  1142. nRes = context.AddIntrinsic(Intrinsic.X86Roundpd, nRes, Const(X86GetRoundControl(roundMode)));
  1143. }
  1144. else
  1145. {
  1146. nRes = EmitSse41RoundToNearestWithTiesToAwayOpF(context, nRes, scalar);
  1147. }
  1148. Operand zero = context.VectorZero();
  1149. Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1150. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1151. Operand fpMaxValMask = scalar // 9.2233720368547760E18d (9223372036854775808)
  1152. ? X86GetScalar (context, 0x43E0000000000000L)
  1153. : X86GetAllElements(context, 0x43E0000000000000L);
  1154. Operand nLong = EmitSse2CvtDoubleToInt64OpF(context, nRes, scalar);
  1155. nRes = context.AddIntrinsic(Intrinsic.X86Subpd, nRes, fpMaxValMask);
  1156. nCmp = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1157. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1158. Operand nLong2 = EmitSse2CvtDoubleToInt64OpF(context, nRes, scalar);
  1159. nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1160. Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nLong2, nRes);
  1161. dRes = context.AddIntrinsic(Intrinsic.X86Paddq, dRes, nLong);
  1162. if (scalar)
  1163. {
  1164. dRes = context.VectorZeroUpper64(dRes);
  1165. }
  1166. context.Copy(GetVec(op.Rd), dRes);
  1167. }
  1168. }
  1169. private static void EmitSse41Fcvts_Gp(ArmEmitterContext context, FPRoundingMode roundMode, bool isFixed)
  1170. {
  1171. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  1172. Operand n = GetVec(op.Rn);
  1173. if (op.Size == 0)
  1174. {
  1175. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, n, n, Const((int)CmpCondition.OrderedQ));
  1176. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1177. if (isFixed)
  1178. {
  1179. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, op.FBits)
  1180. int fpScaled = 0x3F800000 + op.FBits * 0x800000;
  1181. Operand fpScaledMask = X86GetScalar(context, fpScaled);
  1182. nRes = context.AddIntrinsic(Intrinsic.X86Mulss, nRes, fpScaledMask);
  1183. }
  1184. if (roundMode != FPRoundingMode.ToNearestAway)
  1185. {
  1186. nRes = context.AddIntrinsic(Intrinsic.X86Roundss, nRes, Const(X86GetRoundControl(roundMode)));
  1187. }
  1188. else
  1189. {
  1190. nRes = EmitSse41RoundToNearestWithTiesToAwayOpF(context, nRes, scalar: true);
  1191. }
  1192. Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
  1193. ? context.AddIntrinsicInt (Intrinsic.X86Cvtss2si, nRes)
  1194. : context.AddIntrinsicLong(Intrinsic.X86Cvtss2si, nRes);
  1195. int fpMaxVal = op.RegisterSize == RegisterSize.Int32
  1196. ? 0x4F000000 // 2.14748365E9f (2147483648)
  1197. : 0x5F000000; // 9.223372E18f (9223372036854775808)
  1198. Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
  1199. nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1200. Operand nInt = context.AddIntrinsicInt(Intrinsic.X86Cvtsi2si, nRes);
  1201. if (op.RegisterSize == RegisterSize.Int64)
  1202. {
  1203. nInt = context.SignExtend32(OperandType.I64, nInt);
  1204. }
  1205. Operand dRes = context.BitwiseExclusiveOr(nIntOrLong, nInt);
  1206. SetIntOrZR(context, op.Rd, dRes);
  1207. }
  1208. else /* if (op.Size == 1) */
  1209. {
  1210. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, n, n, Const((int)CmpCondition.OrderedQ));
  1211. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1212. if (isFixed)
  1213. {
  1214. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, op.FBits)
  1215. long fpScaled = 0x3FF0000000000000L + op.FBits * 0x10000000000000L;
  1216. Operand fpScaledMask = X86GetScalar(context, fpScaled);
  1217. nRes = context.AddIntrinsic(Intrinsic.X86Mulsd, nRes, fpScaledMask);
  1218. }
  1219. if (roundMode != FPRoundingMode.ToNearestAway)
  1220. {
  1221. nRes = context.AddIntrinsic(Intrinsic.X86Roundsd, nRes, Const(X86GetRoundControl(roundMode)));
  1222. }
  1223. else
  1224. {
  1225. nRes = EmitSse41RoundToNearestWithTiesToAwayOpF(context, nRes, scalar: true);
  1226. }
  1227. Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
  1228. ? context.AddIntrinsicInt (Intrinsic.X86Cvtsd2si, nRes)
  1229. : context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRes);
  1230. long fpMaxVal = op.RegisterSize == RegisterSize.Int32
  1231. ? 0x41E0000000000000L // 2147483648.0000000d (2147483648)
  1232. : 0x43E0000000000000L; // 9.2233720368547760E18d (9223372036854775808)
  1233. Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
  1234. nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1235. Operand nLong = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, nRes);
  1236. if (op.RegisterSize == RegisterSize.Int32)
  1237. {
  1238. nLong = context.ConvertI64ToI32(nLong);
  1239. }
  1240. Operand dRes = context.BitwiseExclusiveOr(nIntOrLong, nLong);
  1241. SetIntOrZR(context, op.Rd, dRes);
  1242. }
  1243. }
  1244. private static void EmitSse41Fcvtu_Gp(ArmEmitterContext context, FPRoundingMode roundMode, bool isFixed)
  1245. {
  1246. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  1247. Operand n = GetVec(op.Rn);
  1248. if (op.Size == 0)
  1249. {
  1250. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, n, n, Const((int)CmpCondition.OrderedQ));
  1251. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1252. if (isFixed)
  1253. {
  1254. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, op.FBits)
  1255. int fpScaled = 0x3F800000 + op.FBits * 0x800000;
  1256. Operand fpScaledMask = X86GetScalar(context, fpScaled);
  1257. nRes = context.AddIntrinsic(Intrinsic.X86Mulss, nRes, fpScaledMask);
  1258. }
  1259. if (roundMode != FPRoundingMode.ToNearestAway)
  1260. {
  1261. nRes = context.AddIntrinsic(Intrinsic.X86Roundss, nRes, Const(X86GetRoundControl(roundMode)));
  1262. }
  1263. else
  1264. {
  1265. nRes = EmitSse41RoundToNearestWithTiesToAwayOpF(context, nRes, scalar: true);
  1266. }
  1267. Operand zero = context.VectorZero();
  1268. Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1269. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1270. int fpMaxVal = op.RegisterSize == RegisterSize.Int32
  1271. ? 0x4F000000 // 2.14748365E9f (2147483648)
  1272. : 0x5F000000; // 9.223372E18f (9223372036854775808)
  1273. Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
  1274. Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
  1275. ? context.AddIntrinsicInt (Intrinsic.X86Cvtss2si, nRes)
  1276. : context.AddIntrinsicLong(Intrinsic.X86Cvtss2si, nRes);
  1277. nRes = context.AddIntrinsic(Intrinsic.X86Subss, nRes, fpMaxValMask);
  1278. nCmp = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1279. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1280. Operand nIntOrLong2 = op.RegisterSize == RegisterSize.Int32
  1281. ? context.AddIntrinsicInt (Intrinsic.X86Cvtss2si, nRes)
  1282. : context.AddIntrinsicLong(Intrinsic.X86Cvtss2si, nRes);
  1283. nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1284. Operand nInt = context.AddIntrinsicInt(Intrinsic.X86Cvtsi2si, nRes);
  1285. if (op.RegisterSize == RegisterSize.Int64)
  1286. {
  1287. nInt = context.SignExtend32(OperandType.I64, nInt);
  1288. }
  1289. Operand dRes = context.BitwiseExclusiveOr(nIntOrLong2, nInt);
  1290. dRes = context.Add(dRes, nIntOrLong);
  1291. SetIntOrZR(context, op.Rd, dRes);
  1292. }
  1293. else /* if (op.Size == 1) */
  1294. {
  1295. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, n, n, Const((int)CmpCondition.OrderedQ));
  1296. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1297. if (isFixed)
  1298. {
  1299. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, op.FBits)
  1300. long fpScaled = 0x3FF0000000000000L + op.FBits * 0x10000000000000L;
  1301. Operand fpScaledMask = X86GetScalar(context, fpScaled);
  1302. nRes = context.AddIntrinsic(Intrinsic.X86Mulsd, nRes, fpScaledMask);
  1303. }
  1304. if (roundMode != FPRoundingMode.ToNearestAway)
  1305. {
  1306. nRes = context.AddIntrinsic(Intrinsic.X86Roundsd, nRes, Const(X86GetRoundControl(roundMode)));
  1307. }
  1308. else
  1309. {
  1310. nRes = EmitSse41RoundToNearestWithTiesToAwayOpF(context, nRes, scalar: true);
  1311. }
  1312. Operand zero = context.VectorZero();
  1313. Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1314. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1315. long fpMaxVal = op.RegisterSize == RegisterSize.Int32
  1316. ? 0x41E0000000000000L // 2147483648.0000000d (2147483648)
  1317. : 0x43E0000000000000L; // 9.2233720368547760E18d (9223372036854775808)
  1318. Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
  1319. Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
  1320. ? context.AddIntrinsicInt (Intrinsic.X86Cvtsd2si, nRes)
  1321. : context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRes);
  1322. nRes = context.AddIntrinsic(Intrinsic.X86Subsd, nRes, fpMaxValMask);
  1323. nCmp = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1324. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1325. Operand nIntOrLong2 = op.RegisterSize == RegisterSize.Int32
  1326. ? context.AddIntrinsicInt (Intrinsic.X86Cvtsd2si, nRes)
  1327. : context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRes);
  1328. nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1329. Operand nLong = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, nRes);
  1330. if (op.RegisterSize == RegisterSize.Int32)
  1331. {
  1332. nLong = context.ConvertI64ToI32(nLong);
  1333. }
  1334. Operand dRes = context.BitwiseExclusiveOr(nIntOrLong2, nLong);
  1335. dRes = context.Add(dRes, nIntOrLong);
  1336. SetIntOrZR(context, op.Rd, dRes);
  1337. }
  1338. }
  1339. private static Operand EmitVectorLongExtract(ArmEmitterContext context, int reg, int index, int size)
  1340. {
  1341. OperandType type = size == 3 ? OperandType.I64 : OperandType.I32;
  1342. return context.VectorExtract(type, GetVec(reg), index);
  1343. }
  1344. }
  1345. }