InstEmitSimdCvt.cs 38 KB

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  1. using ARMeilleure.Decoders;
  2. using ARMeilleure.IntermediateRepresentation;
  3. using ARMeilleure.State;
  4. using ARMeilleure.Translation;
  5. using System;
  6. using System.Diagnostics;
  7. using static ARMeilleure.Instructions.InstEmitHelper;
  8. using static ARMeilleure.Instructions.InstEmitSimdHelper;
  9. using static ARMeilleure.IntermediateRepresentation.OperandHelper;
  10. namespace ARMeilleure.Instructions
  11. {
  12. using Func1I = Func<Operand, Operand>;
  13. static partial class InstEmit
  14. {
  15. public static void Fcvt_S(ArmEmitterContext context)
  16. {
  17. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  18. if (op.Size == 0 && op.Opc == 1) // Single -> Double.
  19. {
  20. if (Optimizations.UseSse2)
  21. {
  22. Operand n = GetVec(op.Rn);
  23. Operand res = context.AddIntrinsic(Intrinsic.X86Cvtss2sd, context.VectorZero(), n);
  24. context.Copy(GetVec(op.Rd), res);
  25. }
  26. else
  27. {
  28. Operand ne = context.VectorExtract(OperandType.FP32, GetVec(op.Rn), 0);
  29. Operand res = context.ConvertToFP(OperandType.FP64, ne);
  30. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  31. }
  32. }
  33. else if (op.Size == 1 && op.Opc == 0) // Double -> Single.
  34. {
  35. if (Optimizations.UseSse2)
  36. {
  37. Operand n = GetVec(op.Rn);
  38. Operand res = context.AddIntrinsic(Intrinsic.X86Cvtsd2ss, context.VectorZero(), n);
  39. context.Copy(GetVec(op.Rd), res);
  40. }
  41. else
  42. {
  43. Operand ne = context.VectorExtract(OperandType.FP64, GetVec(op.Rn), 0);
  44. Operand res = context.ConvertToFP(OperandType.FP32, ne);
  45. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  46. }
  47. }
  48. else if (op.Size == 0 && op.Opc == 3) // Single -> Half.
  49. {
  50. Operand ne = context.VectorExtract(OperandType.FP32, GetVec(op.Rn), 0);
  51. Delegate dlg = new _U16_F32(SoftFloat32_16.FPConvert);
  52. Operand res = context.Call(dlg, ne);
  53. res = context.ZeroExtend16(OperandType.I64, res);
  54. context.Copy(GetVec(op.Rd), EmitVectorInsert(context, context.VectorZero(), res, 0, 1));
  55. }
  56. else if (op.Size == 3 && op.Opc == 0) // Half -> Single.
  57. {
  58. Operand ne = EmitVectorExtractZx(context, op.Rn, 0, 1);
  59. Delegate dlg = new _F32_U16(SoftFloat16_32.FPConvert);
  60. Operand res = context.Call(dlg, ne);
  61. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  62. }
  63. else if (op.Size == 1 && op.Opc == 3) // Double -> Half.
  64. {
  65. throw new NotImplementedException("Double-precision to half-precision.");
  66. }
  67. else if (op.Size == 3 && op.Opc == 1) // Double -> Half.
  68. {
  69. throw new NotImplementedException("Half-precision to double-precision.");
  70. }
  71. else // Invalid encoding.
  72. {
  73. Debug.Assert(false, $"type == {op.Size} && opc == {op.Opc}");
  74. }
  75. }
  76. public static void Fcvtas_Gp(ArmEmitterContext context)
  77. {
  78. EmitFcvt_s_Gp(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1));
  79. }
  80. public static void Fcvtau_Gp(ArmEmitterContext context)
  81. {
  82. EmitFcvt_u_Gp(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1));
  83. }
  84. public static void Fcvtl_V(ArmEmitterContext context)
  85. {
  86. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  87. int sizeF = op.Size & 1;
  88. if (Optimizations.UseSse2 && sizeF == 1)
  89. {
  90. Operand n = GetVec(op.Rn);
  91. Operand res;
  92. if (op.RegisterSize == RegisterSize.Simd128)
  93. {
  94. res = context.AddIntrinsic(Intrinsic.X86Movhlps, n, n);
  95. }
  96. else
  97. {
  98. res = n;
  99. }
  100. res = context.AddIntrinsic(Intrinsic.X86Cvtps2pd, res);
  101. context.Copy(GetVec(op.Rd), res);
  102. }
  103. else
  104. {
  105. Operand res = context.VectorZero();
  106. int elems = 4 >> sizeF;
  107. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  108. for (int index = 0; index < elems; index++)
  109. {
  110. if (sizeF == 0)
  111. {
  112. Operand ne = EmitVectorExtractZx(context, op.Rn, part + index, 1);
  113. Delegate dlg = new _F32_U16(SoftFloat16_32.FPConvert);
  114. Operand e = context.Call(dlg, ne);
  115. res = context.VectorInsert(res, e, index);
  116. }
  117. else /* if (sizeF == 1) */
  118. {
  119. Operand ne = context.VectorExtract(OperandType.FP32, GetVec(op.Rn), part + index);
  120. Operand e = context.ConvertToFP(OperandType.FP64, ne);
  121. res = context.VectorInsert(res, e, index);
  122. }
  123. }
  124. context.Copy(GetVec(op.Rd), res);
  125. }
  126. }
  127. public static void Fcvtms_Gp(ArmEmitterContext context)
  128. {
  129. EmitFcvt_s_Gp(context, (op1) => EmitUnaryMathCall(context, MathF.Floor, Math.Floor, op1));
  130. }
  131. public static void Fcvtmu_Gp(ArmEmitterContext context)
  132. {
  133. EmitFcvt_u_Gp(context, (op1) => EmitUnaryMathCall(context, MathF.Floor, Math.Floor, op1));
  134. }
  135. public static void Fcvtn_V(ArmEmitterContext context)
  136. {
  137. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  138. int sizeF = op.Size & 1;
  139. if (Optimizations.UseSse2 && sizeF == 1)
  140. {
  141. Operand d = GetVec(op.Rd);
  142. Operand n = GetVec(op.Rn);
  143. Operand res = context.AddIntrinsic(Intrinsic.X86Movlhps, d, context.VectorZero());
  144. Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtpd2ps, n);
  145. nInt = context.AddIntrinsic(Intrinsic.X86Movlhps, nInt, nInt);
  146. Intrinsic movInst = op.RegisterSize == RegisterSize.Simd128
  147. ? Intrinsic.X86Movlhps
  148. : Intrinsic.X86Movhlps;
  149. res = context.AddIntrinsic(movInst, res, nInt);
  150. context.Copy(GetVec(op.Rd), res);
  151. }
  152. else
  153. {
  154. OperandType type = sizeF == 0 ? OperandType.FP32 : OperandType.FP64;
  155. int elems = 4 >> sizeF;
  156. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  157. Operand res = part == 0 ? context.VectorZero() : context.Copy(GetVec(op.Rd));
  158. for (int index = 0; index < elems; index++)
  159. {
  160. Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
  161. if (sizeF == 0)
  162. {
  163. Delegate dlg = new _U16_F32(SoftFloat32_16.FPConvert);
  164. Operand e = context.Call(dlg, ne);
  165. e = context.ZeroExtend16(OperandType.I64, e);
  166. res = EmitVectorInsert(context, res, e, part + index, 1);
  167. }
  168. else /* if (sizeF == 1) */
  169. {
  170. Operand e = context.ConvertToFP(OperandType.FP32, ne);
  171. res = context.VectorInsert(res, e, part + index);
  172. }
  173. }
  174. context.Copy(GetVec(op.Rd), res);
  175. }
  176. }
  177. public static void Fcvtns_S(ArmEmitterContext context)
  178. {
  179. if (Optimizations.UseSse41)
  180. {
  181. EmitSse41Fcvts(context, FPRoundingMode.ToNearest, scalar: true);
  182. }
  183. else
  184. {
  185. EmitFcvtn(context, signed: true, scalar: true);
  186. }
  187. }
  188. public static void Fcvtns_V(ArmEmitterContext context)
  189. {
  190. if (Optimizations.UseSse41)
  191. {
  192. EmitSse41Fcvts(context, FPRoundingMode.ToNearest, scalar: false);
  193. }
  194. else
  195. {
  196. EmitFcvtn(context, signed: true, scalar: false);
  197. }
  198. }
  199. public static void Fcvtnu_S(ArmEmitterContext context)
  200. {
  201. if (Optimizations.UseSse41)
  202. {
  203. EmitSse41Fcvtu(context, FPRoundingMode.ToNearest, scalar: true);
  204. }
  205. else
  206. {
  207. EmitFcvtn(context, signed: false, scalar: true);
  208. }
  209. }
  210. public static void Fcvtnu_V(ArmEmitterContext context)
  211. {
  212. if (Optimizations.UseSse41)
  213. {
  214. EmitSse41Fcvtu(context, FPRoundingMode.ToNearest, scalar: false);
  215. }
  216. else
  217. {
  218. EmitFcvtn(context, signed: false, scalar: false);
  219. }
  220. }
  221. public static void Fcvtps_Gp(ArmEmitterContext context)
  222. {
  223. EmitFcvt_s_Gp(context, (op1) => EmitUnaryMathCall(context, MathF.Ceiling, Math.Ceiling, op1));
  224. }
  225. public static void Fcvtpu_Gp(ArmEmitterContext context)
  226. {
  227. EmitFcvt_u_Gp(context, (op1) => EmitUnaryMathCall(context, MathF.Ceiling, Math.Ceiling, op1));
  228. }
  229. public static void Fcvtzs_Gp(ArmEmitterContext context)
  230. {
  231. EmitFcvt_s_Gp(context, (op1) => op1);
  232. }
  233. public static void Fcvtzs_Gp_Fixed(ArmEmitterContext context)
  234. {
  235. EmitFcvtzs_Gp_Fixed(context);
  236. }
  237. public static void Fcvtzs_S(ArmEmitterContext context)
  238. {
  239. if (Optimizations.UseSse41)
  240. {
  241. EmitSse41Fcvts(context, FPRoundingMode.TowardsZero, scalar: true);
  242. }
  243. else
  244. {
  245. EmitFcvtz(context, signed: true, scalar: true);
  246. }
  247. }
  248. public static void Fcvtzs_V(ArmEmitterContext context)
  249. {
  250. if (Optimizations.UseSse41)
  251. {
  252. EmitSse41Fcvts(context, FPRoundingMode.TowardsZero, scalar: false);
  253. }
  254. else
  255. {
  256. EmitFcvtz(context, signed: true, scalar: false);
  257. }
  258. }
  259. public static void Fcvtzs_V_Fixed(ArmEmitterContext context)
  260. {
  261. if (Optimizations.UseSse41)
  262. {
  263. EmitSse41Fcvts(context, FPRoundingMode.TowardsZero, scalar: false);
  264. }
  265. else
  266. {
  267. EmitFcvtz(context, signed: true, scalar: false);
  268. }
  269. }
  270. public static void Fcvtzu_Gp(ArmEmitterContext context)
  271. {
  272. EmitFcvt_u_Gp(context, (op1) => op1);
  273. }
  274. public static void Fcvtzu_Gp_Fixed(ArmEmitterContext context)
  275. {
  276. EmitFcvtzu_Gp_Fixed(context);
  277. }
  278. public static void Fcvtzu_S(ArmEmitterContext context)
  279. {
  280. if (Optimizations.UseSse41)
  281. {
  282. EmitSse41Fcvtu(context, FPRoundingMode.TowardsZero, scalar: true);
  283. }
  284. else
  285. {
  286. EmitFcvtz(context, signed: false, scalar: true);
  287. }
  288. }
  289. public static void Fcvtzu_V(ArmEmitterContext context)
  290. {
  291. if (Optimizations.UseSse41)
  292. {
  293. EmitSse41Fcvtu(context, FPRoundingMode.TowardsZero, scalar: false);
  294. }
  295. else
  296. {
  297. EmitFcvtz(context, signed: false, scalar: false);
  298. }
  299. }
  300. public static void Fcvtzu_V_Fixed(ArmEmitterContext context)
  301. {
  302. if (Optimizations.UseSse41)
  303. {
  304. EmitSse41Fcvtu(context, FPRoundingMode.TowardsZero, scalar: false);
  305. }
  306. else
  307. {
  308. EmitFcvtz(context, signed: false, scalar: false);
  309. }
  310. }
  311. public static void Scvtf_Gp(ArmEmitterContext context)
  312. {
  313. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  314. Operand res = GetIntOrZR(context, op.Rn);
  315. if (op.RegisterSize == RegisterSize.Int32)
  316. {
  317. res = context.SignExtend32(OperandType.I64, res);
  318. }
  319. res = EmitFPConvert(context, res, op.Size, signed: true);
  320. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  321. }
  322. public static void Scvtf_Gp_Fixed(ArmEmitterContext context)
  323. {
  324. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  325. Operand res = GetIntOrZR(context, op.Rn);
  326. if (op.RegisterSize == RegisterSize.Int32)
  327. {
  328. res = context.SignExtend32(OperandType.I64, res);
  329. }
  330. res = EmitFPConvert(context, res, op.Size, signed: true);
  331. res = EmitI2fFBitsMul(context, res, op.FBits);
  332. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  333. }
  334. public static void Scvtf_S(ArmEmitterContext context)
  335. {
  336. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  337. int sizeF = op.Size & 1;
  338. if (Optimizations.UseSse2 && sizeF == 0)
  339. {
  340. EmitSse2Scvtf(context, scalar: true);
  341. }
  342. else
  343. {
  344. Operand res = EmitVectorLongExtract(context, op.Rn, 0, sizeF + 2);
  345. res = EmitFPConvert(context, res, op.Size, signed: true);
  346. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  347. }
  348. }
  349. public static void Scvtf_V(ArmEmitterContext context)
  350. {
  351. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  352. int sizeF = op.Size & 1;
  353. if (Optimizations.UseSse2 && sizeF == 0)
  354. {
  355. EmitSse2Scvtf(context, scalar: false);
  356. }
  357. else
  358. {
  359. EmitVectorCvtf(context, signed: true);
  360. }
  361. }
  362. public static void Scvtf_V_Fixed(ArmEmitterContext context)
  363. {
  364. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  365. // sizeF == ((OpCodeSimdShImm64)op).Size - 2
  366. int sizeF = op.Size & 1;
  367. if (Optimizations.UseSse2 && sizeF == 0)
  368. {
  369. EmitSse2Scvtf(context, scalar: false);
  370. }
  371. else
  372. {
  373. EmitVectorCvtf(context, signed: true);
  374. }
  375. }
  376. public static void Ucvtf_Gp(ArmEmitterContext context)
  377. {
  378. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  379. Operand res = GetIntOrZR(context, op.Rn);
  380. res = EmitFPConvert(context, res, op.Size, signed: false);
  381. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  382. }
  383. public static void Ucvtf_Gp_Fixed(ArmEmitterContext context)
  384. {
  385. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  386. Operand res = GetIntOrZR(context, op.Rn);
  387. res = EmitFPConvert(context, res, op.Size, signed: false);
  388. res = EmitI2fFBitsMul(context, res, op.FBits);
  389. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  390. }
  391. public static void Ucvtf_S(ArmEmitterContext context)
  392. {
  393. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  394. int sizeF = op.Size & 1;
  395. if (Optimizations.UseSse2 && sizeF == 0)
  396. {
  397. EmitSse2Ucvtf(context, scalar: true);
  398. }
  399. else
  400. {
  401. Operand ne = EmitVectorLongExtract(context, op.Rn, 0, sizeF + 2);
  402. Operand res = EmitFPConvert(context, ne, sizeF, signed: false);
  403. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  404. }
  405. }
  406. public static void Ucvtf_V(ArmEmitterContext context)
  407. {
  408. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  409. int sizeF = op.Size & 1;
  410. if (Optimizations.UseSse2 && sizeF == 0)
  411. {
  412. EmitSse2Ucvtf(context, scalar: false);
  413. }
  414. else
  415. {
  416. EmitVectorCvtf(context, signed: false);
  417. }
  418. }
  419. public static void Ucvtf_V_Fixed(ArmEmitterContext context)
  420. {
  421. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  422. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  423. int sizeF = op.Size & 1;
  424. if (Optimizations.UseSse2 && sizeF == 0)
  425. {
  426. EmitSse2Ucvtf(context, scalar: false);
  427. }
  428. else
  429. {
  430. EmitVectorCvtf(context, signed: false);
  431. }
  432. }
  433. private static void EmitFcvtn(ArmEmitterContext context, bool signed, bool scalar)
  434. {
  435. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  436. Operand res = context.VectorZero();
  437. Operand n = GetVec(op.Rn);
  438. int sizeF = op.Size & 1;
  439. int sizeI = sizeF + 2;
  440. OperandType type = sizeF == 0 ? OperandType.FP32 : OperandType.FP64;
  441. int elems = !scalar ? op.GetBytesCount() >> sizeI : 1;
  442. for (int index = 0; index < elems; index++)
  443. {
  444. Operand ne = context.VectorExtract(type, n, index);
  445. Operand e = EmitRoundMathCall(context, MidpointRounding.ToEven, ne);
  446. if (sizeF == 0)
  447. {
  448. Delegate dlg = signed
  449. ? (Delegate)new _S32_F32(SoftFallback.SatF32ToS32)
  450. : (Delegate)new _U32_F32(SoftFallback.SatF32ToU32);
  451. e = context.Call(dlg, e);
  452. e = context.ZeroExtend32(OperandType.I64, e);
  453. }
  454. else /* if (sizeF == 1) */
  455. {
  456. Delegate dlg = signed
  457. ? (Delegate)new _S64_F64(SoftFallback.SatF64ToS64)
  458. : (Delegate)new _U64_F64(SoftFallback.SatF64ToU64);
  459. e = context.Call(dlg, e);
  460. }
  461. res = EmitVectorInsert(context, res, e, index, sizeI);
  462. }
  463. context.Copy(GetVec(op.Rd), res);
  464. }
  465. private static void EmitFcvtz(ArmEmitterContext context, bool signed, bool scalar)
  466. {
  467. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  468. Operand res = context.VectorZero();
  469. Operand n = GetVec(op.Rn);
  470. int sizeF = op.Size & 1;
  471. int sizeI = sizeF + 2;
  472. OperandType type = sizeF == 0 ? OperandType.FP32 : OperandType.FP64;
  473. int fBits = GetFBits(context);
  474. int elems = !scalar ? op.GetBytesCount() >> sizeI : 1;
  475. for (int index = 0; index < elems; index++)
  476. {
  477. Operand ne = context.VectorExtract(type, n, index);
  478. Operand e = EmitF2iFBitsMul(context, ne, fBits);
  479. if (sizeF == 0)
  480. {
  481. Delegate dlg = signed
  482. ? (Delegate)new _S32_F32(SoftFallback.SatF32ToS32)
  483. : (Delegate)new _U32_F32(SoftFallback.SatF32ToU32);
  484. e = context.Call(dlg, e);
  485. e = context.ZeroExtend32(OperandType.I64, e);
  486. }
  487. else /* if (sizeF == 1) */
  488. {
  489. Delegate dlg = signed
  490. ? (Delegate)new _S64_F64(SoftFallback.SatF64ToS64)
  491. : (Delegate)new _U64_F64(SoftFallback.SatF64ToU64);
  492. e = context.Call(dlg, e);
  493. }
  494. res = EmitVectorInsert(context, res, e, index, sizeI);
  495. }
  496. context.Copy(GetVec(op.Rd), res);
  497. }
  498. private static void EmitFcvt_s_Gp(ArmEmitterContext context, Func1I emit)
  499. {
  500. EmitFcvt___Gp(context, emit, signed: true);
  501. }
  502. private static void EmitFcvt_u_Gp(ArmEmitterContext context, Func1I emit)
  503. {
  504. EmitFcvt___Gp(context, emit, signed: false);
  505. }
  506. private static void EmitFcvt___Gp(ArmEmitterContext context, Func1I emit, bool signed)
  507. {
  508. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  509. OperandType type = op.Size == 0 ? OperandType.FP32 : OperandType.FP64;
  510. Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
  511. Operand res = signed
  512. ? EmitScalarFcvts(context, emit(ne), 0)
  513. : EmitScalarFcvtu(context, emit(ne), 0);
  514. SetIntOrZR(context, op.Rd, res);
  515. }
  516. private static void EmitFcvtzs_Gp_Fixed(ArmEmitterContext context)
  517. {
  518. EmitFcvtz__Gp_Fixed(context, signed: true);
  519. }
  520. private static void EmitFcvtzu_Gp_Fixed(ArmEmitterContext context)
  521. {
  522. EmitFcvtz__Gp_Fixed(context, signed: false);
  523. }
  524. private static void EmitFcvtz__Gp_Fixed(ArmEmitterContext context, bool signed)
  525. {
  526. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  527. OperandType type = op.Size == 0 ? OperandType.FP32 : OperandType.FP64;
  528. Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
  529. Operand res = signed
  530. ? EmitScalarFcvts(context, ne, op.FBits)
  531. : EmitScalarFcvtu(context, ne, op.FBits);
  532. SetIntOrZR(context, op.Rd, res);
  533. }
  534. private static void EmitVectorCvtf(ArmEmitterContext context, bool signed)
  535. {
  536. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  537. Operand res = context.VectorZero();
  538. int sizeF = op.Size & 1;
  539. int sizeI = sizeF + 2;
  540. int fBits = GetFBits(context);
  541. int elems = op.GetBytesCount() >> sizeI;
  542. for (int index = 0; index < elems; index++)
  543. {
  544. Operand ne = EmitVectorLongExtract(context, op.Rn, index, sizeI);
  545. Operand e = EmitFPConvert(context, ne, sizeF, signed);
  546. e = EmitI2fFBitsMul(context, e, fBits);
  547. res = context.VectorInsert(res, e, index);
  548. }
  549. context.Copy(GetVec(op.Rd), res);
  550. }
  551. private static int GetFBits(ArmEmitterContext context)
  552. {
  553. if (context.CurrOp is OpCodeSimdShImm op)
  554. {
  555. return GetImmShr(op);
  556. }
  557. return 0;
  558. }
  559. private static Operand EmitFPConvert(ArmEmitterContext context, Operand value, int size, bool signed)
  560. {
  561. Debug.Assert(value.Type == OperandType.I32 || value.Type == OperandType.I64);
  562. Debug.Assert((uint)size < 2);
  563. OperandType type = size == 0 ? OperandType.FP32
  564. : OperandType.FP64;
  565. if (signed)
  566. {
  567. return context.ConvertToFP(type, value);
  568. }
  569. else
  570. {
  571. return context.ConvertToFPUI(type, value);
  572. }
  573. }
  574. private static Operand EmitScalarFcvts(ArmEmitterContext context, Operand value, int fBits)
  575. {
  576. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  577. value = EmitF2iFBitsMul(context, value, fBits);
  578. if (context.CurrOp.RegisterSize == RegisterSize.Int32)
  579. {
  580. Delegate dlg = value.Type == OperandType.FP32
  581. ? (Delegate)new _S32_F32(SoftFallback.SatF32ToS32)
  582. : (Delegate)new _S32_F64(SoftFallback.SatF64ToS32);
  583. return context.Call(dlg, value);
  584. }
  585. else
  586. {
  587. Delegate dlg = value.Type == OperandType.FP32
  588. ? (Delegate)new _S64_F32(SoftFallback.SatF32ToS64)
  589. : (Delegate)new _S64_F64(SoftFallback.SatF64ToS64);
  590. return context.Call(dlg, value);
  591. }
  592. }
  593. private static Operand EmitScalarFcvtu(ArmEmitterContext context, Operand value, int fBits)
  594. {
  595. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  596. value = EmitF2iFBitsMul(context, value, fBits);
  597. if (context.CurrOp.RegisterSize == RegisterSize.Int32)
  598. {
  599. Delegate dlg = value.Type == OperandType.FP32
  600. ? (Delegate)new _U32_F32(SoftFallback.SatF32ToU32)
  601. : (Delegate)new _U32_F64(SoftFallback.SatF64ToU32);
  602. return context.Call(dlg, value);
  603. }
  604. else
  605. {
  606. Delegate dlg = value.Type == OperandType.FP32
  607. ? (Delegate)new _U64_F32(SoftFallback.SatF32ToU64)
  608. : (Delegate)new _U64_F64(SoftFallback.SatF64ToU64);
  609. return context.Call(dlg, value);
  610. }
  611. }
  612. private static Operand EmitF2iFBitsMul(ArmEmitterContext context, Operand value, int fBits)
  613. {
  614. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  615. if (fBits == 0)
  616. {
  617. return value;
  618. }
  619. if (value.Type == OperandType.FP32)
  620. {
  621. return context.Multiply(value, ConstF(MathF.Pow(2f, fBits)));
  622. }
  623. else /* if (value.Type == OperandType.FP64) */
  624. {
  625. return context.Multiply(value, ConstF(Math.Pow(2d, fBits)));
  626. }
  627. }
  628. private static Operand EmitI2fFBitsMul(ArmEmitterContext context, Operand value, int fBits)
  629. {
  630. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  631. if (fBits == 0)
  632. {
  633. return value;
  634. }
  635. if (value.Type == OperandType.FP32)
  636. {
  637. return context.Multiply(value, ConstF(1f / MathF.Pow(2f, fBits)));
  638. }
  639. else /* if (value.Type == OperandType.FP64) */
  640. {
  641. return context.Multiply(value, ConstF(1d / Math.Pow(2d, fBits)));
  642. }
  643. }
  644. private static void EmitSse41Fcvts(ArmEmitterContext context, FPRoundingMode roundMode, bool scalar)
  645. {
  646. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  647. Operand n = GetVec(op.Rn);
  648. const int cmpGreaterThanOrEqual = 5;
  649. const int cmpOrdered = 7;
  650. // sizeF == ((OpCodeSimdShImm64)op).Size - 2
  651. int sizeF = op.Size & 1;
  652. if (sizeF == 0)
  653. {
  654. Operand nMask = context.AddIntrinsic(Intrinsic.X86Cmpps, n, n, Const(cmpOrdered));
  655. Operand nScaled = context.AddIntrinsic(Intrinsic.X86Pand, nMask, n);
  656. if (op is OpCodeSimdShImm fixedOp)
  657. {
  658. int fBits = GetImmShr(fixedOp);
  659. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, fBits)
  660. int fpScaled = 0x3F800000 + fBits * 0x800000;
  661. Operand scale = X86GetAllElements(context, fpScaled);
  662. nScaled = context.AddIntrinsic(Intrinsic.X86Mulps, nScaled, scale);
  663. }
  664. Operand nRnd = context.AddIntrinsic(Intrinsic.X86Roundps, nScaled, Const(X86GetRoundControl(roundMode)));
  665. Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRnd);
  666. Operand mask = X86GetAllElements(context, 0x4F000000); // 2.14748365E9f (2147483648)
  667. Operand mask2 = context.AddIntrinsic(Intrinsic.X86Cmpps, nRnd, mask, Const(cmpGreaterThanOrEqual));
  668. Operand res = context.AddIntrinsic(Intrinsic.X86Pxor, nInt, mask2);
  669. if (scalar)
  670. {
  671. res = context.VectorZeroUpper96(res);
  672. }
  673. else if (op.RegisterSize == RegisterSize.Simd64)
  674. {
  675. res = context.VectorZeroUpper64(res);
  676. }
  677. context.Copy(GetVec(op.Rd), res);
  678. }
  679. else /* if (sizeF == 1) */
  680. {
  681. Operand nMask = context.AddIntrinsic(Intrinsic.X86Cmppd, n, n, Const(cmpOrdered));
  682. Operand nScaled = context.AddIntrinsic(Intrinsic.X86Pand, nMask, n);
  683. if (op is OpCodeSimdShImm fixedOp)
  684. {
  685. int fBits = GetImmShr(fixedOp);
  686. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, fBits)
  687. long fpScaled = 0x3FF0000000000000L + fBits * 0x10000000000000L;
  688. Operand scale = X86GetAllElements(context, fpScaled);
  689. nScaled = context.AddIntrinsic(Intrinsic.X86Mulpd, nScaled, scale);
  690. }
  691. Operand nRnd = context.AddIntrinsic(Intrinsic.X86Roundpd, nScaled, Const(X86GetRoundControl(roundMode)));
  692. Operand high;
  693. if (!scalar)
  694. {
  695. high = context.AddIntrinsic(Intrinsic.X86Unpckhpd, nRnd, nRnd);
  696. high = context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, high);
  697. }
  698. else
  699. {
  700. high = Const(0L);
  701. }
  702. Operand low = context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRnd);
  703. Operand nInt = EmitVectorLongCreate(context, low, high);
  704. Operand mask = X86GetAllElements(context, 0x43E0000000000000L); // 9.2233720368547760E18d (9223372036854775808)
  705. Operand mask2 = context.AddIntrinsic(Intrinsic.X86Cmppd, nRnd, mask, Const(cmpGreaterThanOrEqual));
  706. Operand res = context.AddIntrinsic(Intrinsic.X86Pxor, nInt, mask2);
  707. if (scalar)
  708. {
  709. res = context.VectorZeroUpper64(res);
  710. }
  711. context.Copy(GetVec(op.Rd), res);
  712. }
  713. }
  714. private static void EmitSse41Fcvtu(ArmEmitterContext context, FPRoundingMode roundMode, bool scalar)
  715. {
  716. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  717. Operand n = GetVec(op.Rn);
  718. const int cmpGreaterThanOrEqual = 5;
  719. const int cmpGreaterThan = 6;
  720. const int cmpOrdered = 7;
  721. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  722. int sizeF = op.Size & 1;
  723. if (sizeF == 0)
  724. {
  725. Operand nMask = context.AddIntrinsic(Intrinsic.X86Cmpps, n, n, Const(cmpOrdered));
  726. Operand nScaled = context.AddIntrinsic(Intrinsic.X86Pand, nMask, n);
  727. if (op is OpCodeSimdShImm fixedOp)
  728. {
  729. int fBits = GetImmShr(fixedOp);
  730. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, fBits)
  731. int fpScaled = 0x3F800000 + fBits * 0x800000;
  732. Operand scale = X86GetAllElements(context, fpScaled);
  733. nScaled = context.AddIntrinsic(Intrinsic.X86Mulps, nScaled, scale);
  734. }
  735. Operand nRnd = context.AddIntrinsic(Intrinsic.X86Roundps, nScaled, Const(X86GetRoundControl(roundMode)));
  736. Operand nRndMask = context.AddIntrinsic(Intrinsic.X86Cmpps, nRnd, context.VectorZero(), Const(cmpGreaterThan));
  737. Operand nRndMasked = context.AddIntrinsic(Intrinsic.X86Pand, nRnd, nRndMask);
  738. Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRndMasked);
  739. Operand mask = X86GetAllElements(context, 0x4F000000); // 2.14748365E9f (2147483648)
  740. Operand res = context.AddIntrinsic(Intrinsic.X86Subps, nRndMasked, mask);
  741. Operand mask2 = context.AddIntrinsic(Intrinsic.X86Cmpps, res, context.VectorZero(), Const(cmpGreaterThan));
  742. Operand resMasked = context.AddIntrinsic(Intrinsic.X86Pand, res, mask2);
  743. res = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, resMasked);
  744. Operand mask3 = context.AddIntrinsic(Intrinsic.X86Cmpps, resMasked, mask, Const(cmpGreaterThanOrEqual));
  745. res = context.AddIntrinsic(Intrinsic.X86Pxor, res, mask3);
  746. res = context.AddIntrinsic(Intrinsic.X86Paddd, res, nInt);
  747. if (scalar)
  748. {
  749. res = context.VectorZeroUpper96(res);
  750. }
  751. else if (op.RegisterSize == RegisterSize.Simd64)
  752. {
  753. res = context.VectorZeroUpper64(res);
  754. }
  755. context.Copy(GetVec(op.Rd), res);
  756. }
  757. else /* if (sizeF == 1) */
  758. {
  759. Operand nMask = context.AddIntrinsic(Intrinsic.X86Cmppd, n, n, Const(cmpOrdered));
  760. Operand nScaled = context.AddIntrinsic(Intrinsic.X86Pand, nMask, n);
  761. if (op is OpCodeSimdShImm fixedOp)
  762. {
  763. int fBits = GetImmShr(fixedOp);
  764. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, fBits)
  765. long fpScaled = 0x3FF0000000000000L + fBits * 0x10000000000000L;
  766. Operand scale = X86GetAllElements(context, fpScaled);
  767. nScaled = context.AddIntrinsic(Intrinsic.X86Mulpd, nScaled, scale);
  768. }
  769. Operand nRnd = context.AddIntrinsic(Intrinsic.X86Roundpd, nScaled, Const(X86GetRoundControl(roundMode)));
  770. Operand nRndMask = context.AddIntrinsic(Intrinsic.X86Cmppd, nRnd, context.VectorZero(), Const(cmpGreaterThan));
  771. Operand nRndMasked = context.AddIntrinsic(Intrinsic.X86Pand, nRnd, nRndMask);
  772. Operand high;
  773. if (!scalar)
  774. {
  775. high = context.AddIntrinsic(Intrinsic.X86Unpckhpd, nRndMasked, nRndMasked);
  776. high = context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, high);
  777. }
  778. else
  779. {
  780. high = Const(0L);
  781. }
  782. Operand low = context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRndMasked);
  783. Operand nInt = EmitVectorLongCreate(context, low, high);
  784. Operand mask = X86GetAllElements(context, 0x43E0000000000000L); // 9.2233720368547760E18d (9223372036854775808)
  785. Operand res = context.AddIntrinsic(Intrinsic.X86Subpd, nRndMasked, mask);
  786. Operand mask2 = context.AddIntrinsic(Intrinsic.X86Cmppd, res, context.VectorZero(), Const(cmpGreaterThan));
  787. Operand resMasked = context.AddIntrinsic(Intrinsic.X86Pand, res, mask2);
  788. if (!scalar)
  789. {
  790. high = context.AddIntrinsic(Intrinsic.X86Unpckhpd, resMasked, resMasked);
  791. high = context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, high);
  792. }
  793. low = context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, resMasked);
  794. res = EmitVectorLongCreate(context, low, high);
  795. Operand mask3 = context.AddIntrinsic(Intrinsic.X86Cmppd, resMasked, mask, Const(cmpGreaterThanOrEqual));
  796. res = context.AddIntrinsic(Intrinsic.X86Pxor, res, mask3);
  797. res = context.AddIntrinsic(Intrinsic.X86Paddq, res, nInt);
  798. if (scalar)
  799. {
  800. res = context.VectorZeroUpper64(res);
  801. }
  802. context.Copy(GetVec(op.Rd), res);
  803. }
  804. }
  805. private static void EmitSse2Scvtf(ArmEmitterContext context, bool scalar)
  806. {
  807. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  808. Operand n = GetVec(op.Rn);
  809. Operand res = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, n);
  810. if (op is OpCodeSimdShImm fixedOp)
  811. {
  812. int fBits = GetImmShr(fixedOp);
  813. // BitConverter.Int32BitsToSingle(fpScaled) == 1f / MathF.Pow(2f, fBits)
  814. int fpScaled = 0x3F800000 - fBits * 0x800000;
  815. Operand scale = X86GetAllElements(context, fpScaled);
  816. res = context.AddIntrinsic(Intrinsic.X86Mulps, res, scale);
  817. }
  818. if (scalar)
  819. {
  820. res = context.VectorZeroUpper96(res);
  821. }
  822. else if (op.RegisterSize == RegisterSize.Simd64)
  823. {
  824. res = context.VectorZeroUpper64(res);
  825. }
  826. context.Copy(GetVec(op.Rd), res);
  827. }
  828. private static void EmitSse2Ucvtf(ArmEmitterContext context, bool scalar)
  829. {
  830. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  831. Operand n = GetVec(op.Rn);
  832. Operand res = context.AddIntrinsic(Intrinsic.X86Psrld, n, Const(16));
  833. res = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res);
  834. Operand mask = X86GetAllElements(context, 0x47800000); // 65536.0f (1 << 16)
  835. res = context.AddIntrinsic(Intrinsic.X86Mulps, res, mask);
  836. Operand res2 = context.AddIntrinsic(Intrinsic.X86Pslld, n, Const(16));
  837. res2 = context.AddIntrinsic(Intrinsic.X86Psrld, res2, Const(16));
  838. res2 = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res2);
  839. res = context.AddIntrinsic(Intrinsic.X86Addps, res, res2);
  840. if (op is OpCodeSimdShImm fixedOp)
  841. {
  842. int fBits = GetImmShr(fixedOp);
  843. // BitConverter.Int32BitsToSingle(fpScaled) == 1f / MathF.Pow(2f, fBits)
  844. int fpScaled = 0x3F800000 - fBits * 0x800000;
  845. Operand scale = X86GetAllElements(context, fpScaled);
  846. res = context.AddIntrinsic(Intrinsic.X86Mulps, res, scale);
  847. }
  848. if (scalar)
  849. {
  850. res = context.VectorZeroUpper96(res);
  851. }
  852. else if (op.RegisterSize == RegisterSize.Simd64)
  853. {
  854. res = context.VectorZeroUpper64(res);
  855. }
  856. context.Copy(GetVec(op.Rd), res);
  857. }
  858. private static Operand EmitVectorLongExtract(ArmEmitterContext context, int reg, int index, int size)
  859. {
  860. OperandType type = size == 3 ? OperandType.I64 : OperandType.I32;
  861. return context.VectorExtract(type, GetVec(reg), index);
  862. }
  863. private static Operand EmitVectorLongCreate(ArmEmitterContext context, Operand low, Operand high)
  864. {
  865. Operand vector = context.VectorCreateScalar(low);
  866. vector = context.VectorInsert(vector, high, 1);
  867. return vector;
  868. }
  869. }
  870. }