InstEmitSimdCvt.cs 54 KB

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  1. using ARMeilleure.Decoders;
  2. using ARMeilleure.IntermediateRepresentation;
  3. using ARMeilleure.State;
  4. using ARMeilleure.Translation;
  5. using System;
  6. using System.Diagnostics;
  7. using System.Reflection;
  8. using static ARMeilleure.Instructions.InstEmitHelper;
  9. using static ARMeilleure.Instructions.InstEmitSimdHelper;
  10. using static ARMeilleure.IntermediateRepresentation.OperandHelper;
  11. namespace ARMeilleure.Instructions
  12. {
  13. using Func1I = Func<Operand, Operand>;
  14. static partial class InstEmit
  15. {
  16. public static void Fcvt_S(ArmEmitterContext context)
  17. {
  18. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  19. if (op.Size == 0 && op.Opc == 1) // Single -> Double.
  20. {
  21. if (Optimizations.UseSse2)
  22. {
  23. Operand n = GetVec(op.Rn);
  24. Operand res = context.AddIntrinsic(Intrinsic.X86Cvtss2sd, context.VectorZero(), n);
  25. context.Copy(GetVec(op.Rd), res);
  26. }
  27. else
  28. {
  29. Operand ne = context.VectorExtract(OperandType.FP32, GetVec(op.Rn), 0);
  30. Operand res = context.ConvertToFP(OperandType.FP64, ne);
  31. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  32. }
  33. }
  34. else if (op.Size == 1 && op.Opc == 0) // Double -> Single.
  35. {
  36. if (Optimizations.UseSse2)
  37. {
  38. Operand n = GetVec(op.Rn);
  39. Operand res = context.AddIntrinsic(Intrinsic.X86Cvtsd2ss, context.VectorZero(), n);
  40. context.Copy(GetVec(op.Rd), res);
  41. }
  42. else
  43. {
  44. Operand ne = context.VectorExtract(OperandType.FP64, GetVec(op.Rn), 0);
  45. Operand res = context.ConvertToFP(OperandType.FP32, ne);
  46. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  47. }
  48. }
  49. else if (op.Size == 0 && op.Opc == 3) // Single -> Half.
  50. {
  51. Operand ne = context.VectorExtract(OperandType.FP32, GetVec(op.Rn), 0);
  52. Operand res = context.Call(typeof(SoftFloat32_16).GetMethod(nameof(SoftFloat32_16.FPConvert)), ne);
  53. res = context.ZeroExtend16(OperandType.I64, res);
  54. context.Copy(GetVec(op.Rd), EmitVectorInsert(context, context.VectorZero(), res, 0, 1));
  55. }
  56. else if (op.Size == 3 && op.Opc == 0) // Half -> Single.
  57. {
  58. Operand ne = EmitVectorExtractZx(context, op.Rn, 0, 1);
  59. Operand res = context.Call(typeof(SoftFloat16_32).GetMethod(nameof(SoftFloat16_32.FPConvert)), ne);
  60. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  61. }
  62. else if (op.Size == 1 && op.Opc == 3) // Double -> Half.
  63. {
  64. throw new NotImplementedException("Double-precision to half-precision.");
  65. }
  66. else if (op.Size == 3 && op.Opc == 1) // Double -> Half.
  67. {
  68. throw new NotImplementedException("Half-precision to double-precision.");
  69. }
  70. else // Invalid encoding.
  71. {
  72. Debug.Assert(false, $"type == {op.Size} && opc == {op.Opc}");
  73. }
  74. }
  75. public static void Fcvtas_Gp(ArmEmitterContext context)
  76. {
  77. EmitFcvt_s_Gp(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1));
  78. }
  79. public static void Fcvtas_S(ArmEmitterContext context)
  80. {
  81. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1), signed: true, scalar: true);
  82. }
  83. public static void Fcvtas_V(ArmEmitterContext context)
  84. {
  85. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1), signed: true, scalar: false);
  86. }
  87. public static void Fcvtau_Gp(ArmEmitterContext context)
  88. {
  89. EmitFcvt_u_Gp(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1));
  90. }
  91. public static void Fcvtau_S(ArmEmitterContext context)
  92. {
  93. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1), signed: false, scalar: true);
  94. }
  95. public static void Fcvtau_V(ArmEmitterContext context)
  96. {
  97. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1), signed: false, scalar: false);
  98. }
  99. public static void Fcvtl_V(ArmEmitterContext context)
  100. {
  101. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  102. int sizeF = op.Size & 1;
  103. if (Optimizations.UseSse2 && sizeF == 1)
  104. {
  105. Operand n = GetVec(op.Rn);
  106. Operand res;
  107. if (op.RegisterSize == RegisterSize.Simd128)
  108. {
  109. res = context.AddIntrinsic(Intrinsic.X86Movhlps, n, n);
  110. }
  111. else
  112. {
  113. res = n;
  114. }
  115. res = context.AddIntrinsic(Intrinsic.X86Cvtps2pd, res);
  116. context.Copy(GetVec(op.Rd), res);
  117. }
  118. else
  119. {
  120. Operand res = context.VectorZero();
  121. int elems = 4 >> sizeF;
  122. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  123. for (int index = 0; index < elems; index++)
  124. {
  125. if (sizeF == 0)
  126. {
  127. Operand ne = EmitVectorExtractZx(context, op.Rn, part + index, 1);
  128. Operand e = context.Call(typeof(SoftFloat16_32).GetMethod(nameof(SoftFloat16_32.FPConvert)), ne);
  129. res = context.VectorInsert(res, e, index);
  130. }
  131. else /* if (sizeF == 1) */
  132. {
  133. Operand ne = context.VectorExtract(OperandType.FP32, GetVec(op.Rn), part + index);
  134. Operand e = context.ConvertToFP(OperandType.FP64, ne);
  135. res = context.VectorInsert(res, e, index);
  136. }
  137. }
  138. context.Copy(GetVec(op.Rd), res);
  139. }
  140. }
  141. public static void Fcvtms_Gp(ArmEmitterContext context)
  142. {
  143. if (Optimizations.UseSse41)
  144. {
  145. EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsMinusInfinity, isFixed: false);
  146. }
  147. else
  148. {
  149. EmitFcvt_s_Gp(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Floor), op1));
  150. }
  151. }
  152. public static void Fcvtmu_Gp(ArmEmitterContext context)
  153. {
  154. if (Optimizations.UseSse41)
  155. {
  156. EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsMinusInfinity, isFixed: false);
  157. }
  158. else
  159. {
  160. EmitFcvt_u_Gp(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Floor), op1));
  161. }
  162. }
  163. public static void Fcvtn_V(ArmEmitterContext context)
  164. {
  165. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  166. int sizeF = op.Size & 1;
  167. if (Optimizations.UseSse2 && sizeF == 1)
  168. {
  169. Operand d = GetVec(op.Rd);
  170. Operand res = context.VectorZeroUpper64(d);
  171. Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtpd2ps, GetVec(op.Rn));
  172. nInt = context.AddIntrinsic(Intrinsic.X86Movlhps, nInt, nInt);
  173. Intrinsic movInst = op.RegisterSize == RegisterSize.Simd128
  174. ? Intrinsic.X86Movlhps
  175. : Intrinsic.X86Movhlps;
  176. res = context.AddIntrinsic(movInst, res, nInt);
  177. context.Copy(d, res);
  178. }
  179. else
  180. {
  181. OperandType type = sizeF == 0 ? OperandType.FP32 : OperandType.FP64;
  182. int elems = 4 >> sizeF;
  183. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  184. Operand d = GetVec(op.Rd);
  185. Operand res = part == 0 ? context.VectorZero() : context.Copy(d);
  186. for (int index = 0; index < elems; index++)
  187. {
  188. Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
  189. if (sizeF == 0)
  190. {
  191. Operand e = context.Call(typeof(SoftFloat32_16).GetMethod(nameof(SoftFloat32_16.FPConvert)), ne);
  192. e = context.ZeroExtend16(OperandType.I64, e);
  193. res = EmitVectorInsert(context, res, e, part + index, 1);
  194. }
  195. else /* if (sizeF == 1) */
  196. {
  197. Operand e = context.ConvertToFP(OperandType.FP32, ne);
  198. res = context.VectorInsert(res, e, part + index);
  199. }
  200. }
  201. context.Copy(d, res);
  202. }
  203. }
  204. public static void Fcvtns_S(ArmEmitterContext context)
  205. {
  206. if (Optimizations.UseSse41)
  207. {
  208. EmitSse41FcvtsOpF(context, FPRoundingMode.ToNearest, scalar: true);
  209. }
  210. else
  211. {
  212. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1), signed: true, scalar: true);
  213. }
  214. }
  215. public static void Fcvtns_V(ArmEmitterContext context)
  216. {
  217. if (Optimizations.UseSse41)
  218. {
  219. EmitSse41FcvtsOpF(context, FPRoundingMode.ToNearest, scalar: false);
  220. }
  221. else
  222. {
  223. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1), signed: true, scalar: false);
  224. }
  225. }
  226. public static void Fcvtnu_S(ArmEmitterContext context)
  227. {
  228. if (Optimizations.UseSse41)
  229. {
  230. EmitSse41FcvtuOpF(context, FPRoundingMode.ToNearest, scalar: true);
  231. }
  232. else
  233. {
  234. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1), signed: false, scalar: true);
  235. }
  236. }
  237. public static void Fcvtnu_V(ArmEmitterContext context)
  238. {
  239. if (Optimizations.UseSse41)
  240. {
  241. EmitSse41FcvtuOpF(context, FPRoundingMode.ToNearest, scalar: false);
  242. }
  243. else
  244. {
  245. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1), signed: false, scalar: false);
  246. }
  247. }
  248. public static void Fcvtps_Gp(ArmEmitterContext context)
  249. {
  250. if (Optimizations.UseSse41)
  251. {
  252. EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsPlusInfinity, isFixed: false);
  253. }
  254. else
  255. {
  256. EmitFcvt_s_Gp(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Ceiling), op1));
  257. }
  258. }
  259. public static void Fcvtpu_Gp(ArmEmitterContext context)
  260. {
  261. if (Optimizations.UseSse41)
  262. {
  263. EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsPlusInfinity, isFixed: false);
  264. }
  265. else
  266. {
  267. EmitFcvt_u_Gp(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Ceiling), op1));
  268. }
  269. }
  270. public static void Fcvtzs_Gp(ArmEmitterContext context)
  271. {
  272. if (Optimizations.UseSse41)
  273. {
  274. EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsZero, isFixed: false);
  275. }
  276. else
  277. {
  278. EmitFcvt_s_Gp(context, (op1) => op1);
  279. }
  280. }
  281. public static void Fcvtzs_Gp_Fixed(ArmEmitterContext context)
  282. {
  283. if (Optimizations.UseSse41)
  284. {
  285. EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsZero, isFixed: true);
  286. }
  287. else
  288. {
  289. EmitFcvtzs_Gp_Fixed(context);
  290. }
  291. }
  292. public static void Fcvtzs_S(ArmEmitterContext context)
  293. {
  294. if (Optimizations.UseSse41)
  295. {
  296. EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsZero, scalar: true);
  297. }
  298. else
  299. {
  300. EmitFcvtz(context, signed: true, scalar: true);
  301. }
  302. }
  303. public static void Fcvtzs_V(ArmEmitterContext context)
  304. {
  305. if (Optimizations.UseSse41)
  306. {
  307. EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsZero, scalar: false);
  308. }
  309. else
  310. {
  311. EmitFcvtz(context, signed: true, scalar: false);
  312. }
  313. }
  314. public static void Fcvtzs_V_Fixed(ArmEmitterContext context)
  315. {
  316. if (Optimizations.UseSse41)
  317. {
  318. EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsZero, scalar: false);
  319. }
  320. else
  321. {
  322. EmitFcvtz(context, signed: true, scalar: false);
  323. }
  324. }
  325. public static void Fcvtzu_Gp(ArmEmitterContext context)
  326. {
  327. if (Optimizations.UseSse41)
  328. {
  329. EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsZero, isFixed: false);
  330. }
  331. else
  332. {
  333. EmitFcvt_u_Gp(context, (op1) => op1);
  334. }
  335. }
  336. public static void Fcvtzu_Gp_Fixed(ArmEmitterContext context)
  337. {
  338. if (Optimizations.UseSse41)
  339. {
  340. EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsZero, isFixed: true);
  341. }
  342. else
  343. {
  344. EmitFcvtzu_Gp_Fixed(context);
  345. }
  346. }
  347. public static void Fcvtzu_S(ArmEmitterContext context)
  348. {
  349. if (Optimizations.UseSse41)
  350. {
  351. EmitSse41FcvtuOpF(context, FPRoundingMode.TowardsZero, scalar: true);
  352. }
  353. else
  354. {
  355. EmitFcvtz(context, signed: false, scalar: true);
  356. }
  357. }
  358. public static void Fcvtzu_V(ArmEmitterContext context)
  359. {
  360. if (Optimizations.UseSse41)
  361. {
  362. EmitSse41FcvtuOpF(context, FPRoundingMode.TowardsZero, scalar: false);
  363. }
  364. else
  365. {
  366. EmitFcvtz(context, signed: false, scalar: false);
  367. }
  368. }
  369. public static void Fcvtzu_V_Fixed(ArmEmitterContext context)
  370. {
  371. if (Optimizations.UseSse41)
  372. {
  373. EmitSse41FcvtuOpF(context, FPRoundingMode.TowardsZero, scalar: false);
  374. }
  375. else
  376. {
  377. EmitFcvtz(context, signed: false, scalar: false);
  378. }
  379. }
  380. public static void Scvtf_Gp(ArmEmitterContext context)
  381. {
  382. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  383. Operand res = GetIntOrZR(context, op.Rn);
  384. if (op.RegisterSize == RegisterSize.Int32)
  385. {
  386. res = context.SignExtend32(OperandType.I64, res);
  387. }
  388. res = EmitFPConvert(context, res, op.Size, signed: true);
  389. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  390. }
  391. public static void Scvtf_Gp_Fixed(ArmEmitterContext context)
  392. {
  393. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  394. Operand res = GetIntOrZR(context, op.Rn);
  395. if (op.RegisterSize == RegisterSize.Int32)
  396. {
  397. res = context.SignExtend32(OperandType.I64, res);
  398. }
  399. res = EmitFPConvert(context, res, op.Size, signed: true);
  400. res = EmitI2fFBitsMul(context, res, op.FBits);
  401. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  402. }
  403. public static void Scvtf_S(ArmEmitterContext context)
  404. {
  405. if (Optimizations.UseSse2)
  406. {
  407. EmitSse2ScvtfOp(context, scalar: true);
  408. }
  409. else
  410. {
  411. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  412. int sizeF = op.Size & 1;
  413. Operand res = EmitVectorLongExtract(context, op.Rn, 0, sizeF + 2);
  414. res = EmitFPConvert(context, res, op.Size, signed: true);
  415. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  416. }
  417. }
  418. public static void Scvtf_V(ArmEmitterContext context)
  419. {
  420. if (Optimizations.UseSse2)
  421. {
  422. EmitSse2ScvtfOp(context, scalar: false);
  423. }
  424. else
  425. {
  426. EmitVectorCvtf(context, signed: true);
  427. }
  428. }
  429. public static void Scvtf_V_Fixed(ArmEmitterContext context)
  430. {
  431. if (Optimizations.UseSse2)
  432. {
  433. EmitSse2ScvtfOp(context, scalar: false);
  434. }
  435. else
  436. {
  437. EmitVectorCvtf(context, signed: true);
  438. }
  439. }
  440. public static void Ucvtf_Gp(ArmEmitterContext context)
  441. {
  442. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  443. Operand res = GetIntOrZR(context, op.Rn);
  444. res = EmitFPConvert(context, res, op.Size, signed: false);
  445. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  446. }
  447. public static void Ucvtf_Gp_Fixed(ArmEmitterContext context)
  448. {
  449. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  450. Operand res = GetIntOrZR(context, op.Rn);
  451. res = EmitFPConvert(context, res, op.Size, signed: false);
  452. res = EmitI2fFBitsMul(context, res, op.FBits);
  453. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  454. }
  455. public static void Ucvtf_S(ArmEmitterContext context)
  456. {
  457. if (Optimizations.UseSse2)
  458. {
  459. EmitSse2UcvtfOp(context, scalar: true);
  460. }
  461. else
  462. {
  463. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  464. int sizeF = op.Size & 1;
  465. Operand ne = EmitVectorLongExtract(context, op.Rn, 0, sizeF + 2);
  466. Operand res = EmitFPConvert(context, ne, sizeF, signed: false);
  467. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  468. }
  469. }
  470. public static void Ucvtf_V(ArmEmitterContext context)
  471. {
  472. if (Optimizations.UseSse2)
  473. {
  474. EmitSse2UcvtfOp(context, scalar: false);
  475. }
  476. else
  477. {
  478. EmitVectorCvtf(context, signed: false);
  479. }
  480. }
  481. public static void Ucvtf_V_Fixed(ArmEmitterContext context)
  482. {
  483. if (Optimizations.UseSse2)
  484. {
  485. EmitSse2UcvtfOp(context, scalar: false);
  486. }
  487. else
  488. {
  489. EmitVectorCvtf(context, signed: false);
  490. }
  491. }
  492. private static void EmitFcvt(ArmEmitterContext context, Func1I emit, bool signed, bool scalar)
  493. {
  494. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  495. Operand res = context.VectorZero();
  496. Operand n = GetVec(op.Rn);
  497. int sizeF = op.Size & 1;
  498. int sizeI = sizeF + 2;
  499. OperandType type = sizeF == 0 ? OperandType.FP32 : OperandType.FP64;
  500. int elems = !scalar ? op.GetBytesCount() >> sizeI : 1;
  501. for (int index = 0; index < elems; index++)
  502. {
  503. Operand ne = context.VectorExtract(type, n, index);
  504. Operand e = emit(ne);
  505. if (sizeF == 0)
  506. {
  507. MethodInfo info = signed
  508. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS32))
  509. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU32));
  510. e = context.Call(info, e);
  511. e = context.ZeroExtend32(OperandType.I64, e);
  512. }
  513. else /* if (sizeF == 1) */
  514. {
  515. MethodInfo info = signed
  516. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS64))
  517. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU64));
  518. e = context.Call(info, e);
  519. }
  520. res = EmitVectorInsert(context, res, e, index, sizeI);
  521. }
  522. context.Copy(GetVec(op.Rd), res);
  523. }
  524. private static void EmitFcvtz(ArmEmitterContext context, bool signed, bool scalar)
  525. {
  526. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  527. Operand res = context.VectorZero();
  528. Operand n = GetVec(op.Rn);
  529. int sizeF = op.Size & 1;
  530. int sizeI = sizeF + 2;
  531. OperandType type = sizeF == 0 ? OperandType.FP32 : OperandType.FP64;
  532. int fBits = GetFBits(context);
  533. int elems = !scalar ? op.GetBytesCount() >> sizeI : 1;
  534. for (int index = 0; index < elems; index++)
  535. {
  536. Operand ne = context.VectorExtract(type, n, index);
  537. Operand e = EmitF2iFBitsMul(context, ne, fBits);
  538. if (sizeF == 0)
  539. {
  540. MethodInfo info = signed
  541. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS32))
  542. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU32));
  543. e = context.Call(info, e);
  544. e = context.ZeroExtend32(OperandType.I64, e);
  545. }
  546. else /* if (sizeF == 1) */
  547. {
  548. MethodInfo info = signed
  549. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS64))
  550. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU64));
  551. e = context.Call(info, e);
  552. }
  553. res = EmitVectorInsert(context, res, e, index, sizeI);
  554. }
  555. context.Copy(GetVec(op.Rd), res);
  556. }
  557. private static void EmitFcvt_s_Gp(ArmEmitterContext context, Func1I emit)
  558. {
  559. EmitFcvt___Gp(context, emit, signed: true);
  560. }
  561. private static void EmitFcvt_u_Gp(ArmEmitterContext context, Func1I emit)
  562. {
  563. EmitFcvt___Gp(context, emit, signed: false);
  564. }
  565. private static void EmitFcvt___Gp(ArmEmitterContext context, Func1I emit, bool signed)
  566. {
  567. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  568. OperandType type = op.Size == 0 ? OperandType.FP32 : OperandType.FP64;
  569. Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
  570. Operand res = signed
  571. ? EmitScalarFcvts(context, emit(ne), 0)
  572. : EmitScalarFcvtu(context, emit(ne), 0);
  573. SetIntOrZR(context, op.Rd, res);
  574. }
  575. private static void EmitFcvtzs_Gp_Fixed(ArmEmitterContext context)
  576. {
  577. EmitFcvtz__Gp_Fixed(context, signed: true);
  578. }
  579. private static void EmitFcvtzu_Gp_Fixed(ArmEmitterContext context)
  580. {
  581. EmitFcvtz__Gp_Fixed(context, signed: false);
  582. }
  583. private static void EmitFcvtz__Gp_Fixed(ArmEmitterContext context, bool signed)
  584. {
  585. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  586. OperandType type = op.Size == 0 ? OperandType.FP32 : OperandType.FP64;
  587. Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
  588. Operand res = signed
  589. ? EmitScalarFcvts(context, ne, op.FBits)
  590. : EmitScalarFcvtu(context, ne, op.FBits);
  591. SetIntOrZR(context, op.Rd, res);
  592. }
  593. private static void EmitVectorCvtf(ArmEmitterContext context, bool signed)
  594. {
  595. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  596. Operand res = context.VectorZero();
  597. int sizeF = op.Size & 1;
  598. int sizeI = sizeF + 2;
  599. int fBits = GetFBits(context);
  600. int elems = op.GetBytesCount() >> sizeI;
  601. for (int index = 0; index < elems; index++)
  602. {
  603. Operand ne = EmitVectorLongExtract(context, op.Rn, index, sizeI);
  604. Operand e = EmitFPConvert(context, ne, sizeF, signed);
  605. e = EmitI2fFBitsMul(context, e, fBits);
  606. res = context.VectorInsert(res, e, index);
  607. }
  608. context.Copy(GetVec(op.Rd), res);
  609. }
  610. private static int GetFBits(ArmEmitterContext context)
  611. {
  612. if (context.CurrOp is OpCodeSimdShImm op)
  613. {
  614. return GetImmShr(op);
  615. }
  616. return 0;
  617. }
  618. private static Operand EmitFPConvert(ArmEmitterContext context, Operand value, int size, bool signed)
  619. {
  620. Debug.Assert(value.Type == OperandType.I32 || value.Type == OperandType.I64);
  621. Debug.Assert((uint)size < 2);
  622. OperandType type = size == 0 ? OperandType.FP32 : OperandType.FP64;
  623. if (signed)
  624. {
  625. return context.ConvertToFP(type, value);
  626. }
  627. else
  628. {
  629. return context.ConvertToFPUI(type, value);
  630. }
  631. }
  632. private static Operand EmitScalarFcvts(ArmEmitterContext context, Operand value, int fBits)
  633. {
  634. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  635. value = EmitF2iFBitsMul(context, value, fBits);
  636. MethodInfo info;
  637. if (context.CurrOp.RegisterSize == RegisterSize.Int32)
  638. {
  639. info = value.Type == OperandType.FP32
  640. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS32))
  641. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS32));
  642. }
  643. else
  644. {
  645. info = value.Type == OperandType.FP32
  646. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS64))
  647. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS64));
  648. }
  649. return context.Call(info, value);
  650. }
  651. private static Operand EmitScalarFcvtu(ArmEmitterContext context, Operand value, int fBits)
  652. {
  653. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  654. value = EmitF2iFBitsMul(context, value, fBits);
  655. MethodInfo info;
  656. if (context.CurrOp.RegisterSize == RegisterSize.Int32)
  657. {
  658. info = value.Type == OperandType.FP32
  659. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU32))
  660. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU32));
  661. }
  662. else
  663. {
  664. info = value.Type == OperandType.FP32
  665. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU64))
  666. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU64));
  667. }
  668. return context.Call(info, value);
  669. }
  670. private static Operand EmitF2iFBitsMul(ArmEmitterContext context, Operand value, int fBits)
  671. {
  672. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  673. if (fBits == 0)
  674. {
  675. return value;
  676. }
  677. if (value.Type == OperandType.FP32)
  678. {
  679. return context.Multiply(value, ConstF(MathF.Pow(2f, fBits)));
  680. }
  681. else /* if (value.Type == OperandType.FP64) */
  682. {
  683. return context.Multiply(value, ConstF(Math.Pow(2d, fBits)));
  684. }
  685. }
  686. private static Operand EmitI2fFBitsMul(ArmEmitterContext context, Operand value, int fBits)
  687. {
  688. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  689. if (fBits == 0)
  690. {
  691. return value;
  692. }
  693. if (value.Type == OperandType.FP32)
  694. {
  695. return context.Multiply(value, ConstF(1f / MathF.Pow(2f, fBits)));
  696. }
  697. else /* if (value.Type == OperandType.FP64) */
  698. {
  699. return context.Multiply(value, ConstF(1d / Math.Pow(2d, fBits)));
  700. }
  701. }
  702. public static Operand EmitSse2CvtDoubleToInt64OpF(ArmEmitterContext context, Operand opF, bool scalar)
  703. {
  704. Debug.Assert(opF.Type == OperandType.V128);
  705. Operand longL = context.AddIntrinsicLong (Intrinsic.X86Cvtsd2si, opF); // opFL
  706. Operand res = context.VectorCreateScalar(longL);
  707. if (!scalar)
  708. {
  709. Operand opFH = context.AddIntrinsic (Intrinsic.X86Movhlps, res, opF); // res doesn't matter.
  710. Operand longH = context.AddIntrinsicLong (Intrinsic.X86Cvtsd2si, opFH);
  711. Operand resH = context.VectorCreateScalar(longH);
  712. res = context.AddIntrinsic (Intrinsic.X86Movlhps, res, resH);
  713. }
  714. return res;
  715. }
  716. private static Operand EmitSse2CvtInt64ToDoubleOp(ArmEmitterContext context, Operand op, bool scalar)
  717. {
  718. Debug.Assert(op.Type == OperandType.V128);
  719. Operand longL = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, op); // opL
  720. Operand res = context.AddIntrinsic (Intrinsic.X86Cvtsi2sd, context.VectorZero(), longL);
  721. if (!scalar)
  722. {
  723. Operand opH = context.AddIntrinsic (Intrinsic.X86Movhlps, res, op); // res doesn't matter.
  724. Operand longH = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, opH);
  725. Operand resH = context.AddIntrinsic (Intrinsic.X86Cvtsi2sd, res, longH); // res doesn't matter.
  726. res = context.AddIntrinsic (Intrinsic.X86Movlhps, res, resH);
  727. }
  728. return res;
  729. }
  730. private static void EmitSse2ScvtfOp(ArmEmitterContext context, bool scalar)
  731. {
  732. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  733. Operand n = GetVec(op.Rn);
  734. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  735. int sizeF = op.Size & 1;
  736. if (sizeF == 0)
  737. {
  738. Operand res = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, n);
  739. if (op is OpCodeSimdShImm fixedOp)
  740. {
  741. int fBits = GetImmShr(fixedOp);
  742. // BitConverter.Int32BitsToSingle(fpScaled) == 1f / MathF.Pow(2f, fBits)
  743. int fpScaled = 0x3F800000 - fBits * 0x800000;
  744. Operand fpScaledMask = scalar
  745. ? X86GetScalar (context, fpScaled)
  746. : X86GetAllElements(context, fpScaled);
  747. res = context.AddIntrinsic(Intrinsic.X86Mulps, res, fpScaledMask);
  748. }
  749. if (scalar)
  750. {
  751. res = context.VectorZeroUpper96(res);
  752. }
  753. else if (op.RegisterSize == RegisterSize.Simd64)
  754. {
  755. res = context.VectorZeroUpper64(res);
  756. }
  757. context.Copy(GetVec(op.Rd), res);
  758. }
  759. else /* if (sizeF == 1) */
  760. {
  761. Operand res = EmitSse2CvtInt64ToDoubleOp(context, n, scalar);
  762. if (op is OpCodeSimdShImm fixedOp)
  763. {
  764. int fBits = GetImmShr(fixedOp);
  765. // BitConverter.Int64BitsToDouble(fpScaled) == 1d / Math.Pow(2d, fBits)
  766. long fpScaled = 0x3FF0000000000000L - fBits * 0x10000000000000L;
  767. Operand fpScaledMask = scalar
  768. ? X86GetScalar (context, fpScaled)
  769. : X86GetAllElements(context, fpScaled);
  770. res = context.AddIntrinsic(Intrinsic.X86Mulpd, res, fpScaledMask);
  771. }
  772. if (scalar)
  773. {
  774. res = context.VectorZeroUpper64(res);
  775. }
  776. context.Copy(GetVec(op.Rd), res);
  777. }
  778. }
  779. private static void EmitSse2UcvtfOp(ArmEmitterContext context, bool scalar)
  780. {
  781. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  782. Operand n = GetVec(op.Rn);
  783. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  784. int sizeF = op.Size & 1;
  785. if (sizeF == 0)
  786. {
  787. Operand mask = scalar // 65536.000f (1 << 16)
  788. ? X86GetScalar (context, 0x47800000)
  789. : X86GetAllElements(context, 0x47800000);
  790. Operand res = context.AddIntrinsic(Intrinsic.X86Psrld, n, Const(16));
  791. res = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res);
  792. res = context.AddIntrinsic(Intrinsic.X86Mulps, res, mask);
  793. Operand res2 = context.AddIntrinsic(Intrinsic.X86Pslld, n, Const(16));
  794. res2 = context.AddIntrinsic(Intrinsic.X86Psrld, res2, Const(16));
  795. res2 = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res2);
  796. res = context.AddIntrinsic(Intrinsic.X86Addps, res, res2);
  797. if (op is OpCodeSimdShImm fixedOp)
  798. {
  799. int fBits = GetImmShr(fixedOp);
  800. // BitConverter.Int32BitsToSingle(fpScaled) == 1f / MathF.Pow(2f, fBits)
  801. int fpScaled = 0x3F800000 - fBits * 0x800000;
  802. Operand fpScaledMask = scalar
  803. ? X86GetScalar (context, fpScaled)
  804. : X86GetAllElements(context, fpScaled);
  805. res = context.AddIntrinsic(Intrinsic.X86Mulps, res, fpScaledMask);
  806. }
  807. if (scalar)
  808. {
  809. res = context.VectorZeroUpper96(res);
  810. }
  811. else if (op.RegisterSize == RegisterSize.Simd64)
  812. {
  813. res = context.VectorZeroUpper64(res);
  814. }
  815. context.Copy(GetVec(op.Rd), res);
  816. }
  817. else /* if (sizeF == 1) */
  818. {
  819. Operand mask = scalar // 4294967296.0000000d (1L << 32)
  820. ? X86GetScalar (context, 0x41F0000000000000L)
  821. : X86GetAllElements(context, 0x41F0000000000000L);
  822. Operand res = context.AddIntrinsic (Intrinsic.X86Psrlq, n, Const(32));
  823. res = EmitSse2CvtInt64ToDoubleOp(context, res, scalar);
  824. res = context.AddIntrinsic (Intrinsic.X86Mulpd, res, mask);
  825. Operand res2 = context.AddIntrinsic (Intrinsic.X86Psllq, n, Const(32));
  826. res2 = context.AddIntrinsic (Intrinsic.X86Psrlq, res2, Const(32));
  827. res2 = EmitSse2CvtInt64ToDoubleOp(context, res2, scalar);
  828. res = context.AddIntrinsic(Intrinsic.X86Addpd, res, res2);
  829. if (op is OpCodeSimdShImm fixedOp)
  830. {
  831. int fBits = GetImmShr(fixedOp);
  832. // BitConverter.Int64BitsToDouble(fpScaled) == 1d / Math.Pow(2d, fBits)
  833. long fpScaled = 0x3FF0000000000000L - fBits * 0x10000000000000L;
  834. Operand fpScaledMask = scalar
  835. ? X86GetScalar (context, fpScaled)
  836. : X86GetAllElements(context, fpScaled);
  837. res = context.AddIntrinsic(Intrinsic.X86Mulpd, res, fpScaledMask);
  838. }
  839. if (scalar)
  840. {
  841. res = context.VectorZeroUpper64(res);
  842. }
  843. context.Copy(GetVec(op.Rd), res);
  844. }
  845. }
  846. private static void EmitSse41FcvtsOpF(ArmEmitterContext context, FPRoundingMode roundMode, bool scalar)
  847. {
  848. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  849. Operand n = GetVec(op.Rn);
  850. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  851. int sizeF = op.Size & 1;
  852. if (sizeF == 0)
  853. {
  854. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, n, n, Const((int)CmpCondition.OrderedQ));
  855. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  856. if (op is OpCodeSimdShImm fixedOp)
  857. {
  858. int fBits = GetImmShr(fixedOp);
  859. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, fBits)
  860. int fpScaled = 0x3F800000 + fBits * 0x800000;
  861. Operand fpScaledMask = scalar
  862. ? X86GetScalar (context, fpScaled)
  863. : X86GetAllElements(context, fpScaled);
  864. nRes = context.AddIntrinsic(Intrinsic.X86Mulps, nRes, fpScaledMask);
  865. }
  866. nRes = context.AddIntrinsic(Intrinsic.X86Roundps, nRes, Const(X86GetRoundControl(roundMode)));
  867. Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes);
  868. Operand fpMaxValMask = scalar // 2.14748365E9f (2147483648)
  869. ? X86GetScalar (context, 0x4F000000)
  870. : X86GetAllElements(context, 0x4F000000);
  871. nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  872. Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nInt, nRes);
  873. if (scalar)
  874. {
  875. dRes = context.VectorZeroUpper96(dRes);
  876. }
  877. else if (op.RegisterSize == RegisterSize.Simd64)
  878. {
  879. dRes = context.VectorZeroUpper64(dRes);
  880. }
  881. context.Copy(GetVec(op.Rd), dRes);
  882. }
  883. else /* if (sizeF == 1) */
  884. {
  885. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, n, n, Const((int)CmpCondition.OrderedQ));
  886. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  887. if (op is OpCodeSimdShImm fixedOp)
  888. {
  889. int fBits = GetImmShr(fixedOp);
  890. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, fBits)
  891. long fpScaled = 0x3FF0000000000000L + fBits * 0x10000000000000L;
  892. Operand fpScaledMask = scalar
  893. ? X86GetScalar (context, fpScaled)
  894. : X86GetAllElements(context, fpScaled);
  895. nRes = context.AddIntrinsic(Intrinsic.X86Mulpd, nRes, fpScaledMask);
  896. }
  897. nRes = context.AddIntrinsic(Intrinsic.X86Roundpd, nRes, Const(X86GetRoundControl(roundMode)));
  898. Operand nLong = EmitSse2CvtDoubleToInt64OpF(context, nRes, scalar);
  899. Operand fpMaxValMask = scalar // 9.2233720368547760E18d (9223372036854775808)
  900. ? X86GetScalar (context, 0x43E0000000000000L)
  901. : X86GetAllElements(context, 0x43E0000000000000L);
  902. nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  903. Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nLong, nRes);
  904. if (scalar)
  905. {
  906. dRes = context.VectorZeroUpper64(dRes);
  907. }
  908. context.Copy(GetVec(op.Rd), dRes);
  909. }
  910. }
  911. private static void EmitSse41FcvtuOpF(ArmEmitterContext context, FPRoundingMode roundMode, bool scalar)
  912. {
  913. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  914. Operand n = GetVec(op.Rn);
  915. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  916. int sizeF = op.Size & 1;
  917. if (sizeF == 0)
  918. {
  919. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, n, n, Const((int)CmpCondition.OrderedQ));
  920. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  921. if (op is OpCodeSimdShImm fixedOp)
  922. {
  923. int fBits = GetImmShr(fixedOp);
  924. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, fBits)
  925. int fpScaled = 0x3F800000 + fBits * 0x800000;
  926. Operand fpScaledMask = scalar
  927. ? X86GetScalar (context, fpScaled)
  928. : X86GetAllElements(context, fpScaled);
  929. nRes = context.AddIntrinsic(Intrinsic.X86Mulps, nRes, fpScaledMask);
  930. }
  931. nRes = context.AddIntrinsic(Intrinsic.X86Roundps, nRes, Const(X86GetRoundControl(roundMode)));
  932. Operand zero = context.VectorZero();
  933. Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  934. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  935. Operand fpMaxValMask = scalar // 2.14748365E9f (2147483648)
  936. ? X86GetScalar (context, 0x4F000000)
  937. : X86GetAllElements(context, 0x4F000000);
  938. Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes);
  939. nRes = context.AddIntrinsic(Intrinsic.X86Subps, nRes, fpMaxValMask);
  940. nCmp = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  941. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  942. Operand nInt2 = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes);
  943. nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  944. Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nInt2, nRes);
  945. dRes = context.AddIntrinsic(Intrinsic.X86Paddd, dRes, nInt);
  946. if (scalar)
  947. {
  948. dRes = context.VectorZeroUpper96(dRes);
  949. }
  950. else if (op.RegisterSize == RegisterSize.Simd64)
  951. {
  952. dRes = context.VectorZeroUpper64(dRes);
  953. }
  954. context.Copy(GetVec(op.Rd), dRes);
  955. }
  956. else /* if (sizeF == 1) */
  957. {
  958. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, n, n, Const((int)CmpCondition.OrderedQ));
  959. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  960. if (op is OpCodeSimdShImm fixedOp)
  961. {
  962. int fBits = GetImmShr(fixedOp);
  963. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, fBits)
  964. long fpScaled = 0x3FF0000000000000L + fBits * 0x10000000000000L;
  965. Operand fpScaledMask = scalar
  966. ? X86GetScalar (context, fpScaled)
  967. : X86GetAllElements(context, fpScaled);
  968. nRes = context.AddIntrinsic(Intrinsic.X86Mulpd, nRes, fpScaledMask);
  969. }
  970. nRes = context.AddIntrinsic(Intrinsic.X86Roundpd, nRes, Const(X86GetRoundControl(roundMode)));
  971. Operand zero = context.VectorZero();
  972. Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  973. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  974. Operand fpMaxValMask = scalar // 9.2233720368547760E18d (9223372036854775808)
  975. ? X86GetScalar (context, 0x43E0000000000000L)
  976. : X86GetAllElements(context, 0x43E0000000000000L);
  977. Operand nLong = EmitSse2CvtDoubleToInt64OpF(context, nRes, scalar);
  978. nRes = context.AddIntrinsic(Intrinsic.X86Subpd, nRes, fpMaxValMask);
  979. nCmp = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  980. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  981. Operand nLong2 = EmitSse2CvtDoubleToInt64OpF(context, nRes, scalar);
  982. nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  983. Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nLong2, nRes);
  984. dRes = context.AddIntrinsic(Intrinsic.X86Paddq, dRes, nLong);
  985. if (scalar)
  986. {
  987. dRes = context.VectorZeroUpper64(dRes);
  988. }
  989. context.Copy(GetVec(op.Rd), dRes);
  990. }
  991. }
  992. private static void EmitSse41Fcvts_Gp(ArmEmitterContext context, FPRoundingMode roundMode, bool isFixed)
  993. {
  994. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  995. Operand n = GetVec(op.Rn);
  996. if (op.Size == 0)
  997. {
  998. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, n, n, Const((int)CmpCondition.OrderedQ));
  999. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1000. if (isFixed)
  1001. {
  1002. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, op.FBits)
  1003. int fpScaled = 0x3F800000 + op.FBits * 0x800000;
  1004. Operand fpScaledMask = X86GetScalar(context, fpScaled);
  1005. nRes = context.AddIntrinsic(Intrinsic.X86Mulss, nRes, fpScaledMask);
  1006. }
  1007. nRes = context.AddIntrinsic(Intrinsic.X86Roundss, nRes, Const(X86GetRoundControl(roundMode)));
  1008. Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
  1009. ? context.AddIntrinsicInt (Intrinsic.X86Cvtss2si, nRes)
  1010. : context.AddIntrinsicLong(Intrinsic.X86Cvtss2si, nRes);
  1011. int fpMaxVal = op.RegisterSize == RegisterSize.Int32
  1012. ? 0x4F000000 // 2.14748365E9f (2147483648)
  1013. : 0x5F000000; // 9.223372E18f (9223372036854775808)
  1014. Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
  1015. nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1016. Operand nInt = context.AddIntrinsicInt(Intrinsic.X86Cvtsi2si, nRes);
  1017. if (op.RegisterSize == RegisterSize.Int64)
  1018. {
  1019. nInt = context.SignExtend32(OperandType.I64, nInt);
  1020. }
  1021. Operand dRes = context.BitwiseExclusiveOr(nIntOrLong, nInt);
  1022. SetIntOrZR(context, op.Rd, dRes);
  1023. }
  1024. else /* if (op.Size == 1) */
  1025. {
  1026. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, n, n, Const((int)CmpCondition.OrderedQ));
  1027. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1028. if (isFixed)
  1029. {
  1030. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, op.FBits)
  1031. long fpScaled = 0x3FF0000000000000L + op.FBits * 0x10000000000000L;
  1032. Operand fpScaledMask = X86GetScalar(context, fpScaled);
  1033. nRes = context.AddIntrinsic(Intrinsic.X86Mulsd, nRes, fpScaledMask);
  1034. }
  1035. nRes = context.AddIntrinsic(Intrinsic.X86Roundsd, nRes, Const(X86GetRoundControl(roundMode)));
  1036. Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
  1037. ? context.AddIntrinsicInt (Intrinsic.X86Cvtsd2si, nRes)
  1038. : context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRes);
  1039. long fpMaxVal = op.RegisterSize == RegisterSize.Int32
  1040. ? 0x41E0000000000000L // 2147483648.0000000d (2147483648)
  1041. : 0x43E0000000000000L; // 9.2233720368547760E18d (9223372036854775808)
  1042. Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
  1043. nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1044. Operand nLong = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, nRes);
  1045. if (op.RegisterSize == RegisterSize.Int32)
  1046. {
  1047. nLong = context.ConvertI64ToI32(nLong);
  1048. }
  1049. Operand dRes = context.BitwiseExclusiveOr(nIntOrLong, nLong);
  1050. SetIntOrZR(context, op.Rd, dRes);
  1051. }
  1052. }
  1053. private static void EmitSse41Fcvtu_Gp(ArmEmitterContext context, FPRoundingMode roundMode, bool isFixed)
  1054. {
  1055. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  1056. Operand n = GetVec(op.Rn);
  1057. if (op.Size == 0)
  1058. {
  1059. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, n, n, Const((int)CmpCondition.OrderedQ));
  1060. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1061. if (isFixed)
  1062. {
  1063. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, op.FBits)
  1064. int fpScaled = 0x3F800000 + op.FBits * 0x800000;
  1065. Operand fpScaledMask = X86GetScalar(context, fpScaled);
  1066. nRes = context.AddIntrinsic(Intrinsic.X86Mulss, nRes, fpScaledMask);
  1067. }
  1068. nRes = context.AddIntrinsic(Intrinsic.X86Roundss, nRes, Const(X86GetRoundControl(roundMode)));
  1069. Operand zero = context.VectorZero();
  1070. Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1071. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1072. int fpMaxVal = op.RegisterSize == RegisterSize.Int32
  1073. ? 0x4F000000 // 2.14748365E9f (2147483648)
  1074. : 0x5F000000; // 9.223372E18f (9223372036854775808)
  1075. Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
  1076. Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
  1077. ? context.AddIntrinsicInt (Intrinsic.X86Cvtss2si, nRes)
  1078. : context.AddIntrinsicLong(Intrinsic.X86Cvtss2si, nRes);
  1079. nRes = context.AddIntrinsic(Intrinsic.X86Subss, nRes, fpMaxValMask);
  1080. nCmp = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1081. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1082. Operand nIntOrLong2 = op.RegisterSize == RegisterSize.Int32
  1083. ? context.AddIntrinsicInt (Intrinsic.X86Cvtss2si, nRes)
  1084. : context.AddIntrinsicLong(Intrinsic.X86Cvtss2si, nRes);
  1085. nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1086. Operand nInt = context.AddIntrinsicInt(Intrinsic.X86Cvtsi2si, nRes);
  1087. if (op.RegisterSize == RegisterSize.Int64)
  1088. {
  1089. nInt = context.SignExtend32(OperandType.I64, nInt);
  1090. }
  1091. Operand dRes = context.BitwiseExclusiveOr(nIntOrLong2, nInt);
  1092. dRes = context.Add(dRes, nIntOrLong);
  1093. SetIntOrZR(context, op.Rd, dRes);
  1094. }
  1095. else /* if (op.Size == 1) */
  1096. {
  1097. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, n, n, Const((int)CmpCondition.OrderedQ));
  1098. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1099. if (isFixed)
  1100. {
  1101. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, op.FBits)
  1102. long fpScaled = 0x3FF0000000000000L + op.FBits * 0x10000000000000L;
  1103. Operand fpScaledMask = X86GetScalar(context, fpScaled);
  1104. nRes = context.AddIntrinsic(Intrinsic.X86Mulsd, nRes, fpScaledMask);
  1105. }
  1106. nRes = context.AddIntrinsic(Intrinsic.X86Roundsd, nRes, Const(X86GetRoundControl(roundMode)));
  1107. Operand zero = context.VectorZero();
  1108. Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1109. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1110. long fpMaxVal = op.RegisterSize == RegisterSize.Int32
  1111. ? 0x41E0000000000000L // 2147483648.0000000d (2147483648)
  1112. : 0x43E0000000000000L; // 9.2233720368547760E18d (9223372036854775808)
  1113. Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
  1114. Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
  1115. ? context.AddIntrinsicInt (Intrinsic.X86Cvtsd2si, nRes)
  1116. : context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRes);
  1117. nRes = context.AddIntrinsic(Intrinsic.X86Subsd, nRes, fpMaxValMask);
  1118. nCmp = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1119. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1120. Operand nIntOrLong2 = op.RegisterSize == RegisterSize.Int32
  1121. ? context.AddIntrinsicInt (Intrinsic.X86Cvtsd2si, nRes)
  1122. : context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRes);
  1123. nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1124. Operand nLong = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, nRes);
  1125. if (op.RegisterSize == RegisterSize.Int32)
  1126. {
  1127. nLong = context.ConvertI64ToI32(nLong);
  1128. }
  1129. Operand dRes = context.BitwiseExclusiveOr(nIntOrLong2, nLong);
  1130. dRes = context.Add(dRes, nIntOrLong);
  1131. SetIntOrZR(context, op.Rd, dRes);
  1132. }
  1133. }
  1134. private static Operand EmitVectorLongExtract(ArmEmitterContext context, int reg, int index, int size)
  1135. {
  1136. OperandType type = size == 3 ? OperandType.I64 : OperandType.I32;
  1137. return context.VectorExtract(type, GetVec(reg), index);
  1138. }
  1139. }
  1140. }