InstEmitSimdCvt.cs 59 KB

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  1. using ARMeilleure.Decoders;
  2. using ARMeilleure.IntermediateRepresentation;
  3. using ARMeilleure.State;
  4. using ARMeilleure.Translation;
  5. using System;
  6. using System.Diagnostics;
  7. using System.Reflection;
  8. using static ARMeilleure.Instructions.InstEmitHelper;
  9. using static ARMeilleure.Instructions.InstEmitSimdHelper;
  10. using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
  11. namespace ARMeilleure.Instructions
  12. {
  13. using Func1I = Func<Operand, Operand>;
  14. static partial class InstEmit
  15. {
  16. public static void Fcvt_S(ArmEmitterContext context)
  17. {
  18. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  19. if (op.Size == 0 && op.Opc == 1) // Single -> Double.
  20. {
  21. if (Optimizations.UseSse2)
  22. {
  23. Operand n = GetVec(op.Rn);
  24. Operand res = context.AddIntrinsic(Intrinsic.X86Cvtss2sd, context.VectorZero(), n);
  25. context.Copy(GetVec(op.Rd), res);
  26. }
  27. else
  28. {
  29. Operand ne = context.VectorExtract(OperandType.FP32, GetVec(op.Rn), 0);
  30. Operand res = context.ConvertToFP(OperandType.FP64, ne);
  31. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  32. }
  33. }
  34. else if (op.Size == 1 && op.Opc == 0) // Double -> Single.
  35. {
  36. if (Optimizations.UseSse2)
  37. {
  38. Operand n = GetVec(op.Rn);
  39. Operand res = context.AddIntrinsic(Intrinsic.X86Cvtsd2ss, context.VectorZero(), n);
  40. context.Copy(GetVec(op.Rd), res);
  41. }
  42. else
  43. {
  44. Operand ne = context.VectorExtract(OperandType.FP64, GetVec(op.Rn), 0);
  45. Operand res = context.ConvertToFP(OperandType.FP32, ne);
  46. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  47. }
  48. }
  49. else if (op.Size == 0 && op.Opc == 3) // Single -> Half.
  50. {
  51. if (Optimizations.UseF16c)
  52. {
  53. Debug.Assert(!Optimizations.ForceLegacySse);
  54. Operand n = GetVec(op.Rn);
  55. Operand res = context.AddIntrinsic(Intrinsic.X86Vcvtps2ph, n, Const(X86GetRoundControl(FPRoundingMode.ToNearest)));
  56. res = context.AddIntrinsic(Intrinsic.X86Pslldq, res, Const(14)); // VectorZeroUpper112()
  57. res = context.AddIntrinsic(Intrinsic.X86Psrldq, res, Const(14));
  58. context.Copy(GetVec(op.Rd), res);
  59. }
  60. else
  61. {
  62. Operand ne = context.VectorExtract(OperandType.FP32, GetVec(op.Rn), 0);
  63. context.StoreToContext();
  64. Operand res = context.Call(typeof(SoftFloat32_16).GetMethod(nameof(SoftFloat32_16.FPConvert)), ne);
  65. context.LoadFromContext();
  66. res = context.ZeroExtend16(OperandType.I64, res);
  67. context.Copy(GetVec(op.Rd), EmitVectorInsert(context, context.VectorZero(), res, 0, 1));
  68. }
  69. }
  70. else if (op.Size == 3 && op.Opc == 0) // Half -> Single.
  71. {
  72. if (Optimizations.UseF16c)
  73. {
  74. Debug.Assert(!Optimizations.ForceLegacySse);
  75. Operand res = context.AddIntrinsic(Intrinsic.X86Vcvtph2ps, GetVec(op.Rn));
  76. res = context.VectorZeroUpper96(res);
  77. context.Copy(GetVec(op.Rd), res);
  78. }
  79. else
  80. {
  81. Operand ne = EmitVectorExtractZx(context, op.Rn, 0, 1);
  82. context.StoreToContext();
  83. Operand res = context.Call(typeof(SoftFloat16_32).GetMethod(nameof(SoftFloat16_32.FPConvert)), ne);
  84. context.LoadFromContext();
  85. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  86. }
  87. }
  88. else if (op.Size == 1 && op.Opc == 3) // Double -> Half.
  89. {
  90. if (Optimizations.UseF16c)
  91. {
  92. Debug.Assert(!Optimizations.ForceLegacySse);
  93. Operand n = GetVec(op.Rn);
  94. Operand res = context.AddIntrinsic(Intrinsic.X86Cvtsd2ss, context.VectorZero(), n);
  95. res = context.AddIntrinsic(Intrinsic.X86Vcvtps2ph, res, Const(X86GetRoundControl(FPRoundingMode.ToNearest)));
  96. context.Copy(GetVec(op.Rd), res);
  97. }
  98. else
  99. {
  100. Operand ne = context.VectorExtract(OperandType.FP64, GetVec(op.Rn), 0);
  101. context.StoreToContext();
  102. Operand res = context.Call(typeof(SoftFloat64_16).GetMethod(nameof(SoftFloat64_16.FPConvert)), ne);
  103. context.LoadFromContext();
  104. res = context.ZeroExtend16(OperandType.I64, res);
  105. context.Copy(GetVec(op.Rd), EmitVectorInsert(context, context.VectorZero(), res, 0, 1));
  106. }
  107. }
  108. else if (op.Size == 3 && op.Opc == 1) // Half -> Double.
  109. {
  110. if (Optimizations.UseF16c)
  111. {
  112. Operand n = GetVec(op.Rn);
  113. Operand res = context.AddIntrinsic(Intrinsic.X86Vcvtph2ps, GetVec(op.Rn));
  114. res = context.AddIntrinsic(Intrinsic.X86Cvtss2sd, context.VectorZero(), res);
  115. res = context.VectorZeroUpper64(res);
  116. context.Copy(GetVec(op.Rd), res);
  117. }
  118. else
  119. {
  120. Operand ne = EmitVectorExtractZx(context, op.Rn, 0, 1);
  121. context.StoreToContext();
  122. Operand res = context.Call(typeof(SoftFloat16_64).GetMethod(nameof(SoftFloat16_64.FPConvert)), ne);
  123. context.LoadFromContext();
  124. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  125. }
  126. }
  127. else // Invalid encoding.
  128. {
  129. Debug.Assert(false, $"type == {op.Size} && opc == {op.Opc}");
  130. }
  131. }
  132. public static void Fcvtas_Gp(ArmEmitterContext context)
  133. {
  134. EmitFcvt_s_Gp(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1));
  135. }
  136. public static void Fcvtas_S(ArmEmitterContext context)
  137. {
  138. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1), signed: true, scalar: true);
  139. }
  140. public static void Fcvtas_V(ArmEmitterContext context)
  141. {
  142. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1), signed: true, scalar: false);
  143. }
  144. public static void Fcvtau_Gp(ArmEmitterContext context)
  145. {
  146. EmitFcvt_u_Gp(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1));
  147. }
  148. public static void Fcvtau_S(ArmEmitterContext context)
  149. {
  150. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1), signed: false, scalar: true);
  151. }
  152. public static void Fcvtau_V(ArmEmitterContext context)
  153. {
  154. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1), signed: false, scalar: false);
  155. }
  156. public static void Fcvtl_V(ArmEmitterContext context)
  157. {
  158. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  159. int sizeF = op.Size & 1;
  160. if (Optimizations.UseSse2 && sizeF == 1)
  161. {
  162. Operand n = GetVec(op.Rn);
  163. Operand res = op.RegisterSize == RegisterSize.Simd128 ? context.AddIntrinsic(Intrinsic.X86Movhlps, n, n) : n;
  164. res = context.AddIntrinsic(Intrinsic.X86Cvtps2pd, res);
  165. context.Copy(GetVec(op.Rd), res);
  166. }
  167. else if (Optimizations.UseF16c && sizeF == 0)
  168. {
  169. Debug.Assert(!Optimizations.ForceLegacySse);
  170. Operand n = GetVec(op.Rn);
  171. Operand res = op.RegisterSize == RegisterSize.Simd128 ? context.AddIntrinsic(Intrinsic.X86Movhlps, n, n) : n;
  172. res = context.AddIntrinsic(Intrinsic.X86Vcvtph2ps, res);
  173. context.Copy(GetVec(op.Rd), res);
  174. }
  175. else
  176. {
  177. Operand res = context.VectorZero();
  178. int elems = 4 >> sizeF;
  179. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  180. for (int index = 0; index < elems; index++)
  181. {
  182. if (sizeF == 0)
  183. {
  184. Operand ne = EmitVectorExtractZx(context, op.Rn, part + index, 1);
  185. context.StoreToContext();
  186. Operand e = context.Call(typeof(SoftFloat16_32).GetMethod(nameof(SoftFloat16_32.FPConvert)), ne);
  187. context.LoadFromContext();
  188. res = context.VectorInsert(res, e, index);
  189. }
  190. else /* if (sizeF == 1) */
  191. {
  192. Operand ne = context.VectorExtract(OperandType.FP32, GetVec(op.Rn), part + index);
  193. Operand e = context.ConvertToFP(OperandType.FP64, ne);
  194. res = context.VectorInsert(res, e, index);
  195. }
  196. }
  197. context.Copy(GetVec(op.Rd), res);
  198. }
  199. }
  200. public static void Fcvtms_Gp(ArmEmitterContext context)
  201. {
  202. if (Optimizations.UseSse41)
  203. {
  204. EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsMinusInfinity, isFixed: false);
  205. }
  206. else
  207. {
  208. EmitFcvt_s_Gp(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Floor), op1));
  209. }
  210. }
  211. public static void Fcvtms_V(ArmEmitterContext context)
  212. {
  213. if (Optimizations.UseSse41)
  214. {
  215. EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsMinusInfinity, scalar: false);
  216. }
  217. else
  218. {
  219. EmitFcvt(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Floor), op1), signed: true, scalar: false);
  220. }
  221. }
  222. public static void Fcvtmu_Gp(ArmEmitterContext context)
  223. {
  224. if (Optimizations.UseSse41)
  225. {
  226. EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsMinusInfinity, isFixed: false);
  227. }
  228. else
  229. {
  230. EmitFcvt_u_Gp(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Floor), op1));
  231. }
  232. }
  233. public static void Fcvtn_V(ArmEmitterContext context)
  234. {
  235. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  236. int sizeF = op.Size & 1;
  237. if (Optimizations.UseSse2 && sizeF == 1)
  238. {
  239. Operand d = GetVec(op.Rd);
  240. Intrinsic movInst = op.RegisterSize == RegisterSize.Simd128 ? Intrinsic.X86Movlhps : Intrinsic.X86Movhlps;
  241. Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtpd2ps, GetVec(op.Rn));
  242. nInt = context.AddIntrinsic(Intrinsic.X86Movlhps, nInt, nInt);
  243. Operand res = context.VectorZeroUpper64(d);
  244. res = context.AddIntrinsic(movInst, res, nInt);
  245. context.Copy(d, res);
  246. }
  247. else if (Optimizations.UseF16c && sizeF == 0)
  248. {
  249. Debug.Assert(!Optimizations.ForceLegacySse);
  250. Operand d = GetVec(op.Rd);
  251. Operand n = GetVec(op.Rn);
  252. Intrinsic movInst = op.RegisterSize == RegisterSize.Simd128 ? Intrinsic.X86Movlhps : Intrinsic.X86Movhlps;
  253. Operand nInt = context.AddIntrinsic(Intrinsic.X86Vcvtps2ph, n, Const(X86GetRoundControl(FPRoundingMode.ToNearest)));
  254. nInt = context.AddIntrinsic(Intrinsic.X86Movlhps, nInt, nInt);
  255. Operand res = context.VectorZeroUpper64(d);
  256. res = context.AddIntrinsic(movInst, res, nInt);
  257. context.Copy(d, res);
  258. }
  259. else
  260. {
  261. OperandType type = sizeF == 0 ? OperandType.FP32 : OperandType.FP64;
  262. int elems = 4 >> sizeF;
  263. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  264. Operand d = GetVec(op.Rd);
  265. Operand res = part == 0 ? context.VectorZero() : context.Copy(d);
  266. for (int index = 0; index < elems; index++)
  267. {
  268. Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
  269. if (sizeF == 0)
  270. {
  271. context.StoreToContext();
  272. Operand e = context.Call(typeof(SoftFloat32_16).GetMethod(nameof(SoftFloat32_16.FPConvert)), ne);
  273. context.LoadFromContext();
  274. e = context.ZeroExtend16(OperandType.I64, e);
  275. res = EmitVectorInsert(context, res, e, part + index, 1);
  276. }
  277. else /* if (sizeF == 1) */
  278. {
  279. Operand e = context.ConvertToFP(OperandType.FP32, ne);
  280. res = context.VectorInsert(res, e, part + index);
  281. }
  282. }
  283. context.Copy(d, res);
  284. }
  285. }
  286. public static void Fcvtns_Gp(ArmEmitterContext context)
  287. {
  288. if (Optimizations.UseSse41)
  289. {
  290. EmitSse41Fcvts_Gp(context, FPRoundingMode.ToNearest, isFixed: false);
  291. }
  292. else
  293. {
  294. EmitFcvt_s_Gp(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1));
  295. }
  296. }
  297. public static void Fcvtns_S(ArmEmitterContext context)
  298. {
  299. if (Optimizations.UseSse41)
  300. {
  301. EmitSse41FcvtsOpF(context, FPRoundingMode.ToNearest, scalar: true);
  302. }
  303. else
  304. {
  305. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1), signed: true, scalar: true);
  306. }
  307. }
  308. public static void Fcvtns_V(ArmEmitterContext context)
  309. {
  310. if (Optimizations.UseSse41)
  311. {
  312. EmitSse41FcvtsOpF(context, FPRoundingMode.ToNearest, scalar: false);
  313. }
  314. else
  315. {
  316. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1), signed: true, scalar: false);
  317. }
  318. }
  319. public static void Fcvtnu_S(ArmEmitterContext context)
  320. {
  321. if (Optimizations.UseSse41)
  322. {
  323. EmitSse41FcvtuOpF(context, FPRoundingMode.ToNearest, scalar: true);
  324. }
  325. else
  326. {
  327. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1), signed: false, scalar: true);
  328. }
  329. }
  330. public static void Fcvtnu_V(ArmEmitterContext context)
  331. {
  332. if (Optimizations.UseSse41)
  333. {
  334. EmitSse41FcvtuOpF(context, FPRoundingMode.ToNearest, scalar: false);
  335. }
  336. else
  337. {
  338. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1), signed: false, scalar: false);
  339. }
  340. }
  341. public static void Fcvtps_Gp(ArmEmitterContext context)
  342. {
  343. if (Optimizations.UseSse41)
  344. {
  345. EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsPlusInfinity, isFixed: false);
  346. }
  347. else
  348. {
  349. EmitFcvt_s_Gp(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Ceiling), op1));
  350. }
  351. }
  352. public static void Fcvtpu_Gp(ArmEmitterContext context)
  353. {
  354. if (Optimizations.UseSse41)
  355. {
  356. EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsPlusInfinity, isFixed: false);
  357. }
  358. else
  359. {
  360. EmitFcvt_u_Gp(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Ceiling), op1));
  361. }
  362. }
  363. public static void Fcvtzs_Gp(ArmEmitterContext context)
  364. {
  365. if (Optimizations.UseSse41)
  366. {
  367. EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsZero, isFixed: false);
  368. }
  369. else
  370. {
  371. EmitFcvt_s_Gp(context, (op1) => op1);
  372. }
  373. }
  374. public static void Fcvtzs_Gp_Fixed(ArmEmitterContext context)
  375. {
  376. if (Optimizations.UseSse41)
  377. {
  378. EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsZero, isFixed: true);
  379. }
  380. else
  381. {
  382. EmitFcvtzs_Gp_Fixed(context);
  383. }
  384. }
  385. public static void Fcvtzs_S(ArmEmitterContext context)
  386. {
  387. if (Optimizations.UseSse41)
  388. {
  389. EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsZero, scalar: true);
  390. }
  391. else
  392. {
  393. EmitFcvtz(context, signed: true, scalar: true);
  394. }
  395. }
  396. public static void Fcvtzs_V(ArmEmitterContext context)
  397. {
  398. if (Optimizations.UseSse41)
  399. {
  400. EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsZero, scalar: false);
  401. }
  402. else
  403. {
  404. EmitFcvtz(context, signed: true, scalar: false);
  405. }
  406. }
  407. public static void Fcvtzs_V_Fixed(ArmEmitterContext context)
  408. {
  409. if (Optimizations.UseSse41)
  410. {
  411. EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsZero, scalar: false);
  412. }
  413. else
  414. {
  415. EmitFcvtz(context, signed: true, scalar: false);
  416. }
  417. }
  418. public static void Fcvtzu_Gp(ArmEmitterContext context)
  419. {
  420. if (Optimizations.UseSse41)
  421. {
  422. EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsZero, isFixed: false);
  423. }
  424. else
  425. {
  426. EmitFcvt_u_Gp(context, (op1) => op1);
  427. }
  428. }
  429. public static void Fcvtzu_Gp_Fixed(ArmEmitterContext context)
  430. {
  431. if (Optimizations.UseSse41)
  432. {
  433. EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsZero, isFixed: true);
  434. }
  435. else
  436. {
  437. EmitFcvtzu_Gp_Fixed(context);
  438. }
  439. }
  440. public static void Fcvtzu_S(ArmEmitterContext context)
  441. {
  442. if (Optimizations.UseSse41)
  443. {
  444. EmitSse41FcvtuOpF(context, FPRoundingMode.TowardsZero, scalar: true);
  445. }
  446. else
  447. {
  448. EmitFcvtz(context, signed: false, scalar: true);
  449. }
  450. }
  451. public static void Fcvtzu_V(ArmEmitterContext context)
  452. {
  453. if (Optimizations.UseSse41)
  454. {
  455. EmitSse41FcvtuOpF(context, FPRoundingMode.TowardsZero, scalar: false);
  456. }
  457. else
  458. {
  459. EmitFcvtz(context, signed: false, scalar: false);
  460. }
  461. }
  462. public static void Fcvtzu_V_Fixed(ArmEmitterContext context)
  463. {
  464. if (Optimizations.UseSse41)
  465. {
  466. EmitSse41FcvtuOpF(context, FPRoundingMode.TowardsZero, scalar: false);
  467. }
  468. else
  469. {
  470. EmitFcvtz(context, signed: false, scalar: false);
  471. }
  472. }
  473. public static void Scvtf_Gp(ArmEmitterContext context)
  474. {
  475. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  476. Operand res = GetIntOrZR(context, op.Rn);
  477. if (op.RegisterSize == RegisterSize.Int32)
  478. {
  479. res = context.SignExtend32(OperandType.I64, res);
  480. }
  481. res = EmitFPConvert(context, res, op.Size, signed: true);
  482. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  483. }
  484. public static void Scvtf_Gp_Fixed(ArmEmitterContext context)
  485. {
  486. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  487. Operand res = GetIntOrZR(context, op.Rn);
  488. if (op.RegisterSize == RegisterSize.Int32)
  489. {
  490. res = context.SignExtend32(OperandType.I64, res);
  491. }
  492. res = EmitFPConvert(context, res, op.Size, signed: true);
  493. res = EmitI2fFBitsMul(context, res, op.FBits);
  494. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  495. }
  496. public static void Scvtf_S(ArmEmitterContext context)
  497. {
  498. if (Optimizations.UseSse2)
  499. {
  500. EmitSse2ScvtfOp(context, scalar: true);
  501. }
  502. else
  503. {
  504. EmitCvtf(context, signed: true, scalar: true);
  505. }
  506. }
  507. public static void Scvtf_S_Fixed(ArmEmitterContext context)
  508. {
  509. if (Optimizations.UseSse2)
  510. {
  511. EmitSse2ScvtfOp(context, scalar: true);
  512. }
  513. else
  514. {
  515. EmitCvtf(context, signed: true, scalar: true);
  516. }
  517. }
  518. public static void Scvtf_V(ArmEmitterContext context)
  519. {
  520. if (Optimizations.UseSse2)
  521. {
  522. EmitSse2ScvtfOp(context, scalar: false);
  523. }
  524. else
  525. {
  526. EmitCvtf(context, signed: true, scalar: false);
  527. }
  528. }
  529. public static void Scvtf_V_Fixed(ArmEmitterContext context)
  530. {
  531. if (Optimizations.UseSse2)
  532. {
  533. EmitSse2ScvtfOp(context, scalar: false);
  534. }
  535. else
  536. {
  537. EmitCvtf(context, signed: true, scalar: false);
  538. }
  539. }
  540. public static void Ucvtf_Gp(ArmEmitterContext context)
  541. {
  542. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  543. Operand res = GetIntOrZR(context, op.Rn);
  544. res = EmitFPConvert(context, res, op.Size, signed: false);
  545. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  546. }
  547. public static void Ucvtf_Gp_Fixed(ArmEmitterContext context)
  548. {
  549. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  550. Operand res = GetIntOrZR(context, op.Rn);
  551. res = EmitFPConvert(context, res, op.Size, signed: false);
  552. res = EmitI2fFBitsMul(context, res, op.FBits);
  553. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  554. }
  555. public static void Ucvtf_S(ArmEmitterContext context)
  556. {
  557. if (Optimizations.UseSse2)
  558. {
  559. EmitSse2UcvtfOp(context, scalar: true);
  560. }
  561. else
  562. {
  563. EmitCvtf(context, signed: false, scalar: true);
  564. }
  565. }
  566. public static void Ucvtf_S_Fixed(ArmEmitterContext context)
  567. {
  568. if (Optimizations.UseSse2)
  569. {
  570. EmitSse2UcvtfOp(context, scalar: true);
  571. }
  572. else
  573. {
  574. EmitCvtf(context, signed: false, scalar: true);
  575. }
  576. }
  577. public static void Ucvtf_V(ArmEmitterContext context)
  578. {
  579. if (Optimizations.UseSse2)
  580. {
  581. EmitSse2UcvtfOp(context, scalar: false);
  582. }
  583. else
  584. {
  585. EmitCvtf(context, signed: false, scalar: false);
  586. }
  587. }
  588. public static void Ucvtf_V_Fixed(ArmEmitterContext context)
  589. {
  590. if (Optimizations.UseSse2)
  591. {
  592. EmitSse2UcvtfOp(context, scalar: false);
  593. }
  594. else
  595. {
  596. EmitCvtf(context, signed: false, scalar: false);
  597. }
  598. }
  599. private static void EmitFcvt(ArmEmitterContext context, Func1I emit, bool signed, bool scalar)
  600. {
  601. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  602. Operand res = context.VectorZero();
  603. Operand n = GetVec(op.Rn);
  604. int sizeF = op.Size & 1;
  605. int sizeI = sizeF + 2;
  606. OperandType type = sizeF == 0 ? OperandType.FP32 : OperandType.FP64;
  607. int elems = !scalar ? op.GetBytesCount() >> sizeI : 1;
  608. for (int index = 0; index < elems; index++)
  609. {
  610. Operand ne = context.VectorExtract(type, n, index);
  611. Operand e = emit(ne);
  612. if (sizeF == 0)
  613. {
  614. MethodInfo info = signed
  615. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS32))
  616. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU32));
  617. e = context.Call(info, e);
  618. e = context.ZeroExtend32(OperandType.I64, e);
  619. }
  620. else /* if (sizeF == 1) */
  621. {
  622. MethodInfo info = signed
  623. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS64))
  624. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU64));
  625. e = context.Call(info, e);
  626. }
  627. res = EmitVectorInsert(context, res, e, index, sizeI);
  628. }
  629. context.Copy(GetVec(op.Rd), res);
  630. }
  631. private static void EmitFcvtz(ArmEmitterContext context, bool signed, bool scalar)
  632. {
  633. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  634. Operand res = context.VectorZero();
  635. Operand n = GetVec(op.Rn);
  636. int sizeF = op.Size & 1;
  637. int sizeI = sizeF + 2;
  638. OperandType type = sizeF == 0 ? OperandType.FP32 : OperandType.FP64;
  639. int fBits = GetFBits(context);
  640. int elems = !scalar ? op.GetBytesCount() >> sizeI : 1;
  641. for (int index = 0; index < elems; index++)
  642. {
  643. Operand ne = context.VectorExtract(type, n, index);
  644. Operand e = EmitF2iFBitsMul(context, ne, fBits);
  645. if (sizeF == 0)
  646. {
  647. MethodInfo info = signed
  648. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS32))
  649. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU32));
  650. e = context.Call(info, e);
  651. e = context.ZeroExtend32(OperandType.I64, e);
  652. }
  653. else /* if (sizeF == 1) */
  654. {
  655. MethodInfo info = signed
  656. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS64))
  657. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU64));
  658. e = context.Call(info, e);
  659. }
  660. res = EmitVectorInsert(context, res, e, index, sizeI);
  661. }
  662. context.Copy(GetVec(op.Rd), res);
  663. }
  664. private static void EmitFcvt_s_Gp(ArmEmitterContext context, Func1I emit)
  665. {
  666. EmitFcvt___Gp(context, emit, signed: true);
  667. }
  668. private static void EmitFcvt_u_Gp(ArmEmitterContext context, Func1I emit)
  669. {
  670. EmitFcvt___Gp(context, emit, signed: false);
  671. }
  672. private static void EmitFcvt___Gp(ArmEmitterContext context, Func1I emit, bool signed)
  673. {
  674. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  675. OperandType type = op.Size == 0 ? OperandType.FP32 : OperandType.FP64;
  676. Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
  677. Operand res = signed
  678. ? EmitScalarFcvts(context, emit(ne), 0)
  679. : EmitScalarFcvtu(context, emit(ne), 0);
  680. SetIntOrZR(context, op.Rd, res);
  681. }
  682. private static void EmitFcvtzs_Gp_Fixed(ArmEmitterContext context)
  683. {
  684. EmitFcvtz__Gp_Fixed(context, signed: true);
  685. }
  686. private static void EmitFcvtzu_Gp_Fixed(ArmEmitterContext context)
  687. {
  688. EmitFcvtz__Gp_Fixed(context, signed: false);
  689. }
  690. private static void EmitFcvtz__Gp_Fixed(ArmEmitterContext context, bool signed)
  691. {
  692. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  693. OperandType type = op.Size == 0 ? OperandType.FP32 : OperandType.FP64;
  694. Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
  695. Operand res = signed
  696. ? EmitScalarFcvts(context, ne, op.FBits)
  697. : EmitScalarFcvtu(context, ne, op.FBits);
  698. SetIntOrZR(context, op.Rd, res);
  699. }
  700. private static void EmitCvtf(ArmEmitterContext context, bool signed, bool scalar)
  701. {
  702. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  703. Operand res = context.VectorZero();
  704. int sizeF = op.Size & 1;
  705. int sizeI = sizeF + 2;
  706. int fBits = GetFBits(context);
  707. int elems = !scalar ? op.GetBytesCount() >> sizeI : 1;
  708. for (int index = 0; index < elems; index++)
  709. {
  710. Operand ne = EmitVectorLongExtract(context, op.Rn, index, sizeI);
  711. Operand e = EmitFPConvert(context, ne, sizeF, signed);
  712. e = EmitI2fFBitsMul(context, e, fBits);
  713. res = context.VectorInsert(res, e, index);
  714. }
  715. context.Copy(GetVec(op.Rd), res);
  716. }
  717. private static int GetFBits(ArmEmitterContext context)
  718. {
  719. if (context.CurrOp is OpCodeSimdShImm op)
  720. {
  721. return GetImmShr(op);
  722. }
  723. return 0;
  724. }
  725. private static Operand EmitFPConvert(ArmEmitterContext context, Operand value, int size, bool signed)
  726. {
  727. Debug.Assert(value.Type == OperandType.I32 || value.Type == OperandType.I64);
  728. Debug.Assert((uint)size < 2);
  729. OperandType type = size == 0 ? OperandType.FP32 : OperandType.FP64;
  730. if (signed)
  731. {
  732. return context.ConvertToFP(type, value);
  733. }
  734. else
  735. {
  736. return context.ConvertToFPUI(type, value);
  737. }
  738. }
  739. private static Operand EmitScalarFcvts(ArmEmitterContext context, Operand value, int fBits)
  740. {
  741. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  742. value = EmitF2iFBitsMul(context, value, fBits);
  743. MethodInfo info;
  744. if (context.CurrOp.RegisterSize == RegisterSize.Int32)
  745. {
  746. info = value.Type == OperandType.FP32
  747. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS32))
  748. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS32));
  749. }
  750. else
  751. {
  752. info = value.Type == OperandType.FP32
  753. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS64))
  754. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS64));
  755. }
  756. return context.Call(info, value);
  757. }
  758. private static Operand EmitScalarFcvtu(ArmEmitterContext context, Operand value, int fBits)
  759. {
  760. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  761. value = EmitF2iFBitsMul(context, value, fBits);
  762. MethodInfo info;
  763. if (context.CurrOp.RegisterSize == RegisterSize.Int32)
  764. {
  765. info = value.Type == OperandType.FP32
  766. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU32))
  767. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU32));
  768. }
  769. else
  770. {
  771. info = value.Type == OperandType.FP32
  772. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU64))
  773. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU64));
  774. }
  775. return context.Call(info, value);
  776. }
  777. private static Operand EmitF2iFBitsMul(ArmEmitterContext context, Operand value, int fBits)
  778. {
  779. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  780. if (fBits == 0)
  781. {
  782. return value;
  783. }
  784. if (value.Type == OperandType.FP32)
  785. {
  786. return context.Multiply(value, ConstF(MathF.Pow(2f, fBits)));
  787. }
  788. else /* if (value.Type == OperandType.FP64) */
  789. {
  790. return context.Multiply(value, ConstF(Math.Pow(2d, fBits)));
  791. }
  792. }
  793. private static Operand EmitI2fFBitsMul(ArmEmitterContext context, Operand value, int fBits)
  794. {
  795. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  796. if (fBits == 0)
  797. {
  798. return value;
  799. }
  800. if (value.Type == OperandType.FP32)
  801. {
  802. return context.Multiply(value, ConstF(1f / MathF.Pow(2f, fBits)));
  803. }
  804. else /* if (value.Type == OperandType.FP64) */
  805. {
  806. return context.Multiply(value, ConstF(1d / Math.Pow(2d, fBits)));
  807. }
  808. }
  809. public static Operand EmitSse2CvtDoubleToInt64OpF(ArmEmitterContext context, Operand opF, bool scalar)
  810. {
  811. Debug.Assert(opF.Type == OperandType.V128);
  812. Operand longL = context.AddIntrinsicLong (Intrinsic.X86Cvtsd2si, opF); // opFL
  813. Operand res = context.VectorCreateScalar(longL);
  814. if (!scalar)
  815. {
  816. Operand opFH = context.AddIntrinsic (Intrinsic.X86Movhlps, res, opF); // res doesn't matter.
  817. Operand longH = context.AddIntrinsicLong (Intrinsic.X86Cvtsd2si, opFH);
  818. Operand resH = context.VectorCreateScalar(longH);
  819. res = context.AddIntrinsic (Intrinsic.X86Movlhps, res, resH);
  820. }
  821. return res;
  822. }
  823. private static Operand EmitSse2CvtInt64ToDoubleOp(ArmEmitterContext context, Operand op, bool scalar)
  824. {
  825. Debug.Assert(op.Type == OperandType.V128);
  826. Operand longL = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, op); // opL
  827. Operand res = context.AddIntrinsic (Intrinsic.X86Cvtsi2sd, context.VectorZero(), longL);
  828. if (!scalar)
  829. {
  830. Operand opH = context.AddIntrinsic (Intrinsic.X86Movhlps, res, op); // res doesn't matter.
  831. Operand longH = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, opH);
  832. Operand resH = context.AddIntrinsic (Intrinsic.X86Cvtsi2sd, res, longH); // res doesn't matter.
  833. res = context.AddIntrinsic (Intrinsic.X86Movlhps, res, resH);
  834. }
  835. return res;
  836. }
  837. private static void EmitSse2ScvtfOp(ArmEmitterContext context, bool scalar)
  838. {
  839. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  840. Operand n = GetVec(op.Rn);
  841. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  842. int sizeF = op.Size & 1;
  843. if (sizeF == 0)
  844. {
  845. Operand res = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, n);
  846. if (op is OpCodeSimdShImm fixedOp)
  847. {
  848. int fBits = GetImmShr(fixedOp);
  849. // BitConverter.Int32BitsToSingle(fpScaled) == 1f / MathF.Pow(2f, fBits)
  850. int fpScaled = 0x3F800000 - fBits * 0x800000;
  851. Operand fpScaledMask = scalar
  852. ? X86GetScalar (context, fpScaled)
  853. : X86GetAllElements(context, fpScaled);
  854. res = context.AddIntrinsic(Intrinsic.X86Mulps, res, fpScaledMask);
  855. }
  856. if (scalar)
  857. {
  858. res = context.VectorZeroUpper96(res);
  859. }
  860. else if (op.RegisterSize == RegisterSize.Simd64)
  861. {
  862. res = context.VectorZeroUpper64(res);
  863. }
  864. context.Copy(GetVec(op.Rd), res);
  865. }
  866. else /* if (sizeF == 1) */
  867. {
  868. Operand res = EmitSse2CvtInt64ToDoubleOp(context, n, scalar);
  869. if (op is OpCodeSimdShImm fixedOp)
  870. {
  871. int fBits = GetImmShr(fixedOp);
  872. // BitConverter.Int64BitsToDouble(fpScaled) == 1d / Math.Pow(2d, fBits)
  873. long fpScaled = 0x3FF0000000000000L - fBits * 0x10000000000000L;
  874. Operand fpScaledMask = scalar
  875. ? X86GetScalar (context, fpScaled)
  876. : X86GetAllElements(context, fpScaled);
  877. res = context.AddIntrinsic(Intrinsic.X86Mulpd, res, fpScaledMask);
  878. }
  879. if (scalar)
  880. {
  881. res = context.VectorZeroUpper64(res);
  882. }
  883. context.Copy(GetVec(op.Rd), res);
  884. }
  885. }
  886. private static void EmitSse2UcvtfOp(ArmEmitterContext context, bool scalar)
  887. {
  888. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  889. Operand n = GetVec(op.Rn);
  890. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  891. int sizeF = op.Size & 1;
  892. if (sizeF == 0)
  893. {
  894. Operand mask = scalar // 65536.000f (1 << 16)
  895. ? X86GetScalar (context, 0x47800000)
  896. : X86GetAllElements(context, 0x47800000);
  897. Operand res = context.AddIntrinsic(Intrinsic.X86Psrld, n, Const(16));
  898. res = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res);
  899. res = context.AddIntrinsic(Intrinsic.X86Mulps, res, mask);
  900. Operand res2 = context.AddIntrinsic(Intrinsic.X86Pslld, n, Const(16));
  901. res2 = context.AddIntrinsic(Intrinsic.X86Psrld, res2, Const(16));
  902. res2 = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res2);
  903. res = context.AddIntrinsic(Intrinsic.X86Addps, res, res2);
  904. if (op is OpCodeSimdShImm fixedOp)
  905. {
  906. int fBits = GetImmShr(fixedOp);
  907. // BitConverter.Int32BitsToSingle(fpScaled) == 1f / MathF.Pow(2f, fBits)
  908. int fpScaled = 0x3F800000 - fBits * 0x800000;
  909. Operand fpScaledMask = scalar
  910. ? X86GetScalar (context, fpScaled)
  911. : X86GetAllElements(context, fpScaled);
  912. res = context.AddIntrinsic(Intrinsic.X86Mulps, res, fpScaledMask);
  913. }
  914. if (scalar)
  915. {
  916. res = context.VectorZeroUpper96(res);
  917. }
  918. else if (op.RegisterSize == RegisterSize.Simd64)
  919. {
  920. res = context.VectorZeroUpper64(res);
  921. }
  922. context.Copy(GetVec(op.Rd), res);
  923. }
  924. else /* if (sizeF == 1) */
  925. {
  926. Operand mask = scalar // 4294967296.0000000d (1L << 32)
  927. ? X86GetScalar (context, 0x41F0000000000000L)
  928. : X86GetAllElements(context, 0x41F0000000000000L);
  929. Operand res = context.AddIntrinsic (Intrinsic.X86Psrlq, n, Const(32));
  930. res = EmitSse2CvtInt64ToDoubleOp(context, res, scalar);
  931. res = context.AddIntrinsic (Intrinsic.X86Mulpd, res, mask);
  932. Operand res2 = context.AddIntrinsic (Intrinsic.X86Psllq, n, Const(32));
  933. res2 = context.AddIntrinsic (Intrinsic.X86Psrlq, res2, Const(32));
  934. res2 = EmitSse2CvtInt64ToDoubleOp(context, res2, scalar);
  935. res = context.AddIntrinsic(Intrinsic.X86Addpd, res, res2);
  936. if (op is OpCodeSimdShImm fixedOp)
  937. {
  938. int fBits = GetImmShr(fixedOp);
  939. // BitConverter.Int64BitsToDouble(fpScaled) == 1d / Math.Pow(2d, fBits)
  940. long fpScaled = 0x3FF0000000000000L - fBits * 0x10000000000000L;
  941. Operand fpScaledMask = scalar
  942. ? X86GetScalar (context, fpScaled)
  943. : X86GetAllElements(context, fpScaled);
  944. res = context.AddIntrinsic(Intrinsic.X86Mulpd, res, fpScaledMask);
  945. }
  946. if (scalar)
  947. {
  948. res = context.VectorZeroUpper64(res);
  949. }
  950. context.Copy(GetVec(op.Rd), res);
  951. }
  952. }
  953. private static void EmitSse41FcvtsOpF(ArmEmitterContext context, FPRoundingMode roundMode, bool scalar)
  954. {
  955. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  956. Operand n = GetVec(op.Rn);
  957. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  958. int sizeF = op.Size & 1;
  959. if (sizeF == 0)
  960. {
  961. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, n, n, Const((int)CmpCondition.OrderedQ));
  962. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  963. if (op is OpCodeSimdShImm fixedOp)
  964. {
  965. int fBits = GetImmShr(fixedOp);
  966. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, fBits)
  967. int fpScaled = 0x3F800000 + fBits * 0x800000;
  968. Operand fpScaledMask = scalar
  969. ? X86GetScalar (context, fpScaled)
  970. : X86GetAllElements(context, fpScaled);
  971. nRes = context.AddIntrinsic(Intrinsic.X86Mulps, nRes, fpScaledMask);
  972. }
  973. nRes = context.AddIntrinsic(Intrinsic.X86Roundps, nRes, Const(X86GetRoundControl(roundMode)));
  974. Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes);
  975. Operand fpMaxValMask = scalar // 2.14748365E9f (2147483648)
  976. ? X86GetScalar (context, 0x4F000000)
  977. : X86GetAllElements(context, 0x4F000000);
  978. nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  979. Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nInt, nRes);
  980. if (scalar)
  981. {
  982. dRes = context.VectorZeroUpper96(dRes);
  983. }
  984. else if (op.RegisterSize == RegisterSize.Simd64)
  985. {
  986. dRes = context.VectorZeroUpper64(dRes);
  987. }
  988. context.Copy(GetVec(op.Rd), dRes);
  989. }
  990. else /* if (sizeF == 1) */
  991. {
  992. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, n, n, Const((int)CmpCondition.OrderedQ));
  993. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  994. if (op is OpCodeSimdShImm fixedOp)
  995. {
  996. int fBits = GetImmShr(fixedOp);
  997. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, fBits)
  998. long fpScaled = 0x3FF0000000000000L + fBits * 0x10000000000000L;
  999. Operand fpScaledMask = scalar
  1000. ? X86GetScalar (context, fpScaled)
  1001. : X86GetAllElements(context, fpScaled);
  1002. nRes = context.AddIntrinsic(Intrinsic.X86Mulpd, nRes, fpScaledMask);
  1003. }
  1004. nRes = context.AddIntrinsic(Intrinsic.X86Roundpd, nRes, Const(X86GetRoundControl(roundMode)));
  1005. Operand nLong = EmitSse2CvtDoubleToInt64OpF(context, nRes, scalar);
  1006. Operand fpMaxValMask = scalar // 9.2233720368547760E18d (9223372036854775808)
  1007. ? X86GetScalar (context, 0x43E0000000000000L)
  1008. : X86GetAllElements(context, 0x43E0000000000000L);
  1009. nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1010. Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nLong, nRes);
  1011. if (scalar)
  1012. {
  1013. dRes = context.VectorZeroUpper64(dRes);
  1014. }
  1015. context.Copy(GetVec(op.Rd), dRes);
  1016. }
  1017. }
  1018. private static void EmitSse41FcvtuOpF(ArmEmitterContext context, FPRoundingMode roundMode, bool scalar)
  1019. {
  1020. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  1021. Operand n = GetVec(op.Rn);
  1022. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  1023. int sizeF = op.Size & 1;
  1024. if (sizeF == 0)
  1025. {
  1026. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, n, n, Const((int)CmpCondition.OrderedQ));
  1027. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1028. if (op is OpCodeSimdShImm fixedOp)
  1029. {
  1030. int fBits = GetImmShr(fixedOp);
  1031. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, fBits)
  1032. int fpScaled = 0x3F800000 + fBits * 0x800000;
  1033. Operand fpScaledMask = scalar
  1034. ? X86GetScalar (context, fpScaled)
  1035. : X86GetAllElements(context, fpScaled);
  1036. nRes = context.AddIntrinsic(Intrinsic.X86Mulps, nRes, fpScaledMask);
  1037. }
  1038. nRes = context.AddIntrinsic(Intrinsic.X86Roundps, nRes, Const(X86GetRoundControl(roundMode)));
  1039. Operand zero = context.VectorZero();
  1040. Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1041. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1042. Operand fpMaxValMask = scalar // 2.14748365E9f (2147483648)
  1043. ? X86GetScalar (context, 0x4F000000)
  1044. : X86GetAllElements(context, 0x4F000000);
  1045. Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes);
  1046. nRes = context.AddIntrinsic(Intrinsic.X86Subps, nRes, fpMaxValMask);
  1047. nCmp = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1048. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1049. Operand nInt2 = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes);
  1050. nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1051. Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nInt2, nRes);
  1052. dRes = context.AddIntrinsic(Intrinsic.X86Paddd, dRes, nInt);
  1053. if (scalar)
  1054. {
  1055. dRes = context.VectorZeroUpper96(dRes);
  1056. }
  1057. else if (op.RegisterSize == RegisterSize.Simd64)
  1058. {
  1059. dRes = context.VectorZeroUpper64(dRes);
  1060. }
  1061. context.Copy(GetVec(op.Rd), dRes);
  1062. }
  1063. else /* if (sizeF == 1) */
  1064. {
  1065. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, n, n, Const((int)CmpCondition.OrderedQ));
  1066. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1067. if (op is OpCodeSimdShImm fixedOp)
  1068. {
  1069. int fBits = GetImmShr(fixedOp);
  1070. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, fBits)
  1071. long fpScaled = 0x3FF0000000000000L + fBits * 0x10000000000000L;
  1072. Operand fpScaledMask = scalar
  1073. ? X86GetScalar (context, fpScaled)
  1074. : X86GetAllElements(context, fpScaled);
  1075. nRes = context.AddIntrinsic(Intrinsic.X86Mulpd, nRes, fpScaledMask);
  1076. }
  1077. nRes = context.AddIntrinsic(Intrinsic.X86Roundpd, nRes, Const(X86GetRoundControl(roundMode)));
  1078. Operand zero = context.VectorZero();
  1079. Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1080. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1081. Operand fpMaxValMask = scalar // 9.2233720368547760E18d (9223372036854775808)
  1082. ? X86GetScalar (context, 0x43E0000000000000L)
  1083. : X86GetAllElements(context, 0x43E0000000000000L);
  1084. Operand nLong = EmitSse2CvtDoubleToInt64OpF(context, nRes, scalar);
  1085. nRes = context.AddIntrinsic(Intrinsic.X86Subpd, nRes, fpMaxValMask);
  1086. nCmp = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1087. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1088. Operand nLong2 = EmitSse2CvtDoubleToInt64OpF(context, nRes, scalar);
  1089. nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1090. Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nLong2, nRes);
  1091. dRes = context.AddIntrinsic(Intrinsic.X86Paddq, dRes, nLong);
  1092. if (scalar)
  1093. {
  1094. dRes = context.VectorZeroUpper64(dRes);
  1095. }
  1096. context.Copy(GetVec(op.Rd), dRes);
  1097. }
  1098. }
  1099. private static void EmitSse41Fcvts_Gp(ArmEmitterContext context, FPRoundingMode roundMode, bool isFixed)
  1100. {
  1101. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  1102. Operand n = GetVec(op.Rn);
  1103. if (op.Size == 0)
  1104. {
  1105. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, n, n, Const((int)CmpCondition.OrderedQ));
  1106. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1107. if (isFixed)
  1108. {
  1109. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, op.FBits)
  1110. int fpScaled = 0x3F800000 + op.FBits * 0x800000;
  1111. Operand fpScaledMask = X86GetScalar(context, fpScaled);
  1112. nRes = context.AddIntrinsic(Intrinsic.X86Mulss, nRes, fpScaledMask);
  1113. }
  1114. nRes = context.AddIntrinsic(Intrinsic.X86Roundss, nRes, Const(X86GetRoundControl(roundMode)));
  1115. Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
  1116. ? context.AddIntrinsicInt (Intrinsic.X86Cvtss2si, nRes)
  1117. : context.AddIntrinsicLong(Intrinsic.X86Cvtss2si, nRes);
  1118. int fpMaxVal = op.RegisterSize == RegisterSize.Int32
  1119. ? 0x4F000000 // 2.14748365E9f (2147483648)
  1120. : 0x5F000000; // 9.223372E18f (9223372036854775808)
  1121. Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
  1122. nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1123. Operand nInt = context.AddIntrinsicInt(Intrinsic.X86Cvtsi2si, nRes);
  1124. if (op.RegisterSize == RegisterSize.Int64)
  1125. {
  1126. nInt = context.SignExtend32(OperandType.I64, nInt);
  1127. }
  1128. Operand dRes = context.BitwiseExclusiveOr(nIntOrLong, nInt);
  1129. SetIntOrZR(context, op.Rd, dRes);
  1130. }
  1131. else /* if (op.Size == 1) */
  1132. {
  1133. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, n, n, Const((int)CmpCondition.OrderedQ));
  1134. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1135. if (isFixed)
  1136. {
  1137. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, op.FBits)
  1138. long fpScaled = 0x3FF0000000000000L + op.FBits * 0x10000000000000L;
  1139. Operand fpScaledMask = X86GetScalar(context, fpScaled);
  1140. nRes = context.AddIntrinsic(Intrinsic.X86Mulsd, nRes, fpScaledMask);
  1141. }
  1142. nRes = context.AddIntrinsic(Intrinsic.X86Roundsd, nRes, Const(X86GetRoundControl(roundMode)));
  1143. Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
  1144. ? context.AddIntrinsicInt (Intrinsic.X86Cvtsd2si, nRes)
  1145. : context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRes);
  1146. long fpMaxVal = op.RegisterSize == RegisterSize.Int32
  1147. ? 0x41E0000000000000L // 2147483648.0000000d (2147483648)
  1148. : 0x43E0000000000000L; // 9.2233720368547760E18d (9223372036854775808)
  1149. Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
  1150. nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1151. Operand nLong = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, nRes);
  1152. if (op.RegisterSize == RegisterSize.Int32)
  1153. {
  1154. nLong = context.ConvertI64ToI32(nLong);
  1155. }
  1156. Operand dRes = context.BitwiseExclusiveOr(nIntOrLong, nLong);
  1157. SetIntOrZR(context, op.Rd, dRes);
  1158. }
  1159. }
  1160. private static void EmitSse41Fcvtu_Gp(ArmEmitterContext context, FPRoundingMode roundMode, bool isFixed)
  1161. {
  1162. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  1163. Operand n = GetVec(op.Rn);
  1164. if (op.Size == 0)
  1165. {
  1166. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, n, n, Const((int)CmpCondition.OrderedQ));
  1167. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1168. if (isFixed)
  1169. {
  1170. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, op.FBits)
  1171. int fpScaled = 0x3F800000 + op.FBits * 0x800000;
  1172. Operand fpScaledMask = X86GetScalar(context, fpScaled);
  1173. nRes = context.AddIntrinsic(Intrinsic.X86Mulss, nRes, fpScaledMask);
  1174. }
  1175. nRes = context.AddIntrinsic(Intrinsic.X86Roundss, nRes, Const(X86GetRoundControl(roundMode)));
  1176. Operand zero = context.VectorZero();
  1177. Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1178. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1179. int fpMaxVal = op.RegisterSize == RegisterSize.Int32
  1180. ? 0x4F000000 // 2.14748365E9f (2147483648)
  1181. : 0x5F000000; // 9.223372E18f (9223372036854775808)
  1182. Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
  1183. Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
  1184. ? context.AddIntrinsicInt (Intrinsic.X86Cvtss2si, nRes)
  1185. : context.AddIntrinsicLong(Intrinsic.X86Cvtss2si, nRes);
  1186. nRes = context.AddIntrinsic(Intrinsic.X86Subss, nRes, fpMaxValMask);
  1187. nCmp = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1188. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1189. Operand nIntOrLong2 = op.RegisterSize == RegisterSize.Int32
  1190. ? context.AddIntrinsicInt (Intrinsic.X86Cvtss2si, nRes)
  1191. : context.AddIntrinsicLong(Intrinsic.X86Cvtss2si, nRes);
  1192. nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1193. Operand nInt = context.AddIntrinsicInt(Intrinsic.X86Cvtsi2si, nRes);
  1194. if (op.RegisterSize == RegisterSize.Int64)
  1195. {
  1196. nInt = context.SignExtend32(OperandType.I64, nInt);
  1197. }
  1198. Operand dRes = context.BitwiseExclusiveOr(nIntOrLong2, nInt);
  1199. dRes = context.Add(dRes, nIntOrLong);
  1200. SetIntOrZR(context, op.Rd, dRes);
  1201. }
  1202. else /* if (op.Size == 1) */
  1203. {
  1204. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, n, n, Const((int)CmpCondition.OrderedQ));
  1205. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1206. if (isFixed)
  1207. {
  1208. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, op.FBits)
  1209. long fpScaled = 0x3FF0000000000000L + op.FBits * 0x10000000000000L;
  1210. Operand fpScaledMask = X86GetScalar(context, fpScaled);
  1211. nRes = context.AddIntrinsic(Intrinsic.X86Mulsd, nRes, fpScaledMask);
  1212. }
  1213. nRes = context.AddIntrinsic(Intrinsic.X86Roundsd, nRes, Const(X86GetRoundControl(roundMode)));
  1214. Operand zero = context.VectorZero();
  1215. Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1216. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1217. long fpMaxVal = op.RegisterSize == RegisterSize.Int32
  1218. ? 0x41E0000000000000L // 2147483648.0000000d (2147483648)
  1219. : 0x43E0000000000000L; // 9.2233720368547760E18d (9223372036854775808)
  1220. Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
  1221. Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
  1222. ? context.AddIntrinsicInt (Intrinsic.X86Cvtsd2si, nRes)
  1223. : context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRes);
  1224. nRes = context.AddIntrinsic(Intrinsic.X86Subsd, nRes, fpMaxValMask);
  1225. nCmp = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1226. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1227. Operand nIntOrLong2 = op.RegisterSize == RegisterSize.Int32
  1228. ? context.AddIntrinsicInt (Intrinsic.X86Cvtsd2si, nRes)
  1229. : context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRes);
  1230. nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1231. Operand nLong = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, nRes);
  1232. if (op.RegisterSize == RegisterSize.Int32)
  1233. {
  1234. nLong = context.ConvertI64ToI32(nLong);
  1235. }
  1236. Operand dRes = context.BitwiseExclusiveOr(nIntOrLong2, nLong);
  1237. dRes = context.Add(dRes, nIntOrLong);
  1238. SetIntOrZR(context, op.Rd, dRes);
  1239. }
  1240. }
  1241. private static Operand EmitVectorLongExtract(ArmEmitterContext context, int reg, int index, int size)
  1242. {
  1243. OperandType type = size == 3 ? OperandType.I64 : OperandType.I32;
  1244. return context.VectorExtract(type, GetVec(reg), index);
  1245. }
  1246. }
  1247. }