InstEmitSimdHelper.cs 54 KB

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  1. using ARMeilleure.Decoders;
  2. using ARMeilleure.IntermediateRepresentation;
  3. using ARMeilleure.State;
  4. using ARMeilleure.Translation;
  5. using System;
  6. using System.Diagnostics;
  7. using static ARMeilleure.Instructions.InstEmitHelper;
  8. using static ARMeilleure.IntermediateRepresentation.OperandHelper;
  9. namespace ARMeilleure.Instructions
  10. {
  11. using Func1I = Func<Operand, Operand>;
  12. using Func2I = Func<Operand, Operand, Operand>;
  13. using Func3I = Func<Operand, Operand, Operand, Operand>;
  14. static class InstEmitSimdHelper
  15. {
  16. #region "Masks"
  17. public static readonly long[] EvenMasks = new long[]
  18. {
  19. 14L << 56 | 12L << 48 | 10L << 40 | 08L << 32 | 06L << 24 | 04L << 16 | 02L << 8 | 00L << 0, // B
  20. 13L << 56 | 12L << 48 | 09L << 40 | 08L << 32 | 05L << 24 | 04L << 16 | 01L << 8 | 00L << 0, // H
  21. 11L << 56 | 10L << 48 | 09L << 40 | 08L << 32 | 03L << 24 | 02L << 16 | 01L << 8 | 00L << 0 // S
  22. };
  23. public static readonly long[] OddMasks = new long[]
  24. {
  25. 15L << 56 | 13L << 48 | 11L << 40 | 09L << 32 | 07L << 24 | 05L << 16 | 03L << 8 | 01L << 0, // B
  26. 15L << 56 | 14L << 48 | 11L << 40 | 10L << 32 | 07L << 24 | 06L << 16 | 03L << 8 | 02L << 0, // H
  27. 15L << 56 | 14L << 48 | 13L << 40 | 12L << 32 | 07L << 24 | 06L << 16 | 05L << 8 | 04L << 0 // S
  28. };
  29. private static readonly long _zeroMask = 128L << 56 | 128L << 48 | 128L << 40 | 128L << 32 | 128L << 24 | 128L << 16 | 128L << 8 | 128L << 0;
  30. #endregion
  31. #region "X86 SSE Intrinsics"
  32. public static readonly Intrinsic[] X86PaddInstruction = new Intrinsic[]
  33. {
  34. Intrinsic.X86Paddb,
  35. Intrinsic.X86Paddw,
  36. Intrinsic.X86Paddd,
  37. Intrinsic.X86Paddq
  38. };
  39. public static readonly Intrinsic[] X86PcmpeqInstruction = new Intrinsic[]
  40. {
  41. Intrinsic.X86Pcmpeqb,
  42. Intrinsic.X86Pcmpeqw,
  43. Intrinsic.X86Pcmpeqd,
  44. Intrinsic.X86Pcmpeqq
  45. };
  46. public static readonly Intrinsic[] X86PcmpgtInstruction = new Intrinsic[]
  47. {
  48. Intrinsic.X86Pcmpgtb,
  49. Intrinsic.X86Pcmpgtw,
  50. Intrinsic.X86Pcmpgtd,
  51. Intrinsic.X86Pcmpgtq
  52. };
  53. public static readonly Intrinsic[] X86PmaxsInstruction = new Intrinsic[]
  54. {
  55. Intrinsic.X86Pmaxsb,
  56. Intrinsic.X86Pmaxsw,
  57. Intrinsic.X86Pmaxsd
  58. };
  59. public static readonly Intrinsic[] X86PmaxuInstruction = new Intrinsic[]
  60. {
  61. Intrinsic.X86Pmaxub,
  62. Intrinsic.X86Pmaxuw,
  63. Intrinsic.X86Pmaxud
  64. };
  65. public static readonly Intrinsic[] X86PminsInstruction = new Intrinsic[]
  66. {
  67. Intrinsic.X86Pminsb,
  68. Intrinsic.X86Pminsw,
  69. Intrinsic.X86Pminsd
  70. };
  71. public static readonly Intrinsic[] X86PminuInstruction = new Intrinsic[]
  72. {
  73. Intrinsic.X86Pminub,
  74. Intrinsic.X86Pminuw,
  75. Intrinsic.X86Pminud
  76. };
  77. public static readonly Intrinsic[] X86PmovsxInstruction = new Intrinsic[]
  78. {
  79. Intrinsic.X86Pmovsxbw,
  80. Intrinsic.X86Pmovsxwd,
  81. Intrinsic.X86Pmovsxdq
  82. };
  83. public static readonly Intrinsic[] X86PmovzxInstruction = new Intrinsic[]
  84. {
  85. Intrinsic.X86Pmovzxbw,
  86. Intrinsic.X86Pmovzxwd,
  87. Intrinsic.X86Pmovzxdq
  88. };
  89. public static readonly Intrinsic[] X86PsllInstruction = new Intrinsic[]
  90. {
  91. 0,
  92. Intrinsic.X86Psllw,
  93. Intrinsic.X86Pslld,
  94. Intrinsic.X86Psllq
  95. };
  96. public static readonly Intrinsic[] X86PsraInstruction = new Intrinsic[]
  97. {
  98. 0,
  99. Intrinsic.X86Psraw,
  100. Intrinsic.X86Psrad
  101. };
  102. public static readonly Intrinsic[] X86PsrlInstruction = new Intrinsic[]
  103. {
  104. 0,
  105. Intrinsic.X86Psrlw,
  106. Intrinsic.X86Psrld,
  107. Intrinsic.X86Psrlq
  108. };
  109. public static readonly Intrinsic[] X86PsubInstruction = new Intrinsic[]
  110. {
  111. Intrinsic.X86Psubb,
  112. Intrinsic.X86Psubw,
  113. Intrinsic.X86Psubd,
  114. Intrinsic.X86Psubq
  115. };
  116. public static readonly Intrinsic[] X86PunpckhInstruction = new Intrinsic[]
  117. {
  118. Intrinsic.X86Punpckhbw,
  119. Intrinsic.X86Punpckhwd,
  120. Intrinsic.X86Punpckhdq,
  121. Intrinsic.X86Punpckhqdq
  122. };
  123. public static readonly Intrinsic[] X86PunpcklInstruction = new Intrinsic[]
  124. {
  125. Intrinsic.X86Punpcklbw,
  126. Intrinsic.X86Punpcklwd,
  127. Intrinsic.X86Punpckldq,
  128. Intrinsic.X86Punpcklqdq
  129. };
  130. #endregion
  131. public static int GetImmShl(OpCodeSimdShImm op)
  132. {
  133. return op.Imm - (8 << op.Size);
  134. }
  135. public static int GetImmShr(OpCodeSimdShImm op)
  136. {
  137. return (8 << (op.Size + 1)) - op.Imm;
  138. }
  139. public static Operand X86GetScalar(ArmEmitterContext context, float value)
  140. {
  141. return X86GetScalar(context, BitConverter.SingleToInt32Bits(value));
  142. }
  143. public static Operand X86GetScalar(ArmEmitterContext context, double value)
  144. {
  145. return X86GetScalar(context, BitConverter.DoubleToInt64Bits(value));
  146. }
  147. public static Operand X86GetScalar(ArmEmitterContext context, int value)
  148. {
  149. return context.VectorCreateScalar(Const(value));
  150. }
  151. public static Operand X86GetScalar(ArmEmitterContext context, long value)
  152. {
  153. return context.VectorCreateScalar(Const(value));
  154. }
  155. public static Operand X86GetAllElements(ArmEmitterContext context, float value)
  156. {
  157. return X86GetAllElements(context, BitConverter.SingleToInt32Bits(value));
  158. }
  159. public static Operand X86GetAllElements(ArmEmitterContext context, double value)
  160. {
  161. return X86GetAllElements(context, BitConverter.DoubleToInt64Bits(value));
  162. }
  163. public static Operand X86GetAllElements(ArmEmitterContext context, int value)
  164. {
  165. Operand vector = context.VectorCreateScalar(Const(value));
  166. vector = context.AddIntrinsic(Intrinsic.X86Shufps, vector, vector, Const(0));
  167. return vector;
  168. }
  169. public static Operand X86GetAllElements(ArmEmitterContext context, long value)
  170. {
  171. Operand vector = context.VectorCreateScalar(Const(value));
  172. vector = context.AddIntrinsic(Intrinsic.X86Movlhps, vector, vector);
  173. return vector;
  174. }
  175. public static Operand X86GetElements(ArmEmitterContext context, long e1, long e0)
  176. {
  177. Operand vector0 = context.VectorCreateScalar(Const(e0));
  178. Operand vector1 = context.VectorCreateScalar(Const(e1));
  179. return context.AddIntrinsic(Intrinsic.X86Punpcklqdq, vector0, vector1);
  180. }
  181. public static int X86GetRoundControl(FPRoundingMode roundMode)
  182. {
  183. switch (roundMode)
  184. {
  185. case FPRoundingMode.ToNearest: return 8 | 0; // even
  186. case FPRoundingMode.TowardsPlusInfinity: return 8 | 2;
  187. case FPRoundingMode.TowardsMinusInfinity: return 8 | 1;
  188. case FPRoundingMode.TowardsZero: return 8 | 3;
  189. }
  190. throw new ArgumentException($"Invalid rounding mode \"{roundMode}\".");
  191. }
  192. public static void EmitScalarUnaryOpF(ArmEmitterContext context, Intrinsic inst32, Intrinsic inst64)
  193. {
  194. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  195. Operand n = GetVec(op.Rn);
  196. Intrinsic inst = (op.Size & 1) != 0 ? inst64 : inst32;
  197. Operand res = context.AddIntrinsic(inst, n);
  198. if ((op.Size & 1) != 0)
  199. {
  200. res = context.VectorZeroUpper64(res);
  201. }
  202. else
  203. {
  204. res = context.VectorZeroUpper96(res);
  205. }
  206. context.Copy(GetVec(op.Rd), res);
  207. }
  208. public static void EmitScalarBinaryOpF(ArmEmitterContext context, Intrinsic inst32, Intrinsic inst64)
  209. {
  210. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  211. Operand n = GetVec(op.Rn);
  212. Operand m = GetVec(op.Rm);
  213. Intrinsic inst = (op.Size & 1) != 0 ? inst64 : inst32;
  214. Operand res = context.AddIntrinsic(inst, n, m);
  215. if ((op.Size & 1) != 0)
  216. {
  217. res = context.VectorZeroUpper64(res);
  218. }
  219. else
  220. {
  221. res = context.VectorZeroUpper96(res);
  222. }
  223. context.Copy(GetVec(op.Rd), res);
  224. }
  225. public static void EmitVectorUnaryOpF(ArmEmitterContext context, Intrinsic inst32, Intrinsic inst64)
  226. {
  227. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  228. Operand n = GetVec(op.Rn);
  229. Intrinsic inst = (op.Size & 1) != 0 ? inst64 : inst32;
  230. Operand res = context.AddIntrinsic(inst, n);
  231. if (op.RegisterSize == RegisterSize.Simd64)
  232. {
  233. res = context.VectorZeroUpper64(res);
  234. }
  235. context.Copy(GetVec(op.Rd), res);
  236. }
  237. public static void EmitVectorBinaryOpF(ArmEmitterContext context, Intrinsic inst32, Intrinsic inst64)
  238. {
  239. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  240. Operand n = GetVec(op.Rn);
  241. Operand m = GetVec(op.Rm);
  242. Intrinsic inst = (op.Size & 1) != 0 ? inst64 : inst32;
  243. Operand res = context.AddIntrinsic(inst, n, m);
  244. if (op.RegisterSize == RegisterSize.Simd64)
  245. {
  246. res = context.VectorZeroUpper64(res);
  247. }
  248. context.Copy(GetVec(op.Rd), res);
  249. }
  250. public static Operand EmitUnaryMathCall(ArmEmitterContext context, _F32_F32 f32, _F64_F64 f64, Operand n)
  251. {
  252. IOpCodeSimd op = (IOpCodeSimd)context.CurrOp;
  253. return (op.Size & 1) == 0 ? context.Call(f32, n) : context.Call(f64, n);
  254. }
  255. public static Operand EmitRoundMathCall(ArmEmitterContext context, MidpointRounding roundMode, Operand n)
  256. {
  257. IOpCodeSimd op = (IOpCodeSimd)context.CurrOp;
  258. Delegate dlg;
  259. if ((op.Size & 1) == 0)
  260. {
  261. dlg = new _F32_F32_MidpointRounding(MathF.Round);
  262. }
  263. else /* if ((op.Size & 1) == 1) */
  264. {
  265. dlg = new _F64_F64_MidpointRounding(Math.Round);
  266. }
  267. return context.Call(dlg, n, Const((int)roundMode));
  268. }
  269. public static Operand EmitSoftFloatCall(
  270. ArmEmitterContext context,
  271. _F32_F32 f32,
  272. _F64_F64 f64,
  273. params Operand[] callArgs)
  274. {
  275. IOpCodeSimd op = (IOpCodeSimd)context.CurrOp;
  276. Delegate dlg = (op.Size & 1) == 0 ? (Delegate)f32 : (Delegate)f64;
  277. return context.Call(dlg, callArgs);
  278. }
  279. public static Operand EmitSoftFloatCall(
  280. ArmEmitterContext context,
  281. _F32_F32_F32 f32,
  282. _F64_F64_F64 f64,
  283. params Operand[] callArgs)
  284. {
  285. IOpCodeSimd op = (IOpCodeSimd)context.CurrOp;
  286. Delegate dlg = (op.Size & 1) == 0 ? (Delegate)f32 : (Delegate)f64;
  287. return context.Call(dlg, callArgs);
  288. }
  289. public static Operand EmitSoftFloatCall(
  290. ArmEmitterContext context,
  291. _F32_F32_F32_F32 f32,
  292. _F64_F64_F64_F64 f64,
  293. params Operand[] callArgs)
  294. {
  295. IOpCodeSimd op = (IOpCodeSimd)context.CurrOp;
  296. Delegate dlg = (op.Size & 1) == 0 ? (Delegate)f32 : (Delegate)f64;
  297. return context.Call(dlg, callArgs);
  298. }
  299. public static void EmitScalarBinaryOpByElemF(ArmEmitterContext context, Func2I emit)
  300. {
  301. OpCodeSimdRegElemF op = (OpCodeSimdRegElemF)context.CurrOp;
  302. OperandType type = (op.Size & 1) != 0 ? OperandType.FP64 : OperandType.FP32;
  303. Operand n = context.VectorExtract(type, GetVec(op.Rn), 0);
  304. Operand m = context.VectorExtract(type, GetVec(op.Rm), op.Index);
  305. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), emit(n, m), 0));
  306. }
  307. public static void EmitScalarTernaryOpByElemF(ArmEmitterContext context, Func3I emit)
  308. {
  309. OpCodeSimdRegElemF op = (OpCodeSimdRegElemF)context.CurrOp;
  310. OperandType type = (op.Size & 1) != 0 ? OperandType.FP64 : OperandType.FP32;
  311. Operand d = context.VectorExtract(type, GetVec(op.Rd), 0);
  312. Operand n = context.VectorExtract(type, GetVec(op.Rn), 0);
  313. Operand m = context.VectorExtract(type, GetVec(op.Rm), op.Index);
  314. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), emit(d, n, m), 0));
  315. }
  316. public static void EmitScalarUnaryOpSx(ArmEmitterContext context, Func1I emit)
  317. {
  318. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  319. Operand n = EmitVectorExtractSx(context, op.Rn, 0, op.Size);
  320. Operand d = EmitVectorInsert(context, context.VectorZero(), emit(n), 0, op.Size);
  321. context.Copy(GetVec(op.Rd), d);
  322. }
  323. public static void EmitScalarBinaryOpSx(ArmEmitterContext context, Func2I emit)
  324. {
  325. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  326. Operand n = EmitVectorExtractSx(context, op.Rn, 0, op.Size);
  327. Operand m = EmitVectorExtractSx(context, op.Rm, 0, op.Size);
  328. Operand d = EmitVectorInsert(context, context.VectorZero(), emit(n, m), 0, op.Size);
  329. context.Copy(GetVec(op.Rd), d);
  330. }
  331. public static void EmitScalarUnaryOpZx(ArmEmitterContext context, Func1I emit)
  332. {
  333. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  334. Operand n = EmitVectorExtractZx(context, op.Rn, 0, op.Size);
  335. Operand d = EmitVectorInsert(context, context.VectorZero(), emit(n), 0, op.Size);
  336. context.Copy(GetVec(op.Rd), d);
  337. }
  338. public static void EmitScalarBinaryOpZx(ArmEmitterContext context, Func2I emit)
  339. {
  340. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  341. Operand n = EmitVectorExtractZx(context, op.Rn, 0, op.Size);
  342. Operand m = EmitVectorExtractZx(context, op.Rm, 0, op.Size);
  343. Operand d = EmitVectorInsert(context, context.VectorZero(), emit(n, m), 0, op.Size);
  344. context.Copy(GetVec(op.Rd), d);
  345. }
  346. public static void EmitScalarTernaryOpZx(ArmEmitterContext context, Func3I emit)
  347. {
  348. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  349. Operand d = EmitVectorExtractZx(context, op.Rd, 0, op.Size);
  350. Operand n = EmitVectorExtractZx(context, op.Rn, 0, op.Size);
  351. Operand m = EmitVectorExtractZx(context, op.Rm, 0, op.Size);
  352. d = EmitVectorInsert(context, context.VectorZero(), emit(d, n, m), 0, op.Size);
  353. context.Copy(GetVec(op.Rd), d);
  354. }
  355. public static void EmitScalarUnaryOpF(ArmEmitterContext context, Func1I emit)
  356. {
  357. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  358. OperandType type = (op.Size & 1) != 0 ? OperandType.FP64 : OperandType.FP32;
  359. Operand n = context.VectorExtract(type, GetVec(op.Rn), 0);
  360. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), emit(n), 0));
  361. }
  362. public static void EmitScalarBinaryOpF(ArmEmitterContext context, Func2I emit)
  363. {
  364. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  365. OperandType type = (op.Size & 1) != 0 ? OperandType.FP64 : OperandType.FP32;
  366. Operand n = context.VectorExtract(type, GetVec(op.Rn), 0);
  367. Operand m = context.VectorExtract(type, GetVec(op.Rm), 0);
  368. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), emit(n, m), 0));
  369. }
  370. public static void EmitScalarTernaryRaOpF(ArmEmitterContext context, Func3I emit)
  371. {
  372. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  373. OperandType type = (op.Size & 1) != 0 ? OperandType.FP64 : OperandType.FP32;
  374. Operand a = context.VectorExtract(type, GetVec(op.Ra), 0);
  375. Operand n = context.VectorExtract(type, GetVec(op.Rn), 0);
  376. Operand m = context.VectorExtract(type, GetVec(op.Rm), 0);
  377. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), emit(a, n, m), 0));
  378. }
  379. public static void EmitVectorUnaryOpF(ArmEmitterContext context, Func1I emit)
  380. {
  381. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  382. Operand res = context.VectorZero();
  383. int sizeF = op.Size & 1;
  384. OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
  385. int elems = op.GetBytesCount() >> sizeF + 2;
  386. for (int index = 0; index < elems; index++)
  387. {
  388. Operand ne = context.VectorExtract(type, GetVec(op.Rn), index);
  389. res = context.VectorInsert(res, emit(ne), index);
  390. }
  391. context.Copy(GetVec(op.Rd), res);
  392. }
  393. public static void EmitVectorBinaryOpF(ArmEmitterContext context, Func2I emit)
  394. {
  395. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  396. Operand res = context.VectorZero();
  397. int sizeF = op.Size & 1;
  398. OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
  399. int elems = op.GetBytesCount() >> sizeF + 2;
  400. for (int index = 0; index < elems; index++)
  401. {
  402. Operand ne = context.VectorExtract(type, GetVec(op.Rn), index);
  403. Operand me = context.VectorExtract(type, GetVec(op.Rm), index);
  404. res = context.VectorInsert(res, emit(ne, me), index);
  405. }
  406. context.Copy(GetVec(op.Rd), res);
  407. }
  408. public static void EmitVectorTernaryOpF(ArmEmitterContext context, Func3I emit)
  409. {
  410. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  411. Operand res = context.VectorZero();
  412. int sizeF = op.Size & 1;
  413. OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
  414. int elems = op.GetBytesCount() >> sizeF + 2;
  415. for (int index = 0; index < elems; index++)
  416. {
  417. Operand de = context.VectorExtract(type, GetVec(op.Rd), index);
  418. Operand ne = context.VectorExtract(type, GetVec(op.Rn), index);
  419. Operand me = context.VectorExtract(type, GetVec(op.Rm), index);
  420. res = context.VectorInsert(res, emit(de, ne, me), index);
  421. }
  422. context.Copy(GetVec(op.Rd), res);
  423. }
  424. public static void EmitVectorBinaryOpByElemF(ArmEmitterContext context, Func2I emit)
  425. {
  426. OpCodeSimdRegElemF op = (OpCodeSimdRegElemF)context.CurrOp;
  427. Operand res = context.VectorZero();
  428. int sizeF = op.Size & 1;
  429. OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
  430. int elems = op.GetBytesCount() >> sizeF + 2;
  431. for (int index = 0; index < elems; index++)
  432. {
  433. Operand ne = context.VectorExtract(type, GetVec(op.Rn), index);
  434. Operand me = context.VectorExtract(type, GetVec(op.Rm), op.Index);
  435. res = context.VectorInsert(res, emit(ne, me), index);
  436. }
  437. context.Copy(GetVec(op.Rd), res);
  438. }
  439. public static void EmitVectorTernaryOpByElemF(ArmEmitterContext context, Func3I emit)
  440. {
  441. OpCodeSimdRegElemF op = (OpCodeSimdRegElemF)context.CurrOp;
  442. Operand res = context.VectorZero();
  443. int sizeF = op.Size & 1;
  444. OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
  445. int elems = op.GetBytesCount() >> sizeF + 2;
  446. for (int index = 0; index < elems; index++)
  447. {
  448. Operand de = context.VectorExtract(type, GetVec(op.Rd), index);
  449. Operand ne = context.VectorExtract(type, GetVec(op.Rn), index);
  450. Operand me = context.VectorExtract(type, GetVec(op.Rm), op.Index);
  451. res = context.VectorInsert(res, emit(de, ne, me), index);
  452. }
  453. context.Copy(GetVec(op.Rd), res);
  454. }
  455. public static void EmitVectorUnaryOpSx(ArmEmitterContext context, Func1I emit)
  456. {
  457. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  458. Operand res = context.VectorZero();
  459. int elems = op.GetBytesCount() >> op.Size;
  460. for (int index = 0; index < elems; index++)
  461. {
  462. Operand ne = EmitVectorExtractSx(context, op.Rn, index, op.Size);
  463. res = EmitVectorInsert(context, res, emit(ne), index, op.Size);
  464. }
  465. context.Copy(GetVec(op.Rd), res);
  466. }
  467. public static void EmitVectorBinaryOpSx(ArmEmitterContext context, Func2I emit)
  468. {
  469. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  470. Operand res = context.VectorZero();
  471. int elems = op.GetBytesCount() >> op.Size;
  472. for (int index = 0; index < elems; index++)
  473. {
  474. Operand ne = EmitVectorExtractSx(context, op.Rn, index, op.Size);
  475. Operand me = EmitVectorExtractSx(context, op.Rm, index, op.Size);
  476. res = EmitVectorInsert(context, res, emit(ne, me), index, op.Size);
  477. }
  478. context.Copy(GetVec(op.Rd), res);
  479. }
  480. public static void EmitVectorTernaryOpSx(ArmEmitterContext context, Func3I emit)
  481. {
  482. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  483. Operand res = context.VectorZero();
  484. int elems = op.GetBytesCount() >> op.Size;
  485. for (int index = 0; index < elems; index++)
  486. {
  487. Operand de = EmitVectorExtractSx(context, op.Rd, index, op.Size);
  488. Operand ne = EmitVectorExtractSx(context, op.Rn, index, op.Size);
  489. Operand me = EmitVectorExtractSx(context, op.Rm, index, op.Size);
  490. res = EmitVectorInsert(context, res, emit(de, ne, me), index, op.Size);
  491. }
  492. context.Copy(GetVec(op.Rd), res);
  493. }
  494. public static void EmitVectorUnaryOpZx(ArmEmitterContext context, Func1I emit)
  495. {
  496. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  497. Operand res = context.VectorZero();
  498. int elems = op.GetBytesCount() >> op.Size;
  499. for (int index = 0; index < elems; index++)
  500. {
  501. Operand ne = EmitVectorExtractZx(context, op.Rn, index, op.Size);
  502. res = EmitVectorInsert(context, res, emit(ne), index, op.Size);
  503. }
  504. context.Copy(GetVec(op.Rd), res);
  505. }
  506. public static void EmitVectorBinaryOpZx(ArmEmitterContext context, Func2I emit)
  507. {
  508. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  509. Operand res = context.VectorZero();
  510. int elems = op.GetBytesCount() >> op.Size;
  511. for (int index = 0; index < elems; index++)
  512. {
  513. Operand ne = EmitVectorExtractZx(context, op.Rn, index, op.Size);
  514. Operand me = EmitVectorExtractZx(context, op.Rm, index, op.Size);
  515. res = EmitVectorInsert(context, res, emit(ne, me), index, op.Size);
  516. }
  517. context.Copy(GetVec(op.Rd), res);
  518. }
  519. public static void EmitVectorTernaryOpZx(ArmEmitterContext context, Func3I emit)
  520. {
  521. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  522. Operand res = context.VectorZero();
  523. int elems = op.GetBytesCount() >> op.Size;
  524. for (int index = 0; index < elems; index++)
  525. {
  526. Operand de = EmitVectorExtractZx(context, op.Rd, index, op.Size);
  527. Operand ne = EmitVectorExtractZx(context, op.Rn, index, op.Size);
  528. Operand me = EmitVectorExtractZx(context, op.Rm, index, op.Size);
  529. res = EmitVectorInsert(context, res, emit(de, ne, me), index, op.Size);
  530. }
  531. context.Copy(GetVec(op.Rd), res);
  532. }
  533. public static void EmitVectorBinaryOpByElemSx(ArmEmitterContext context, Func2I emit)
  534. {
  535. OpCodeSimdRegElem op = (OpCodeSimdRegElem)context.CurrOp;
  536. Operand res = context.VectorZero();
  537. Operand me = EmitVectorExtractSx(context, op.Rm, op.Index, op.Size);
  538. int elems = op.GetBytesCount() >> op.Size;
  539. for (int index = 0; index < elems; index++)
  540. {
  541. Operand ne = EmitVectorExtractSx(context, op.Rn, index, op.Size);
  542. res = EmitVectorInsert(context, res, emit(ne, me), index, op.Size);
  543. }
  544. context.Copy(GetVec(op.Rd), res);
  545. }
  546. public static void EmitVectorBinaryOpByElemZx(ArmEmitterContext context, Func2I emit)
  547. {
  548. OpCodeSimdRegElem op = (OpCodeSimdRegElem)context.CurrOp;
  549. Operand res = context.VectorZero();
  550. Operand me = EmitVectorExtractZx(context, op.Rm, op.Index, op.Size);
  551. int elems = op.GetBytesCount() >> op.Size;
  552. for (int index = 0; index < elems; index++)
  553. {
  554. Operand ne = EmitVectorExtractZx(context, op.Rn, index, op.Size);
  555. res = EmitVectorInsert(context, res, emit(ne, me), index, op.Size);
  556. }
  557. context.Copy(GetVec(op.Rd), res);
  558. }
  559. public static void EmitVectorTernaryOpByElemZx(ArmEmitterContext context, Func3I emit)
  560. {
  561. OpCodeSimdRegElem op = (OpCodeSimdRegElem)context.CurrOp;
  562. Operand res = context.VectorZero();
  563. Operand me = EmitVectorExtractZx(context, op.Rm, op.Index, op.Size);
  564. int elems = op.GetBytesCount() >> op.Size;
  565. for (int index = 0; index < elems; index++)
  566. {
  567. Operand de = EmitVectorExtractZx(context, op.Rd, index, op.Size);
  568. Operand ne = EmitVectorExtractZx(context, op.Rn, index, op.Size);
  569. res = EmitVectorInsert(context, res, emit(de, ne, me), index, op.Size);
  570. }
  571. context.Copy(GetVec(op.Rd), res);
  572. }
  573. public static void EmitVectorImmUnaryOp(ArmEmitterContext context, Func1I emit)
  574. {
  575. OpCodeSimdImm op = (OpCodeSimdImm)context.CurrOp;
  576. Operand imm = Const(op.Immediate);
  577. Operand res = context.VectorZero();
  578. int elems = op.GetBytesCount() >> op.Size;
  579. for (int index = 0; index < elems; index++)
  580. {
  581. res = EmitVectorInsert(context, res, emit(imm), index, op.Size);
  582. }
  583. context.Copy(GetVec(op.Rd), res);
  584. }
  585. public static void EmitVectorImmBinaryOp(ArmEmitterContext context, Func2I emit)
  586. {
  587. OpCodeSimdImm op = (OpCodeSimdImm)context.CurrOp;
  588. Operand imm = Const(op.Immediate);
  589. Operand res = context.VectorZero();
  590. int elems = op.GetBytesCount() >> op.Size;
  591. for (int index = 0; index < elems; index++)
  592. {
  593. Operand de = EmitVectorExtractZx(context, op.Rd, index, op.Size);
  594. res = EmitVectorInsert(context, res, emit(de, imm), index, op.Size);
  595. }
  596. context.Copy(GetVec(op.Rd), res);
  597. }
  598. public static void EmitVectorWidenRmBinaryOpSx(ArmEmitterContext context, Func2I emit)
  599. {
  600. EmitVectorWidenRmBinaryOp(context, emit, signed: true);
  601. }
  602. public static void EmitVectorWidenRmBinaryOpZx(ArmEmitterContext context, Func2I emit)
  603. {
  604. EmitVectorWidenRmBinaryOp(context, emit, signed: false);
  605. }
  606. private static void EmitVectorWidenRmBinaryOp(ArmEmitterContext context, Func2I emit, bool signed)
  607. {
  608. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  609. Operand res = context.VectorZero();
  610. int elems = 8 >> op.Size;
  611. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  612. for (int index = 0; index < elems; index++)
  613. {
  614. Operand ne = EmitVectorExtract(context, op.Rn, index, op.Size + 1, signed);
  615. Operand me = EmitVectorExtract(context, op.Rm, part + index, op.Size, signed);
  616. res = EmitVectorInsert(context, res, emit(ne, me), index, op.Size + 1);
  617. }
  618. context.Copy(GetVec(op.Rd), res);
  619. }
  620. public static void EmitVectorWidenRnRmBinaryOpSx(ArmEmitterContext context, Func2I emit)
  621. {
  622. EmitVectorWidenRnRmBinaryOp(context, emit, signed: true);
  623. }
  624. public static void EmitVectorWidenRnRmBinaryOpZx(ArmEmitterContext context, Func2I emit)
  625. {
  626. EmitVectorWidenRnRmBinaryOp(context, emit, signed: false);
  627. }
  628. private static void EmitVectorWidenRnRmBinaryOp(ArmEmitterContext context, Func2I emit, bool signed)
  629. {
  630. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  631. Operand res = context.VectorZero();
  632. int elems = 8 >> op.Size;
  633. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  634. for (int index = 0; index < elems; index++)
  635. {
  636. Operand ne = EmitVectorExtract(context, op.Rn, part + index, op.Size, signed);
  637. Operand me = EmitVectorExtract(context, op.Rm, part + index, op.Size, signed);
  638. res = EmitVectorInsert(context, res, emit(ne, me), index, op.Size + 1);
  639. }
  640. context.Copy(GetVec(op.Rd), res);
  641. }
  642. public static void EmitVectorWidenRnRmTernaryOpSx(ArmEmitterContext context, Func3I emit)
  643. {
  644. EmitVectorWidenRnRmTernaryOp(context, emit, signed: true);
  645. }
  646. public static void EmitVectorWidenRnRmTernaryOpZx(ArmEmitterContext context, Func3I emit)
  647. {
  648. EmitVectorWidenRnRmTernaryOp(context, emit, signed: false);
  649. }
  650. private static void EmitVectorWidenRnRmTernaryOp(ArmEmitterContext context, Func3I emit, bool signed)
  651. {
  652. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  653. Operand res = context.VectorZero();
  654. int elems = 8 >> op.Size;
  655. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  656. for (int index = 0; index < elems; index++)
  657. {
  658. Operand de = EmitVectorExtract(context, op.Rd, index, op.Size + 1, signed);
  659. Operand ne = EmitVectorExtract(context, op.Rn, part + index, op.Size, signed);
  660. Operand me = EmitVectorExtract(context, op.Rm, part + index, op.Size, signed);
  661. res = EmitVectorInsert(context, res, emit(de, ne, me), index, op.Size + 1);
  662. }
  663. context.Copy(GetVec(op.Rd), res);
  664. }
  665. public static void EmitVectorWidenBinaryOpByElemSx(ArmEmitterContext context, Func2I emit)
  666. {
  667. EmitVectorWidenBinaryOpByElem(context, emit, signed: true);
  668. }
  669. public static void EmitVectorWidenBinaryOpByElemZx(ArmEmitterContext context, Func2I emit)
  670. {
  671. EmitVectorWidenBinaryOpByElem(context, emit, signed: false);
  672. }
  673. private static void EmitVectorWidenBinaryOpByElem(ArmEmitterContext context, Func2I emit, bool signed)
  674. {
  675. OpCodeSimdRegElem op = (OpCodeSimdRegElem)context.CurrOp;
  676. Operand res = context.VectorZero();
  677. Operand me = EmitVectorExtract(context, op.Rm, op.Index, op.Size, signed);
  678. int elems = 8 >> op.Size;
  679. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  680. for (int index = 0; index < elems; index++)
  681. {
  682. Operand ne = EmitVectorExtract(context, op.Rn, part + index, op.Size, signed);
  683. res = EmitVectorInsert(context, res, emit(ne, me), index, op.Size + 1);
  684. }
  685. context.Copy(GetVec(op.Rd), res);
  686. }
  687. public static void EmitVectorWidenTernaryOpByElemSx(ArmEmitterContext context, Func3I emit)
  688. {
  689. EmitVectorWidenTernaryOpByElem(context, emit, signed: true);
  690. }
  691. public static void EmitVectorWidenTernaryOpByElemZx(ArmEmitterContext context, Func3I emit)
  692. {
  693. EmitVectorWidenTernaryOpByElem(context, emit, signed: false);
  694. }
  695. private static void EmitVectorWidenTernaryOpByElem(ArmEmitterContext context, Func3I emit, bool signed)
  696. {
  697. OpCodeSimdRegElem op = (OpCodeSimdRegElem)context.CurrOp;
  698. Operand res = context.VectorZero();
  699. Operand me = EmitVectorExtract(context, op.Rm, op.Index, op.Size, signed);
  700. int elems = 8 >> op.Size;
  701. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  702. for (int index = 0; index < elems; index++)
  703. {
  704. Operand de = EmitVectorExtract(context, op.Rd, index, op.Size + 1, signed);
  705. Operand ne = EmitVectorExtract(context, op.Rn, part + index, op.Size, signed);
  706. res = EmitVectorInsert(context, res, emit(de, ne, me), index, op.Size + 1);
  707. }
  708. context.Copy(GetVec(op.Rd), res);
  709. }
  710. public static void EmitVectorPairwiseOpSx(ArmEmitterContext context, Func2I emit)
  711. {
  712. EmitVectorPairwiseOp(context, emit, signed: true);
  713. }
  714. public static void EmitVectorPairwiseOpZx(ArmEmitterContext context, Func2I emit)
  715. {
  716. EmitVectorPairwiseOp(context, emit, signed: false);
  717. }
  718. private static void EmitVectorPairwiseOp(ArmEmitterContext context, Func2I emit, bool signed)
  719. {
  720. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  721. Operand res = context.VectorZero();
  722. int pairs = op.GetPairsCount() >> op.Size;
  723. for (int index = 0; index < pairs; index++)
  724. {
  725. int pairIndex = index << 1;
  726. Operand n0 = EmitVectorExtract(context, op.Rn, pairIndex, op.Size, signed);
  727. Operand n1 = EmitVectorExtract(context, op.Rn, pairIndex + 1, op.Size, signed);
  728. Operand m0 = EmitVectorExtract(context, op.Rm, pairIndex, op.Size, signed);
  729. Operand m1 = EmitVectorExtract(context, op.Rm, pairIndex + 1, op.Size, signed);
  730. res = EmitVectorInsert(context, res, emit(n0, n1), index, op.Size);
  731. res = EmitVectorInsert(context, res, emit(m0, m1), pairs + index, op.Size);
  732. }
  733. context.Copy(GetVec(op.Rd), res);
  734. }
  735. public static void EmitSsse3VectorPairwiseOp(ArmEmitterContext context, Intrinsic[] inst)
  736. {
  737. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  738. Operand n = GetVec(op.Rn);
  739. Operand m = GetVec(op.Rm);
  740. if (op.RegisterSize == RegisterSize.Simd64)
  741. {
  742. Operand zeroEvenMask = X86GetElements(context, _zeroMask, EvenMasks[op.Size]);
  743. Operand zeroOddMask = X86GetElements(context, _zeroMask, OddMasks [op.Size]);
  744. Operand mN = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, n, m); // m:n
  745. Operand left = context.AddIntrinsic(Intrinsic.X86Pshufb, mN, zeroEvenMask); // 0:even from m:n
  746. Operand right = context.AddIntrinsic(Intrinsic.X86Pshufb, mN, zeroOddMask); // 0:odd from m:n
  747. context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst[op.Size], left, right));
  748. }
  749. else if (op.Size < 3)
  750. {
  751. Operand oddEvenMask = X86GetElements(context, OddMasks[op.Size], EvenMasks[op.Size]);
  752. Operand oddEvenN = context.AddIntrinsic(Intrinsic.X86Pshufb, n, oddEvenMask); // odd:even from n
  753. Operand oddEvenM = context.AddIntrinsic(Intrinsic.X86Pshufb, m, oddEvenMask); // odd:even from m
  754. Operand left = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, oddEvenN, oddEvenM);
  755. Operand right = context.AddIntrinsic(Intrinsic.X86Punpckhqdq, oddEvenN, oddEvenM);
  756. context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst[op.Size], left, right));
  757. }
  758. else
  759. {
  760. Operand left = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, n, m);
  761. Operand right = context.AddIntrinsic(Intrinsic.X86Punpckhqdq, n, m);
  762. context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst[3], left, right));
  763. }
  764. }
  765. public static void EmitVectorAcrossVectorOpSx(ArmEmitterContext context, Func2I emit)
  766. {
  767. EmitVectorAcrossVectorOp(context, emit, signed: true, isLong: false);
  768. }
  769. public static void EmitVectorAcrossVectorOpZx(ArmEmitterContext context, Func2I emit)
  770. {
  771. EmitVectorAcrossVectorOp(context, emit, signed: false, isLong: false);
  772. }
  773. public static void EmitVectorLongAcrossVectorOpSx(ArmEmitterContext context, Func2I emit)
  774. {
  775. EmitVectorAcrossVectorOp(context, emit, signed: true, isLong: true);
  776. }
  777. public static void EmitVectorLongAcrossVectorOpZx(ArmEmitterContext context, Func2I emit)
  778. {
  779. EmitVectorAcrossVectorOp(context, emit, signed: false, isLong: true);
  780. }
  781. private static void EmitVectorAcrossVectorOp(
  782. ArmEmitterContext context,
  783. Func2I emit,
  784. bool signed,
  785. bool isLong)
  786. {
  787. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  788. int elems = op.GetBytesCount() >> op.Size;
  789. Operand res = EmitVectorExtract(context, op.Rn, 0, op.Size, signed);
  790. for (int index = 1; index < elems; index++)
  791. {
  792. Operand n = EmitVectorExtract(context, op.Rn, index, op.Size, signed);
  793. res = emit(res, n);
  794. }
  795. int size = isLong ? op.Size + 1 : op.Size;
  796. Operand d = EmitVectorInsert(context, context.VectorZero(), res, 0, size);
  797. context.Copy(GetVec(op.Rd), d);
  798. }
  799. public static void EmitVectorPairwiseOpF(ArmEmitterContext context, Func2I emit)
  800. {
  801. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  802. Operand res = context.VectorZero();
  803. int sizeF = op.Size & 1;
  804. OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
  805. int pairs = op.GetPairsCount() >> sizeF + 2;
  806. for (int index = 0; index < pairs; index++)
  807. {
  808. int pairIndex = index << 1;
  809. Operand n0 = context.VectorExtract(type, GetVec(op.Rn), pairIndex);
  810. Operand n1 = context.VectorExtract(type, GetVec(op.Rn), pairIndex + 1);
  811. Operand m0 = context.VectorExtract(type, GetVec(op.Rm), pairIndex);
  812. Operand m1 = context.VectorExtract(type, GetVec(op.Rm), pairIndex + 1);
  813. res = context.VectorInsert(res, emit(n0, n1), index);
  814. res = context.VectorInsert(res, emit(m0, m1), pairs + index);
  815. }
  816. context.Copy(GetVec(op.Rd), res);
  817. }
  818. public static void EmitSse2VectorPairwiseOpF(ArmEmitterContext context, Intrinsic inst32, Intrinsic inst64)
  819. {
  820. OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
  821. Operand n = GetVec(op.Rn);
  822. Operand m = GetVec(op.Rm);
  823. int sizeF = op.Size & 1;
  824. if (sizeF == 0)
  825. {
  826. if (op.RegisterSize == RegisterSize.Simd64)
  827. {
  828. Operand unpck = context.AddIntrinsic(Intrinsic.X86Unpcklps, n, m);
  829. Operand zero = context.VectorZero();
  830. Operand part0 = context.AddIntrinsic(Intrinsic.X86Movlhps, unpck, zero);
  831. Operand part1 = context.AddIntrinsic(Intrinsic.X86Movhlps, zero, unpck);
  832. context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst32, part0, part1));
  833. }
  834. else /* if (op.RegisterSize == RegisterSize.Simd128) */
  835. {
  836. const int sm0 = 2 << 6 | 0 << 4 | 2 << 2 | 0 << 0;
  837. const int sm1 = 3 << 6 | 1 << 4 | 3 << 2 | 1 << 0;
  838. Operand part0 = context.AddIntrinsic(Intrinsic.X86Shufps, n, m, Const(sm0));
  839. Operand part1 = context.AddIntrinsic(Intrinsic.X86Shufps, n, m, Const(sm1));
  840. context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst32, part0, part1));
  841. }
  842. }
  843. else /* if (sizeF == 1) */
  844. {
  845. Operand part0 = context.AddIntrinsic(Intrinsic.X86Unpcklpd, n, m);
  846. Operand part1 = context.AddIntrinsic(Intrinsic.X86Unpckhpd, n, m);
  847. context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst64, part0, part1));
  848. }
  849. }
  850. public enum CmpCondition
  851. {
  852. // Legacy Sse.
  853. Equal = 0, // Ordered, non-signaling.
  854. LessThan = 1, // Ordered, signaling.
  855. LessThanOrEqual = 2, // Ordered, signaling.
  856. UnorderedQ = 3, // Non-signaling.
  857. NotLessThan = 5, // Unordered, signaling.
  858. NotLessThanOrEqual = 6, // Unordered, signaling.
  859. OrderedQ = 7, // Non-signaling.
  860. // Vex.
  861. GreaterThanOrEqual = 13, // Ordered, signaling.
  862. GreaterThan = 14, // Ordered, signaling.
  863. OrderedS = 23 // Signaling.
  864. }
  865. [Flags]
  866. public enum SaturatingFlags
  867. {
  868. Scalar = 1 << 0,
  869. Signed = 1 << 1,
  870. Add = 1 << 2,
  871. Sub = 1 << 3,
  872. Accumulate = 1 << 4,
  873. ScalarSx = Scalar | Signed,
  874. ScalarZx = Scalar,
  875. VectorSx = Signed,
  876. VectorZx = 0
  877. }
  878. public static void EmitScalarSaturatingUnaryOpSx(ArmEmitterContext context, Func1I emit)
  879. {
  880. EmitSaturatingUnaryOpSx(context, emit, SaturatingFlags.ScalarSx);
  881. }
  882. public static void EmitVectorSaturatingUnaryOpSx(ArmEmitterContext context, Func1I emit)
  883. {
  884. EmitSaturatingUnaryOpSx(context, emit, SaturatingFlags.VectorSx);
  885. }
  886. private static void EmitSaturatingUnaryOpSx(ArmEmitterContext context, Func1I emit, SaturatingFlags flags)
  887. {
  888. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  889. Operand res = context.VectorZero();
  890. bool scalar = (flags & SaturatingFlags.Scalar) != 0;
  891. int elems = !scalar ? op.GetBytesCount() >> op.Size : 1;
  892. for (int index = 0; index < elems; index++)
  893. {
  894. Operand ne = EmitVectorExtractSx(context, op.Rn, index, op.Size);
  895. Operand de;
  896. if (op.Size <= 2)
  897. {
  898. de = EmitSatQ(context, emit(ne), op.Size, signedSrc: true, signedDst: true);
  899. }
  900. else /* if (op.Size == 3) */
  901. {
  902. de = EmitUnarySignedSatQAbsOrNeg(context, emit(ne));
  903. }
  904. res = EmitVectorInsert(context, res, de, index, op.Size);
  905. }
  906. context.Copy(GetVec(op.Rd), res);
  907. }
  908. public static void EmitScalarSaturatingBinaryOpSx(ArmEmitterContext context, SaturatingFlags flags)
  909. {
  910. EmitSaturatingBinaryOp(context, null, SaturatingFlags.ScalarSx | flags);
  911. }
  912. public static void EmitScalarSaturatingBinaryOpZx(ArmEmitterContext context, SaturatingFlags flags)
  913. {
  914. EmitSaturatingBinaryOp(context, null, SaturatingFlags.ScalarZx | flags);
  915. }
  916. public static void EmitVectorSaturatingBinaryOpSx(ArmEmitterContext context, SaturatingFlags flags)
  917. {
  918. EmitSaturatingBinaryOp(context, null, SaturatingFlags.VectorSx | flags);
  919. }
  920. public static void EmitVectorSaturatingBinaryOpZx(ArmEmitterContext context, SaturatingFlags flags)
  921. {
  922. EmitSaturatingBinaryOp(context, null, SaturatingFlags.VectorZx | flags);
  923. }
  924. public static void EmitSaturatingBinaryOp(ArmEmitterContext context, Func2I emit, SaturatingFlags flags)
  925. {
  926. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  927. Operand res = context.VectorZero();
  928. bool scalar = (flags & SaturatingFlags.Scalar) != 0;
  929. bool signed = (flags & SaturatingFlags.Signed) != 0;
  930. bool add = (flags & SaturatingFlags.Add) != 0;
  931. bool sub = (flags & SaturatingFlags.Sub) != 0;
  932. bool accumulate = (flags & SaturatingFlags.Accumulate) != 0;
  933. int elems = !scalar ? op.GetBytesCount() >> op.Size : 1;
  934. if (add || sub)
  935. {
  936. OpCodeSimdReg opReg = (OpCodeSimdReg)op;
  937. for (int index = 0; index < elems; index++)
  938. {
  939. Operand de;
  940. Operand ne = EmitVectorExtract(context, opReg.Rn, index, op.Size, signed);
  941. Operand me = EmitVectorExtract(context, opReg.Rm, index, op.Size, signed);
  942. if (op.Size <= 2)
  943. {
  944. Operand temp = add ? context.Add(ne, me) : context.Subtract(ne, me);
  945. de = EmitSatQ(context, temp, op.Size, signedSrc: true, signedDst: signed);
  946. }
  947. else if (add) /* if (op.Size == 3) */
  948. {
  949. de = EmitBinarySatQAdd(context, ne, me, signed);
  950. }
  951. else /* if (sub) */
  952. {
  953. de = EmitBinarySatQSub(context, ne, me, signed);
  954. }
  955. res = EmitVectorInsert(context, res, de, index, op.Size);
  956. }
  957. }
  958. else if (accumulate)
  959. {
  960. for (int index = 0; index < elems; index++)
  961. {
  962. Operand de;
  963. Operand ne = EmitVectorExtract(context, op.Rn, index, op.Size, !signed);
  964. Operand me = EmitVectorExtract(context, op.Rd, index, op.Size, signed);
  965. if (op.Size <= 2)
  966. {
  967. Operand temp = context.Add(ne, me);
  968. de = EmitSatQ(context, temp, op.Size, signedSrc: true, signedDst: signed);
  969. }
  970. else /* if (op.Size == 3) */
  971. {
  972. de = EmitBinarySatQAccumulate(context, ne, me, signed);
  973. }
  974. res = EmitVectorInsert(context, res, de, index, op.Size);
  975. }
  976. }
  977. else
  978. {
  979. OpCodeSimdReg opReg = (OpCodeSimdReg)op;
  980. for (int index = 0; index < elems; index++)
  981. {
  982. Operand ne = EmitVectorExtract(context, opReg.Rn, index, op.Size, signed);
  983. Operand me = EmitVectorExtract(context, opReg.Rm, index, op.Size, signed);
  984. Operand de = EmitSatQ(context, emit(ne, me), op.Size, true, signed);
  985. res = EmitVectorInsert(context, res, de, index, op.Size);
  986. }
  987. }
  988. context.Copy(GetVec(op.Rd), res);
  989. }
  990. [Flags]
  991. public enum SaturatingNarrowFlags
  992. {
  993. Scalar = 1 << 0,
  994. SignedSrc = 1 << 1,
  995. SignedDst = 1 << 2,
  996. ScalarSxSx = Scalar | SignedSrc | SignedDst,
  997. ScalarSxZx = Scalar | SignedSrc,
  998. ScalarZxZx = Scalar,
  999. VectorSxSx = SignedSrc | SignedDst,
  1000. VectorSxZx = SignedSrc,
  1001. VectorZxZx = 0
  1002. }
  1003. public static void EmitSaturatingNarrowOp(ArmEmitterContext context, SaturatingNarrowFlags flags)
  1004. {
  1005. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  1006. bool scalar = (flags & SaturatingNarrowFlags.Scalar) != 0;
  1007. bool signedSrc = (flags & SaturatingNarrowFlags.SignedSrc) != 0;
  1008. bool signedDst = (flags & SaturatingNarrowFlags.SignedDst) != 0;
  1009. int elems = !scalar ? 8 >> op.Size : 1;
  1010. int part = !scalar && (op.RegisterSize == RegisterSize.Simd128) ? elems : 0;
  1011. Operand d = GetVec(op.Rd);
  1012. Operand res = part == 0 ? context.VectorZero() : context.Copy(d);
  1013. for (int index = 0; index < elems; index++)
  1014. {
  1015. Operand ne = EmitVectorExtract(context, op.Rn, index, op.Size + 1, signedSrc);
  1016. Operand temp = EmitSatQ(context, ne, op.Size, signedSrc, signedDst);
  1017. res = EmitVectorInsert(context, res, temp, part + index, op.Size);
  1018. }
  1019. context.Copy(d, res);
  1020. }
  1021. // TSrc (16bit, 32bit, 64bit; signed, unsigned) > TDst (8bit, 16bit, 32bit; signed, unsigned).
  1022. public static Operand EmitSatQ(ArmEmitterContext context, Operand op, int sizeDst, bool signedSrc, bool signedDst)
  1023. {
  1024. if ((uint)sizeDst > 2u)
  1025. {
  1026. throw new ArgumentOutOfRangeException(nameof(sizeDst));
  1027. }
  1028. Delegate dlg;
  1029. if (signedSrc)
  1030. {
  1031. dlg = signedDst
  1032. ? (Delegate)new _S64_S64_S32(SoftFallback.SignedSrcSignedDstSatQ)
  1033. : (Delegate)new _U64_S64_S32(SoftFallback.SignedSrcUnsignedDstSatQ);
  1034. }
  1035. else
  1036. {
  1037. dlg = signedDst
  1038. ? (Delegate)new _S64_U64_S32(SoftFallback.UnsignedSrcSignedDstSatQ)
  1039. : (Delegate)new _U64_U64_S32(SoftFallback.UnsignedSrcUnsignedDstSatQ);
  1040. }
  1041. return context.Call(dlg, op, Const(sizeDst));
  1042. }
  1043. // TSrc (64bit) == TDst (64bit); signed.
  1044. public static Operand EmitUnarySignedSatQAbsOrNeg(ArmEmitterContext context, Operand op)
  1045. {
  1046. Debug.Assert(((OpCodeSimd)context.CurrOp).Size == 3, "Invalid element size.");
  1047. return context.Call(new _S64_S64(SoftFallback.UnarySignedSatQAbsOrNeg), op);
  1048. }
  1049. // TSrcs (64bit) == TDst (64bit); signed, unsigned.
  1050. public static Operand EmitBinarySatQAdd(ArmEmitterContext context, Operand op1, Operand op2, bool signed)
  1051. {
  1052. Debug.Assert(((OpCodeSimd)context.CurrOp).Size == 3, "Invalid element size.");
  1053. Delegate dlg = signed
  1054. ? (Delegate)new _S64_S64_S64(SoftFallback.BinarySignedSatQAdd)
  1055. : (Delegate)new _U64_U64_U64(SoftFallback.BinaryUnsignedSatQAdd);
  1056. return context.Call(dlg, op1, op2);
  1057. }
  1058. // TSrcs (64bit) == TDst (64bit); signed, unsigned.
  1059. public static Operand EmitBinarySatQSub(ArmEmitterContext context, Operand op1, Operand op2, bool signed)
  1060. {
  1061. Debug.Assert(((OpCodeSimd)context.CurrOp).Size == 3, "Invalid element size.");
  1062. Delegate dlg = signed
  1063. ? (Delegate)new _S64_S64_S64(SoftFallback.BinarySignedSatQSub)
  1064. : (Delegate)new _U64_U64_U64(SoftFallback.BinaryUnsignedSatQSub);
  1065. return context.Call(dlg, op1, op2);
  1066. }
  1067. // TSrcs (64bit) == TDst (64bit); signed, unsigned.
  1068. public static Operand EmitBinarySatQAccumulate(ArmEmitterContext context, Operand op1, Operand op2, bool signed)
  1069. {
  1070. Debug.Assert(((OpCodeSimd)context.CurrOp).Size == 3, "Invalid element size.");
  1071. Delegate dlg = signed
  1072. ? (Delegate)new _S64_U64_S64(SoftFallback.BinarySignedSatQAcc)
  1073. : (Delegate)new _U64_S64_U64(SoftFallback.BinaryUnsignedSatQAcc);
  1074. return context.Call(dlg, op1, op2);
  1075. }
  1076. public static Operand EmitVectorExtractSx(ArmEmitterContext context, int reg, int index, int size)
  1077. {
  1078. return EmitVectorExtract(context, reg, index, size, true);
  1079. }
  1080. public static Operand EmitVectorExtractZx(ArmEmitterContext context, int reg, int index, int size)
  1081. {
  1082. return EmitVectorExtract(context, reg, index, size, false);
  1083. }
  1084. public static Operand EmitVectorExtract(ArmEmitterContext context, int reg, int index, int size, bool signed)
  1085. {
  1086. ThrowIfInvalid(index, size);
  1087. Operand res = null;
  1088. switch (size)
  1089. {
  1090. case 0:
  1091. res = context.VectorExtract8(GetVec(reg), index);
  1092. break;
  1093. case 1:
  1094. res = context.VectorExtract16(GetVec(reg), index);
  1095. break;
  1096. case 2:
  1097. res = context.VectorExtract(OperandType.I32, GetVec(reg), index);
  1098. break;
  1099. case 3:
  1100. res = context.VectorExtract(OperandType.I64, GetVec(reg), index);
  1101. break;
  1102. }
  1103. if (signed)
  1104. {
  1105. switch (size)
  1106. {
  1107. case 0: res = context.SignExtend8 (OperandType.I64, res); break;
  1108. case 1: res = context.SignExtend16(OperandType.I64, res); break;
  1109. case 2: res = context.SignExtend32(OperandType.I64, res); break;
  1110. }
  1111. }
  1112. else
  1113. {
  1114. switch (size)
  1115. {
  1116. case 0: res = context.ZeroExtend8 (OperandType.I64, res); break;
  1117. case 1: res = context.ZeroExtend16(OperandType.I64, res); break;
  1118. case 2: res = context.ZeroExtend32(OperandType.I64, res); break;
  1119. }
  1120. }
  1121. return res;
  1122. }
  1123. public static Operand EmitVectorInsert(ArmEmitterContext context, Operand vector, Operand value, int index, int size)
  1124. {
  1125. ThrowIfInvalid(index, size);
  1126. if (size < 3)
  1127. {
  1128. value = context.ConvertI64ToI32(value);
  1129. }
  1130. switch (size)
  1131. {
  1132. case 0: vector = context.VectorInsert8 (vector, value, index); break;
  1133. case 1: vector = context.VectorInsert16(vector, value, index); break;
  1134. case 2: vector = context.VectorInsert (vector, value, index); break;
  1135. case 3: vector = context.VectorInsert (vector, value, index); break;
  1136. }
  1137. return vector;
  1138. }
  1139. private static void ThrowIfInvalid(int index, int size)
  1140. {
  1141. if ((uint)size > 3u)
  1142. {
  1143. throw new ArgumentOutOfRangeException(nameof(size));
  1144. }
  1145. if ((uint)index >= 16u >> size)
  1146. {
  1147. throw new ArgumentOutOfRangeException(nameof(index));
  1148. }
  1149. }
  1150. }
  1151. }