InstEmitSimdCvt.cs 57 KB

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  1. using ARMeilleure.Decoders;
  2. using ARMeilleure.IntermediateRepresentation;
  3. using ARMeilleure.State;
  4. using ARMeilleure.Translation;
  5. using System;
  6. using System.Diagnostics;
  7. using System.Reflection;
  8. using static ARMeilleure.Instructions.InstEmitHelper;
  9. using static ARMeilleure.Instructions.InstEmitSimdHelper;
  10. using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
  11. namespace ARMeilleure.Instructions
  12. {
  13. using Func1I = Func<Operand, Operand>;
  14. static partial class InstEmit
  15. {
  16. public static void Fcvt_S(ArmEmitterContext context)
  17. {
  18. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  19. if (op.Size == 0 && op.Opc == 1) // Single -> Double.
  20. {
  21. if (Optimizations.UseSse2)
  22. {
  23. Operand n = GetVec(op.Rn);
  24. Operand res = context.AddIntrinsic(Intrinsic.X86Cvtss2sd, context.VectorZero(), n);
  25. context.Copy(GetVec(op.Rd), res);
  26. }
  27. else
  28. {
  29. Operand ne = context.VectorExtract(OperandType.FP32, GetVec(op.Rn), 0);
  30. Operand res = context.ConvertToFP(OperandType.FP64, ne);
  31. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  32. }
  33. }
  34. else if (op.Size == 1 && op.Opc == 0) // Double -> Single.
  35. {
  36. if (Optimizations.UseSse2)
  37. {
  38. Operand n = GetVec(op.Rn);
  39. Operand res = context.AddIntrinsic(Intrinsic.X86Cvtsd2ss, context.VectorZero(), n);
  40. context.Copy(GetVec(op.Rd), res);
  41. }
  42. else
  43. {
  44. Operand ne = context.VectorExtract(OperandType.FP64, GetVec(op.Rn), 0);
  45. Operand res = context.ConvertToFP(OperandType.FP32, ne);
  46. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  47. }
  48. }
  49. else if (op.Size == 0 && op.Opc == 3) // Single -> Half.
  50. {
  51. if (Optimizations.UseF16c)
  52. {
  53. Debug.Assert(!Optimizations.ForceLegacySse);
  54. Operand n = GetVec(op.Rn);
  55. Operand res = context.AddIntrinsic(Intrinsic.X86Vcvtps2ph, n, Const(X86GetRoundControl(FPRoundingMode.ToNearest)));
  56. res = context.AddIntrinsic(Intrinsic.X86Pslldq, res, Const(14)); // VectorZeroUpper112()
  57. res = context.AddIntrinsic(Intrinsic.X86Psrldq, res, Const(14));
  58. context.Copy(GetVec(op.Rd), res);
  59. }
  60. else
  61. {
  62. Operand ne = context.VectorExtract(OperandType.FP32, GetVec(op.Rn), 0);
  63. Operand res = context.Call(typeof(SoftFloat32_16).GetMethod(nameof(SoftFloat32_16.FPConvert)), ne);
  64. res = context.ZeroExtend16(OperandType.I64, res);
  65. context.Copy(GetVec(op.Rd), EmitVectorInsert(context, context.VectorZero(), res, 0, 1));
  66. }
  67. }
  68. else if (op.Size == 3 && op.Opc == 0) // Half -> Single.
  69. {
  70. if (Optimizations.UseF16c)
  71. {
  72. Debug.Assert(!Optimizations.ForceLegacySse);
  73. Operand res = context.AddIntrinsic(Intrinsic.X86Vcvtph2ps, GetVec(op.Rn));
  74. res = context.VectorZeroUpper96(res);
  75. context.Copy(GetVec(op.Rd), res);
  76. }
  77. else
  78. {
  79. Operand ne = EmitVectorExtractZx(context, op.Rn, 0, 1);
  80. Operand res = context.Call(typeof(SoftFloat16_32).GetMethod(nameof(SoftFloat16_32.FPConvert)), ne);
  81. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  82. }
  83. }
  84. else if (op.Size == 1 && op.Opc == 3) // Double -> Half.
  85. {
  86. throw new NotImplementedException("Double-precision to half-precision.");
  87. }
  88. else if (op.Size == 3 && op.Opc == 1) // Double -> Half.
  89. {
  90. throw new NotImplementedException("Half-precision to double-precision.");
  91. }
  92. else // Invalid encoding.
  93. {
  94. Debug.Assert(false, $"type == {op.Size} && opc == {op.Opc}");
  95. }
  96. }
  97. public static void Fcvtas_Gp(ArmEmitterContext context)
  98. {
  99. EmitFcvt_s_Gp(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1));
  100. }
  101. public static void Fcvtas_S(ArmEmitterContext context)
  102. {
  103. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1), signed: true, scalar: true);
  104. }
  105. public static void Fcvtas_V(ArmEmitterContext context)
  106. {
  107. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1), signed: true, scalar: false);
  108. }
  109. public static void Fcvtau_Gp(ArmEmitterContext context)
  110. {
  111. EmitFcvt_u_Gp(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1));
  112. }
  113. public static void Fcvtau_S(ArmEmitterContext context)
  114. {
  115. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1), signed: false, scalar: true);
  116. }
  117. public static void Fcvtau_V(ArmEmitterContext context)
  118. {
  119. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, op1), signed: false, scalar: false);
  120. }
  121. public static void Fcvtl_V(ArmEmitterContext context)
  122. {
  123. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  124. int sizeF = op.Size & 1;
  125. if (Optimizations.UseSse2 && sizeF == 1)
  126. {
  127. Operand n = GetVec(op.Rn);
  128. Operand res = op.RegisterSize == RegisterSize.Simd128 ? context.AddIntrinsic(Intrinsic.X86Movhlps, n, n) : n;
  129. res = context.AddIntrinsic(Intrinsic.X86Cvtps2pd, res);
  130. context.Copy(GetVec(op.Rd), res);
  131. }
  132. else if (Optimizations.UseF16c && sizeF == 0)
  133. {
  134. Debug.Assert(!Optimizations.ForceLegacySse);
  135. Operand n = GetVec(op.Rn);
  136. Operand res = op.RegisterSize == RegisterSize.Simd128 ? context.AddIntrinsic(Intrinsic.X86Movhlps, n, n) : n;
  137. res = context.AddIntrinsic(Intrinsic.X86Vcvtph2ps, res);
  138. context.Copy(GetVec(op.Rd), res);
  139. }
  140. else
  141. {
  142. Operand res = context.VectorZero();
  143. int elems = 4 >> sizeF;
  144. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  145. for (int index = 0; index < elems; index++)
  146. {
  147. if (sizeF == 0)
  148. {
  149. Operand ne = EmitVectorExtractZx(context, op.Rn, part + index, 1);
  150. Operand e = context.Call(typeof(SoftFloat16_32).GetMethod(nameof(SoftFloat16_32.FPConvert)), ne);
  151. res = context.VectorInsert(res, e, index);
  152. }
  153. else /* if (sizeF == 1) */
  154. {
  155. Operand ne = context.VectorExtract(OperandType.FP32, GetVec(op.Rn), part + index);
  156. Operand e = context.ConvertToFP(OperandType.FP64, ne);
  157. res = context.VectorInsert(res, e, index);
  158. }
  159. }
  160. context.Copy(GetVec(op.Rd), res);
  161. }
  162. }
  163. public static void Fcvtms_Gp(ArmEmitterContext context)
  164. {
  165. if (Optimizations.UseSse41)
  166. {
  167. EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsMinusInfinity, isFixed: false);
  168. }
  169. else
  170. {
  171. EmitFcvt_s_Gp(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Floor), op1));
  172. }
  173. }
  174. public static void Fcvtms_V(ArmEmitterContext context)
  175. {
  176. if (Optimizations.UseSse41)
  177. {
  178. EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsMinusInfinity, scalar: false);
  179. }
  180. else
  181. {
  182. EmitFcvt(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Floor), op1), signed: true, scalar: false);
  183. }
  184. }
  185. public static void Fcvtmu_Gp(ArmEmitterContext context)
  186. {
  187. if (Optimizations.UseSse41)
  188. {
  189. EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsMinusInfinity, isFixed: false);
  190. }
  191. else
  192. {
  193. EmitFcvt_u_Gp(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Floor), op1));
  194. }
  195. }
  196. public static void Fcvtn_V(ArmEmitterContext context)
  197. {
  198. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  199. int sizeF = op.Size & 1;
  200. if (Optimizations.UseSse2 && sizeF == 1)
  201. {
  202. Operand d = GetVec(op.Rd);
  203. Intrinsic movInst = op.RegisterSize == RegisterSize.Simd128 ? Intrinsic.X86Movlhps : Intrinsic.X86Movhlps;
  204. Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtpd2ps, GetVec(op.Rn));
  205. nInt = context.AddIntrinsic(Intrinsic.X86Movlhps, nInt, nInt);
  206. Operand res = context.VectorZeroUpper64(d);
  207. res = context.AddIntrinsic(movInst, res, nInt);
  208. context.Copy(d, res);
  209. }
  210. else if (Optimizations.UseF16c && sizeF == 0)
  211. {
  212. Debug.Assert(!Optimizations.ForceLegacySse);
  213. Operand d = GetVec(op.Rd);
  214. Operand n = GetVec(op.Rn);
  215. Intrinsic movInst = op.RegisterSize == RegisterSize.Simd128 ? Intrinsic.X86Movlhps : Intrinsic.X86Movhlps;
  216. Operand nInt = context.AddIntrinsic(Intrinsic.X86Vcvtps2ph, n, Const(X86GetRoundControl(FPRoundingMode.ToNearest)));
  217. nInt = context.AddIntrinsic(Intrinsic.X86Movlhps, nInt, nInt);
  218. Operand res = context.VectorZeroUpper64(d);
  219. res = context.AddIntrinsic(movInst, res, nInt);
  220. context.Copy(d, res);
  221. }
  222. else
  223. {
  224. OperandType type = sizeF == 0 ? OperandType.FP32 : OperandType.FP64;
  225. int elems = 4 >> sizeF;
  226. int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
  227. Operand d = GetVec(op.Rd);
  228. Operand res = part == 0 ? context.VectorZero() : context.Copy(d);
  229. for (int index = 0; index < elems; index++)
  230. {
  231. Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
  232. if (sizeF == 0)
  233. {
  234. Operand e = context.Call(typeof(SoftFloat32_16).GetMethod(nameof(SoftFloat32_16.FPConvert)), ne);
  235. e = context.ZeroExtend16(OperandType.I64, e);
  236. res = EmitVectorInsert(context, res, e, part + index, 1);
  237. }
  238. else /* if (sizeF == 1) */
  239. {
  240. Operand e = context.ConvertToFP(OperandType.FP32, ne);
  241. res = context.VectorInsert(res, e, part + index);
  242. }
  243. }
  244. context.Copy(d, res);
  245. }
  246. }
  247. public static void Fcvtns_Gp(ArmEmitterContext context)
  248. {
  249. if (Optimizations.UseSse41)
  250. {
  251. EmitSse41Fcvts_Gp(context, FPRoundingMode.ToNearest, isFixed: false);
  252. }
  253. else
  254. {
  255. EmitFcvt_s_Gp(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1));
  256. }
  257. }
  258. public static void Fcvtns_S(ArmEmitterContext context)
  259. {
  260. if (Optimizations.UseSse41)
  261. {
  262. EmitSse41FcvtsOpF(context, FPRoundingMode.ToNearest, scalar: true);
  263. }
  264. else
  265. {
  266. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1), signed: true, scalar: true);
  267. }
  268. }
  269. public static void Fcvtns_V(ArmEmitterContext context)
  270. {
  271. if (Optimizations.UseSse41)
  272. {
  273. EmitSse41FcvtsOpF(context, FPRoundingMode.ToNearest, scalar: false);
  274. }
  275. else
  276. {
  277. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1), signed: true, scalar: false);
  278. }
  279. }
  280. public static void Fcvtnu_S(ArmEmitterContext context)
  281. {
  282. if (Optimizations.UseSse41)
  283. {
  284. EmitSse41FcvtuOpF(context, FPRoundingMode.ToNearest, scalar: true);
  285. }
  286. else
  287. {
  288. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1), signed: false, scalar: true);
  289. }
  290. }
  291. public static void Fcvtnu_V(ArmEmitterContext context)
  292. {
  293. if (Optimizations.UseSse41)
  294. {
  295. EmitSse41FcvtuOpF(context, FPRoundingMode.ToNearest, scalar: false);
  296. }
  297. else
  298. {
  299. EmitFcvt(context, (op1) => EmitRoundMathCall(context, MidpointRounding.ToEven, op1), signed: false, scalar: false);
  300. }
  301. }
  302. public static void Fcvtps_Gp(ArmEmitterContext context)
  303. {
  304. if (Optimizations.UseSse41)
  305. {
  306. EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsPlusInfinity, isFixed: false);
  307. }
  308. else
  309. {
  310. EmitFcvt_s_Gp(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Ceiling), op1));
  311. }
  312. }
  313. public static void Fcvtpu_Gp(ArmEmitterContext context)
  314. {
  315. if (Optimizations.UseSse41)
  316. {
  317. EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsPlusInfinity, isFixed: false);
  318. }
  319. else
  320. {
  321. EmitFcvt_u_Gp(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Ceiling), op1));
  322. }
  323. }
  324. public static void Fcvtzs_Gp(ArmEmitterContext context)
  325. {
  326. if (Optimizations.UseSse41)
  327. {
  328. EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsZero, isFixed: false);
  329. }
  330. else
  331. {
  332. EmitFcvt_s_Gp(context, (op1) => op1);
  333. }
  334. }
  335. public static void Fcvtzs_Gp_Fixed(ArmEmitterContext context)
  336. {
  337. if (Optimizations.UseSse41)
  338. {
  339. EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsZero, isFixed: true);
  340. }
  341. else
  342. {
  343. EmitFcvtzs_Gp_Fixed(context);
  344. }
  345. }
  346. public static void Fcvtzs_S(ArmEmitterContext context)
  347. {
  348. if (Optimizations.UseSse41)
  349. {
  350. EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsZero, scalar: true);
  351. }
  352. else
  353. {
  354. EmitFcvtz(context, signed: true, scalar: true);
  355. }
  356. }
  357. public static void Fcvtzs_V(ArmEmitterContext context)
  358. {
  359. if (Optimizations.UseSse41)
  360. {
  361. EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsZero, scalar: false);
  362. }
  363. else
  364. {
  365. EmitFcvtz(context, signed: true, scalar: false);
  366. }
  367. }
  368. public static void Fcvtzs_V_Fixed(ArmEmitterContext context)
  369. {
  370. if (Optimizations.UseSse41)
  371. {
  372. EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsZero, scalar: false);
  373. }
  374. else
  375. {
  376. EmitFcvtz(context, signed: true, scalar: false);
  377. }
  378. }
  379. public static void Fcvtzu_Gp(ArmEmitterContext context)
  380. {
  381. if (Optimizations.UseSse41)
  382. {
  383. EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsZero, isFixed: false);
  384. }
  385. else
  386. {
  387. EmitFcvt_u_Gp(context, (op1) => op1);
  388. }
  389. }
  390. public static void Fcvtzu_Gp_Fixed(ArmEmitterContext context)
  391. {
  392. if (Optimizations.UseSse41)
  393. {
  394. EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsZero, isFixed: true);
  395. }
  396. else
  397. {
  398. EmitFcvtzu_Gp_Fixed(context);
  399. }
  400. }
  401. public static void Fcvtzu_S(ArmEmitterContext context)
  402. {
  403. if (Optimizations.UseSse41)
  404. {
  405. EmitSse41FcvtuOpF(context, FPRoundingMode.TowardsZero, scalar: true);
  406. }
  407. else
  408. {
  409. EmitFcvtz(context, signed: false, scalar: true);
  410. }
  411. }
  412. public static void Fcvtzu_V(ArmEmitterContext context)
  413. {
  414. if (Optimizations.UseSse41)
  415. {
  416. EmitSse41FcvtuOpF(context, FPRoundingMode.TowardsZero, scalar: false);
  417. }
  418. else
  419. {
  420. EmitFcvtz(context, signed: false, scalar: false);
  421. }
  422. }
  423. public static void Fcvtzu_V_Fixed(ArmEmitterContext context)
  424. {
  425. if (Optimizations.UseSse41)
  426. {
  427. EmitSse41FcvtuOpF(context, FPRoundingMode.TowardsZero, scalar: false);
  428. }
  429. else
  430. {
  431. EmitFcvtz(context, signed: false, scalar: false);
  432. }
  433. }
  434. public static void Scvtf_Gp(ArmEmitterContext context)
  435. {
  436. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  437. Operand res = GetIntOrZR(context, op.Rn);
  438. if (op.RegisterSize == RegisterSize.Int32)
  439. {
  440. res = context.SignExtend32(OperandType.I64, res);
  441. }
  442. res = EmitFPConvert(context, res, op.Size, signed: true);
  443. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  444. }
  445. public static void Scvtf_Gp_Fixed(ArmEmitterContext context)
  446. {
  447. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  448. Operand res = GetIntOrZR(context, op.Rn);
  449. if (op.RegisterSize == RegisterSize.Int32)
  450. {
  451. res = context.SignExtend32(OperandType.I64, res);
  452. }
  453. res = EmitFPConvert(context, res, op.Size, signed: true);
  454. res = EmitI2fFBitsMul(context, res, op.FBits);
  455. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  456. }
  457. public static void Scvtf_S(ArmEmitterContext context)
  458. {
  459. if (Optimizations.UseSse2)
  460. {
  461. EmitSse2ScvtfOp(context, scalar: true);
  462. }
  463. else
  464. {
  465. EmitCvtf(context, signed: true, scalar: true);
  466. }
  467. }
  468. public static void Scvtf_S_Fixed(ArmEmitterContext context)
  469. {
  470. if (Optimizations.UseSse2)
  471. {
  472. EmitSse2ScvtfOp(context, scalar: true);
  473. }
  474. else
  475. {
  476. EmitCvtf(context, signed: true, scalar: true);
  477. }
  478. }
  479. public static void Scvtf_V(ArmEmitterContext context)
  480. {
  481. if (Optimizations.UseSse2)
  482. {
  483. EmitSse2ScvtfOp(context, scalar: false);
  484. }
  485. else
  486. {
  487. EmitCvtf(context, signed: true, scalar: false);
  488. }
  489. }
  490. public static void Scvtf_V_Fixed(ArmEmitterContext context)
  491. {
  492. if (Optimizations.UseSse2)
  493. {
  494. EmitSse2ScvtfOp(context, scalar: false);
  495. }
  496. else
  497. {
  498. EmitCvtf(context, signed: true, scalar: false);
  499. }
  500. }
  501. public static void Ucvtf_Gp(ArmEmitterContext context)
  502. {
  503. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  504. Operand res = GetIntOrZR(context, op.Rn);
  505. res = EmitFPConvert(context, res, op.Size, signed: false);
  506. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  507. }
  508. public static void Ucvtf_Gp_Fixed(ArmEmitterContext context)
  509. {
  510. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  511. Operand res = GetIntOrZR(context, op.Rn);
  512. res = EmitFPConvert(context, res, op.Size, signed: false);
  513. res = EmitI2fFBitsMul(context, res, op.FBits);
  514. context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
  515. }
  516. public static void Ucvtf_S(ArmEmitterContext context)
  517. {
  518. if (Optimizations.UseSse2)
  519. {
  520. EmitSse2UcvtfOp(context, scalar: true);
  521. }
  522. else
  523. {
  524. EmitCvtf(context, signed: false, scalar: true);
  525. }
  526. }
  527. public static void Ucvtf_S_Fixed(ArmEmitterContext context)
  528. {
  529. if (Optimizations.UseSse2)
  530. {
  531. EmitSse2UcvtfOp(context, scalar: true);
  532. }
  533. else
  534. {
  535. EmitCvtf(context, signed: false, scalar: true);
  536. }
  537. }
  538. public static void Ucvtf_V(ArmEmitterContext context)
  539. {
  540. if (Optimizations.UseSse2)
  541. {
  542. EmitSse2UcvtfOp(context, scalar: false);
  543. }
  544. else
  545. {
  546. EmitCvtf(context, signed: false, scalar: false);
  547. }
  548. }
  549. public static void Ucvtf_V_Fixed(ArmEmitterContext context)
  550. {
  551. if (Optimizations.UseSse2)
  552. {
  553. EmitSse2UcvtfOp(context, scalar: false);
  554. }
  555. else
  556. {
  557. EmitCvtf(context, signed: false, scalar: false);
  558. }
  559. }
  560. private static void EmitFcvt(ArmEmitterContext context, Func1I emit, bool signed, bool scalar)
  561. {
  562. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  563. Operand res = context.VectorZero();
  564. Operand n = GetVec(op.Rn);
  565. int sizeF = op.Size & 1;
  566. int sizeI = sizeF + 2;
  567. OperandType type = sizeF == 0 ? OperandType.FP32 : OperandType.FP64;
  568. int elems = !scalar ? op.GetBytesCount() >> sizeI : 1;
  569. for (int index = 0; index < elems; index++)
  570. {
  571. Operand ne = context.VectorExtract(type, n, index);
  572. Operand e = emit(ne);
  573. if (sizeF == 0)
  574. {
  575. MethodInfo info = signed
  576. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS32))
  577. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU32));
  578. e = context.Call(info, e);
  579. e = context.ZeroExtend32(OperandType.I64, e);
  580. }
  581. else /* if (sizeF == 1) */
  582. {
  583. MethodInfo info = signed
  584. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS64))
  585. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU64));
  586. e = context.Call(info, e);
  587. }
  588. res = EmitVectorInsert(context, res, e, index, sizeI);
  589. }
  590. context.Copy(GetVec(op.Rd), res);
  591. }
  592. private static void EmitFcvtz(ArmEmitterContext context, bool signed, bool scalar)
  593. {
  594. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  595. Operand res = context.VectorZero();
  596. Operand n = GetVec(op.Rn);
  597. int sizeF = op.Size & 1;
  598. int sizeI = sizeF + 2;
  599. OperandType type = sizeF == 0 ? OperandType.FP32 : OperandType.FP64;
  600. int fBits = GetFBits(context);
  601. int elems = !scalar ? op.GetBytesCount() >> sizeI : 1;
  602. for (int index = 0; index < elems; index++)
  603. {
  604. Operand ne = context.VectorExtract(type, n, index);
  605. Operand e = EmitF2iFBitsMul(context, ne, fBits);
  606. if (sizeF == 0)
  607. {
  608. MethodInfo info = signed
  609. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS32))
  610. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU32));
  611. e = context.Call(info, e);
  612. e = context.ZeroExtend32(OperandType.I64, e);
  613. }
  614. else /* if (sizeF == 1) */
  615. {
  616. MethodInfo info = signed
  617. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS64))
  618. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU64));
  619. e = context.Call(info, e);
  620. }
  621. res = EmitVectorInsert(context, res, e, index, sizeI);
  622. }
  623. context.Copy(GetVec(op.Rd), res);
  624. }
  625. private static void EmitFcvt_s_Gp(ArmEmitterContext context, Func1I emit)
  626. {
  627. EmitFcvt___Gp(context, emit, signed: true);
  628. }
  629. private static void EmitFcvt_u_Gp(ArmEmitterContext context, Func1I emit)
  630. {
  631. EmitFcvt___Gp(context, emit, signed: false);
  632. }
  633. private static void EmitFcvt___Gp(ArmEmitterContext context, Func1I emit, bool signed)
  634. {
  635. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  636. OperandType type = op.Size == 0 ? OperandType.FP32 : OperandType.FP64;
  637. Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
  638. Operand res = signed
  639. ? EmitScalarFcvts(context, emit(ne), 0)
  640. : EmitScalarFcvtu(context, emit(ne), 0);
  641. SetIntOrZR(context, op.Rd, res);
  642. }
  643. private static void EmitFcvtzs_Gp_Fixed(ArmEmitterContext context)
  644. {
  645. EmitFcvtz__Gp_Fixed(context, signed: true);
  646. }
  647. private static void EmitFcvtzu_Gp_Fixed(ArmEmitterContext context)
  648. {
  649. EmitFcvtz__Gp_Fixed(context, signed: false);
  650. }
  651. private static void EmitFcvtz__Gp_Fixed(ArmEmitterContext context, bool signed)
  652. {
  653. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  654. OperandType type = op.Size == 0 ? OperandType.FP32 : OperandType.FP64;
  655. Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
  656. Operand res = signed
  657. ? EmitScalarFcvts(context, ne, op.FBits)
  658. : EmitScalarFcvtu(context, ne, op.FBits);
  659. SetIntOrZR(context, op.Rd, res);
  660. }
  661. private static void EmitCvtf(ArmEmitterContext context, bool signed, bool scalar)
  662. {
  663. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  664. Operand res = context.VectorZero();
  665. int sizeF = op.Size & 1;
  666. int sizeI = sizeF + 2;
  667. int fBits = GetFBits(context);
  668. int elems = !scalar ? op.GetBytesCount() >> sizeI : 1;
  669. for (int index = 0; index < elems; index++)
  670. {
  671. Operand ne = EmitVectorLongExtract(context, op.Rn, index, sizeI);
  672. Operand e = EmitFPConvert(context, ne, sizeF, signed);
  673. e = EmitI2fFBitsMul(context, e, fBits);
  674. res = context.VectorInsert(res, e, index);
  675. }
  676. context.Copy(GetVec(op.Rd), res);
  677. }
  678. private static int GetFBits(ArmEmitterContext context)
  679. {
  680. if (context.CurrOp is OpCodeSimdShImm op)
  681. {
  682. return GetImmShr(op);
  683. }
  684. return 0;
  685. }
  686. private static Operand EmitFPConvert(ArmEmitterContext context, Operand value, int size, bool signed)
  687. {
  688. Debug.Assert(value.Type == OperandType.I32 || value.Type == OperandType.I64);
  689. Debug.Assert((uint)size < 2);
  690. OperandType type = size == 0 ? OperandType.FP32 : OperandType.FP64;
  691. if (signed)
  692. {
  693. return context.ConvertToFP(type, value);
  694. }
  695. else
  696. {
  697. return context.ConvertToFPUI(type, value);
  698. }
  699. }
  700. private static Operand EmitScalarFcvts(ArmEmitterContext context, Operand value, int fBits)
  701. {
  702. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  703. value = EmitF2iFBitsMul(context, value, fBits);
  704. MethodInfo info;
  705. if (context.CurrOp.RegisterSize == RegisterSize.Int32)
  706. {
  707. info = value.Type == OperandType.FP32
  708. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS32))
  709. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS32));
  710. }
  711. else
  712. {
  713. info = value.Type == OperandType.FP32
  714. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS64))
  715. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS64));
  716. }
  717. return context.Call(info, value);
  718. }
  719. private static Operand EmitScalarFcvtu(ArmEmitterContext context, Operand value, int fBits)
  720. {
  721. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  722. value = EmitF2iFBitsMul(context, value, fBits);
  723. MethodInfo info;
  724. if (context.CurrOp.RegisterSize == RegisterSize.Int32)
  725. {
  726. info = value.Type == OperandType.FP32
  727. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU32))
  728. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU32));
  729. }
  730. else
  731. {
  732. info = value.Type == OperandType.FP32
  733. ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU64))
  734. : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU64));
  735. }
  736. return context.Call(info, value);
  737. }
  738. private static Operand EmitF2iFBitsMul(ArmEmitterContext context, Operand value, int fBits)
  739. {
  740. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  741. if (fBits == 0)
  742. {
  743. return value;
  744. }
  745. if (value.Type == OperandType.FP32)
  746. {
  747. return context.Multiply(value, ConstF(MathF.Pow(2f, fBits)));
  748. }
  749. else /* if (value.Type == OperandType.FP64) */
  750. {
  751. return context.Multiply(value, ConstF(Math.Pow(2d, fBits)));
  752. }
  753. }
  754. private static Operand EmitI2fFBitsMul(ArmEmitterContext context, Operand value, int fBits)
  755. {
  756. Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
  757. if (fBits == 0)
  758. {
  759. return value;
  760. }
  761. if (value.Type == OperandType.FP32)
  762. {
  763. return context.Multiply(value, ConstF(1f / MathF.Pow(2f, fBits)));
  764. }
  765. else /* if (value.Type == OperandType.FP64) */
  766. {
  767. return context.Multiply(value, ConstF(1d / Math.Pow(2d, fBits)));
  768. }
  769. }
  770. public static Operand EmitSse2CvtDoubleToInt64OpF(ArmEmitterContext context, Operand opF, bool scalar)
  771. {
  772. Debug.Assert(opF.Type == OperandType.V128);
  773. Operand longL = context.AddIntrinsicLong (Intrinsic.X86Cvtsd2si, opF); // opFL
  774. Operand res = context.VectorCreateScalar(longL);
  775. if (!scalar)
  776. {
  777. Operand opFH = context.AddIntrinsic (Intrinsic.X86Movhlps, res, opF); // res doesn't matter.
  778. Operand longH = context.AddIntrinsicLong (Intrinsic.X86Cvtsd2si, opFH);
  779. Operand resH = context.VectorCreateScalar(longH);
  780. res = context.AddIntrinsic (Intrinsic.X86Movlhps, res, resH);
  781. }
  782. return res;
  783. }
  784. private static Operand EmitSse2CvtInt64ToDoubleOp(ArmEmitterContext context, Operand op, bool scalar)
  785. {
  786. Debug.Assert(op.Type == OperandType.V128);
  787. Operand longL = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, op); // opL
  788. Operand res = context.AddIntrinsic (Intrinsic.X86Cvtsi2sd, context.VectorZero(), longL);
  789. if (!scalar)
  790. {
  791. Operand opH = context.AddIntrinsic (Intrinsic.X86Movhlps, res, op); // res doesn't matter.
  792. Operand longH = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, opH);
  793. Operand resH = context.AddIntrinsic (Intrinsic.X86Cvtsi2sd, res, longH); // res doesn't matter.
  794. res = context.AddIntrinsic (Intrinsic.X86Movlhps, res, resH);
  795. }
  796. return res;
  797. }
  798. private static void EmitSse2ScvtfOp(ArmEmitterContext context, bool scalar)
  799. {
  800. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  801. Operand n = GetVec(op.Rn);
  802. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  803. int sizeF = op.Size & 1;
  804. if (sizeF == 0)
  805. {
  806. Operand res = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, n);
  807. if (op is OpCodeSimdShImm fixedOp)
  808. {
  809. int fBits = GetImmShr(fixedOp);
  810. // BitConverter.Int32BitsToSingle(fpScaled) == 1f / MathF.Pow(2f, fBits)
  811. int fpScaled = 0x3F800000 - fBits * 0x800000;
  812. Operand fpScaledMask = scalar
  813. ? X86GetScalar (context, fpScaled)
  814. : X86GetAllElements(context, fpScaled);
  815. res = context.AddIntrinsic(Intrinsic.X86Mulps, res, fpScaledMask);
  816. }
  817. if (scalar)
  818. {
  819. res = context.VectorZeroUpper96(res);
  820. }
  821. else if (op.RegisterSize == RegisterSize.Simd64)
  822. {
  823. res = context.VectorZeroUpper64(res);
  824. }
  825. context.Copy(GetVec(op.Rd), res);
  826. }
  827. else /* if (sizeF == 1) */
  828. {
  829. Operand res = EmitSse2CvtInt64ToDoubleOp(context, n, scalar);
  830. if (op is OpCodeSimdShImm fixedOp)
  831. {
  832. int fBits = GetImmShr(fixedOp);
  833. // BitConverter.Int64BitsToDouble(fpScaled) == 1d / Math.Pow(2d, fBits)
  834. long fpScaled = 0x3FF0000000000000L - fBits * 0x10000000000000L;
  835. Operand fpScaledMask = scalar
  836. ? X86GetScalar (context, fpScaled)
  837. : X86GetAllElements(context, fpScaled);
  838. res = context.AddIntrinsic(Intrinsic.X86Mulpd, res, fpScaledMask);
  839. }
  840. if (scalar)
  841. {
  842. res = context.VectorZeroUpper64(res);
  843. }
  844. context.Copy(GetVec(op.Rd), res);
  845. }
  846. }
  847. private static void EmitSse2UcvtfOp(ArmEmitterContext context, bool scalar)
  848. {
  849. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  850. Operand n = GetVec(op.Rn);
  851. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  852. int sizeF = op.Size & 1;
  853. if (sizeF == 0)
  854. {
  855. Operand mask = scalar // 65536.000f (1 << 16)
  856. ? X86GetScalar (context, 0x47800000)
  857. : X86GetAllElements(context, 0x47800000);
  858. Operand res = context.AddIntrinsic(Intrinsic.X86Psrld, n, Const(16));
  859. res = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res);
  860. res = context.AddIntrinsic(Intrinsic.X86Mulps, res, mask);
  861. Operand res2 = context.AddIntrinsic(Intrinsic.X86Pslld, n, Const(16));
  862. res2 = context.AddIntrinsic(Intrinsic.X86Psrld, res2, Const(16));
  863. res2 = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res2);
  864. res = context.AddIntrinsic(Intrinsic.X86Addps, res, res2);
  865. if (op is OpCodeSimdShImm fixedOp)
  866. {
  867. int fBits = GetImmShr(fixedOp);
  868. // BitConverter.Int32BitsToSingle(fpScaled) == 1f / MathF.Pow(2f, fBits)
  869. int fpScaled = 0x3F800000 - fBits * 0x800000;
  870. Operand fpScaledMask = scalar
  871. ? X86GetScalar (context, fpScaled)
  872. : X86GetAllElements(context, fpScaled);
  873. res = context.AddIntrinsic(Intrinsic.X86Mulps, res, fpScaledMask);
  874. }
  875. if (scalar)
  876. {
  877. res = context.VectorZeroUpper96(res);
  878. }
  879. else if (op.RegisterSize == RegisterSize.Simd64)
  880. {
  881. res = context.VectorZeroUpper64(res);
  882. }
  883. context.Copy(GetVec(op.Rd), res);
  884. }
  885. else /* if (sizeF == 1) */
  886. {
  887. Operand mask = scalar // 4294967296.0000000d (1L << 32)
  888. ? X86GetScalar (context, 0x41F0000000000000L)
  889. : X86GetAllElements(context, 0x41F0000000000000L);
  890. Operand res = context.AddIntrinsic (Intrinsic.X86Psrlq, n, Const(32));
  891. res = EmitSse2CvtInt64ToDoubleOp(context, res, scalar);
  892. res = context.AddIntrinsic (Intrinsic.X86Mulpd, res, mask);
  893. Operand res2 = context.AddIntrinsic (Intrinsic.X86Psllq, n, Const(32));
  894. res2 = context.AddIntrinsic (Intrinsic.X86Psrlq, res2, Const(32));
  895. res2 = EmitSse2CvtInt64ToDoubleOp(context, res2, scalar);
  896. res = context.AddIntrinsic(Intrinsic.X86Addpd, res, res2);
  897. if (op is OpCodeSimdShImm fixedOp)
  898. {
  899. int fBits = GetImmShr(fixedOp);
  900. // BitConverter.Int64BitsToDouble(fpScaled) == 1d / Math.Pow(2d, fBits)
  901. long fpScaled = 0x3FF0000000000000L - fBits * 0x10000000000000L;
  902. Operand fpScaledMask = scalar
  903. ? X86GetScalar (context, fpScaled)
  904. : X86GetAllElements(context, fpScaled);
  905. res = context.AddIntrinsic(Intrinsic.X86Mulpd, res, fpScaledMask);
  906. }
  907. if (scalar)
  908. {
  909. res = context.VectorZeroUpper64(res);
  910. }
  911. context.Copy(GetVec(op.Rd), res);
  912. }
  913. }
  914. private static void EmitSse41FcvtsOpF(ArmEmitterContext context, FPRoundingMode roundMode, bool scalar)
  915. {
  916. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  917. Operand n = GetVec(op.Rn);
  918. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  919. int sizeF = op.Size & 1;
  920. if (sizeF == 0)
  921. {
  922. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, n, n, Const((int)CmpCondition.OrderedQ));
  923. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  924. if (op is OpCodeSimdShImm fixedOp)
  925. {
  926. int fBits = GetImmShr(fixedOp);
  927. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, fBits)
  928. int fpScaled = 0x3F800000 + fBits * 0x800000;
  929. Operand fpScaledMask = scalar
  930. ? X86GetScalar (context, fpScaled)
  931. : X86GetAllElements(context, fpScaled);
  932. nRes = context.AddIntrinsic(Intrinsic.X86Mulps, nRes, fpScaledMask);
  933. }
  934. nRes = context.AddIntrinsic(Intrinsic.X86Roundps, nRes, Const(X86GetRoundControl(roundMode)));
  935. Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes);
  936. Operand fpMaxValMask = scalar // 2.14748365E9f (2147483648)
  937. ? X86GetScalar (context, 0x4F000000)
  938. : X86GetAllElements(context, 0x4F000000);
  939. nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  940. Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nInt, nRes);
  941. if (scalar)
  942. {
  943. dRes = context.VectorZeroUpper96(dRes);
  944. }
  945. else if (op.RegisterSize == RegisterSize.Simd64)
  946. {
  947. dRes = context.VectorZeroUpper64(dRes);
  948. }
  949. context.Copy(GetVec(op.Rd), dRes);
  950. }
  951. else /* if (sizeF == 1) */
  952. {
  953. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, n, n, Const((int)CmpCondition.OrderedQ));
  954. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  955. if (op is OpCodeSimdShImm fixedOp)
  956. {
  957. int fBits = GetImmShr(fixedOp);
  958. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, fBits)
  959. long fpScaled = 0x3FF0000000000000L + fBits * 0x10000000000000L;
  960. Operand fpScaledMask = scalar
  961. ? X86GetScalar (context, fpScaled)
  962. : X86GetAllElements(context, fpScaled);
  963. nRes = context.AddIntrinsic(Intrinsic.X86Mulpd, nRes, fpScaledMask);
  964. }
  965. nRes = context.AddIntrinsic(Intrinsic.X86Roundpd, nRes, Const(X86GetRoundControl(roundMode)));
  966. Operand nLong = EmitSse2CvtDoubleToInt64OpF(context, nRes, scalar);
  967. Operand fpMaxValMask = scalar // 9.2233720368547760E18d (9223372036854775808)
  968. ? X86GetScalar (context, 0x43E0000000000000L)
  969. : X86GetAllElements(context, 0x43E0000000000000L);
  970. nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  971. Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nLong, nRes);
  972. if (scalar)
  973. {
  974. dRes = context.VectorZeroUpper64(dRes);
  975. }
  976. context.Copy(GetVec(op.Rd), dRes);
  977. }
  978. }
  979. private static void EmitSse41FcvtuOpF(ArmEmitterContext context, FPRoundingMode roundMode, bool scalar)
  980. {
  981. OpCodeSimd op = (OpCodeSimd)context.CurrOp;
  982. Operand n = GetVec(op.Rn);
  983. // sizeF == ((OpCodeSimdShImm)op).Size - 2
  984. int sizeF = op.Size & 1;
  985. if (sizeF == 0)
  986. {
  987. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, n, n, Const((int)CmpCondition.OrderedQ));
  988. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  989. if (op is OpCodeSimdShImm fixedOp)
  990. {
  991. int fBits = GetImmShr(fixedOp);
  992. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, fBits)
  993. int fpScaled = 0x3F800000 + fBits * 0x800000;
  994. Operand fpScaledMask = scalar
  995. ? X86GetScalar (context, fpScaled)
  996. : X86GetAllElements(context, fpScaled);
  997. nRes = context.AddIntrinsic(Intrinsic.X86Mulps, nRes, fpScaledMask);
  998. }
  999. nRes = context.AddIntrinsic(Intrinsic.X86Roundps, nRes, Const(X86GetRoundControl(roundMode)));
  1000. Operand zero = context.VectorZero();
  1001. Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1002. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1003. Operand fpMaxValMask = scalar // 2.14748365E9f (2147483648)
  1004. ? X86GetScalar (context, 0x4F000000)
  1005. : X86GetAllElements(context, 0x4F000000);
  1006. Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes);
  1007. nRes = context.AddIntrinsic(Intrinsic.X86Subps, nRes, fpMaxValMask);
  1008. nCmp = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1009. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1010. Operand nInt2 = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes);
  1011. nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1012. Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nInt2, nRes);
  1013. dRes = context.AddIntrinsic(Intrinsic.X86Paddd, dRes, nInt);
  1014. if (scalar)
  1015. {
  1016. dRes = context.VectorZeroUpper96(dRes);
  1017. }
  1018. else if (op.RegisterSize == RegisterSize.Simd64)
  1019. {
  1020. dRes = context.VectorZeroUpper64(dRes);
  1021. }
  1022. context.Copy(GetVec(op.Rd), dRes);
  1023. }
  1024. else /* if (sizeF == 1) */
  1025. {
  1026. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, n, n, Const((int)CmpCondition.OrderedQ));
  1027. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1028. if (op is OpCodeSimdShImm fixedOp)
  1029. {
  1030. int fBits = GetImmShr(fixedOp);
  1031. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, fBits)
  1032. long fpScaled = 0x3FF0000000000000L + fBits * 0x10000000000000L;
  1033. Operand fpScaledMask = scalar
  1034. ? X86GetScalar (context, fpScaled)
  1035. : X86GetAllElements(context, fpScaled);
  1036. nRes = context.AddIntrinsic(Intrinsic.X86Mulpd, nRes, fpScaledMask);
  1037. }
  1038. nRes = context.AddIntrinsic(Intrinsic.X86Roundpd, nRes, Const(X86GetRoundControl(roundMode)));
  1039. Operand zero = context.VectorZero();
  1040. Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1041. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1042. Operand fpMaxValMask = scalar // 9.2233720368547760E18d (9223372036854775808)
  1043. ? X86GetScalar (context, 0x43E0000000000000L)
  1044. : X86GetAllElements(context, 0x43E0000000000000L);
  1045. Operand nLong = EmitSse2CvtDoubleToInt64OpF(context, nRes, scalar);
  1046. nRes = context.AddIntrinsic(Intrinsic.X86Subpd, nRes, fpMaxValMask);
  1047. nCmp = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1048. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1049. Operand nLong2 = EmitSse2CvtDoubleToInt64OpF(context, nRes, scalar);
  1050. nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1051. Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nLong2, nRes);
  1052. dRes = context.AddIntrinsic(Intrinsic.X86Paddq, dRes, nLong);
  1053. if (scalar)
  1054. {
  1055. dRes = context.VectorZeroUpper64(dRes);
  1056. }
  1057. context.Copy(GetVec(op.Rd), dRes);
  1058. }
  1059. }
  1060. private static void EmitSse41Fcvts_Gp(ArmEmitterContext context, FPRoundingMode roundMode, bool isFixed)
  1061. {
  1062. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  1063. Operand n = GetVec(op.Rn);
  1064. if (op.Size == 0)
  1065. {
  1066. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, n, n, Const((int)CmpCondition.OrderedQ));
  1067. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1068. if (isFixed)
  1069. {
  1070. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, op.FBits)
  1071. int fpScaled = 0x3F800000 + op.FBits * 0x800000;
  1072. Operand fpScaledMask = X86GetScalar(context, fpScaled);
  1073. nRes = context.AddIntrinsic(Intrinsic.X86Mulss, nRes, fpScaledMask);
  1074. }
  1075. nRes = context.AddIntrinsic(Intrinsic.X86Roundss, nRes, Const(X86GetRoundControl(roundMode)));
  1076. Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
  1077. ? context.AddIntrinsicInt (Intrinsic.X86Cvtss2si, nRes)
  1078. : context.AddIntrinsicLong(Intrinsic.X86Cvtss2si, nRes);
  1079. int fpMaxVal = op.RegisterSize == RegisterSize.Int32
  1080. ? 0x4F000000 // 2.14748365E9f (2147483648)
  1081. : 0x5F000000; // 9.223372E18f (9223372036854775808)
  1082. Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
  1083. nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1084. Operand nInt = context.AddIntrinsicInt(Intrinsic.X86Cvtsi2si, nRes);
  1085. if (op.RegisterSize == RegisterSize.Int64)
  1086. {
  1087. nInt = context.SignExtend32(OperandType.I64, nInt);
  1088. }
  1089. Operand dRes = context.BitwiseExclusiveOr(nIntOrLong, nInt);
  1090. SetIntOrZR(context, op.Rd, dRes);
  1091. }
  1092. else /* if (op.Size == 1) */
  1093. {
  1094. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, n, n, Const((int)CmpCondition.OrderedQ));
  1095. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1096. if (isFixed)
  1097. {
  1098. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, op.FBits)
  1099. long fpScaled = 0x3FF0000000000000L + op.FBits * 0x10000000000000L;
  1100. Operand fpScaledMask = X86GetScalar(context, fpScaled);
  1101. nRes = context.AddIntrinsic(Intrinsic.X86Mulsd, nRes, fpScaledMask);
  1102. }
  1103. nRes = context.AddIntrinsic(Intrinsic.X86Roundsd, nRes, Const(X86GetRoundControl(roundMode)));
  1104. Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
  1105. ? context.AddIntrinsicInt (Intrinsic.X86Cvtsd2si, nRes)
  1106. : context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRes);
  1107. long fpMaxVal = op.RegisterSize == RegisterSize.Int32
  1108. ? 0x41E0000000000000L // 2147483648.0000000d (2147483648)
  1109. : 0x43E0000000000000L; // 9.2233720368547760E18d (9223372036854775808)
  1110. Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
  1111. nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1112. Operand nLong = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, nRes);
  1113. if (op.RegisterSize == RegisterSize.Int32)
  1114. {
  1115. nLong = context.ConvertI64ToI32(nLong);
  1116. }
  1117. Operand dRes = context.BitwiseExclusiveOr(nIntOrLong, nLong);
  1118. SetIntOrZR(context, op.Rd, dRes);
  1119. }
  1120. }
  1121. private static void EmitSse41Fcvtu_Gp(ArmEmitterContext context, FPRoundingMode roundMode, bool isFixed)
  1122. {
  1123. OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
  1124. Operand n = GetVec(op.Rn);
  1125. if (op.Size == 0)
  1126. {
  1127. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, n, n, Const((int)CmpCondition.OrderedQ));
  1128. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1129. if (isFixed)
  1130. {
  1131. // BitConverter.Int32BitsToSingle(fpScaled) == MathF.Pow(2f, op.FBits)
  1132. int fpScaled = 0x3F800000 + op.FBits * 0x800000;
  1133. Operand fpScaledMask = X86GetScalar(context, fpScaled);
  1134. nRes = context.AddIntrinsic(Intrinsic.X86Mulss, nRes, fpScaledMask);
  1135. }
  1136. nRes = context.AddIntrinsic(Intrinsic.X86Roundss, nRes, Const(X86GetRoundControl(roundMode)));
  1137. Operand zero = context.VectorZero();
  1138. Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1139. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1140. int fpMaxVal = op.RegisterSize == RegisterSize.Int32
  1141. ? 0x4F000000 // 2.14748365E9f (2147483648)
  1142. : 0x5F000000; // 9.223372E18f (9223372036854775808)
  1143. Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
  1144. Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
  1145. ? context.AddIntrinsicInt (Intrinsic.X86Cvtss2si, nRes)
  1146. : context.AddIntrinsicLong(Intrinsic.X86Cvtss2si, nRes);
  1147. nRes = context.AddIntrinsic(Intrinsic.X86Subss, nRes, fpMaxValMask);
  1148. nCmp = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1149. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1150. Operand nIntOrLong2 = op.RegisterSize == RegisterSize.Int32
  1151. ? context.AddIntrinsicInt (Intrinsic.X86Cvtss2si, nRes)
  1152. : context.AddIntrinsicLong(Intrinsic.X86Cvtss2si, nRes);
  1153. nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1154. Operand nInt = context.AddIntrinsicInt(Intrinsic.X86Cvtsi2si, nRes);
  1155. if (op.RegisterSize == RegisterSize.Int64)
  1156. {
  1157. nInt = context.SignExtend32(OperandType.I64, nInt);
  1158. }
  1159. Operand dRes = context.BitwiseExclusiveOr(nIntOrLong2, nInt);
  1160. dRes = context.Add(dRes, nIntOrLong);
  1161. SetIntOrZR(context, op.Rd, dRes);
  1162. }
  1163. else /* if (op.Size == 1) */
  1164. {
  1165. Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, n, n, Const((int)CmpCondition.OrderedQ));
  1166. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
  1167. if (isFixed)
  1168. {
  1169. // BitConverter.Int64BitsToDouble(fpScaled) == Math.Pow(2d, op.FBits)
  1170. long fpScaled = 0x3FF0000000000000L + op.FBits * 0x10000000000000L;
  1171. Operand fpScaledMask = X86GetScalar(context, fpScaled);
  1172. nRes = context.AddIntrinsic(Intrinsic.X86Mulsd, nRes, fpScaledMask);
  1173. }
  1174. nRes = context.AddIntrinsic(Intrinsic.X86Roundsd, nRes, Const(X86GetRoundControl(roundMode)));
  1175. Operand zero = context.VectorZero();
  1176. Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1177. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1178. long fpMaxVal = op.RegisterSize == RegisterSize.Int32
  1179. ? 0x41E0000000000000L // 2147483648.0000000d (2147483648)
  1180. : 0x43E0000000000000L; // 9.2233720368547760E18d (9223372036854775808)
  1181. Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
  1182. Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
  1183. ? context.AddIntrinsicInt (Intrinsic.X86Cvtsd2si, nRes)
  1184. : context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRes);
  1185. nRes = context.AddIntrinsic(Intrinsic.X86Subsd, nRes, fpMaxValMask);
  1186. nCmp = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
  1187. nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
  1188. Operand nIntOrLong2 = op.RegisterSize == RegisterSize.Int32
  1189. ? context.AddIntrinsicInt (Intrinsic.X86Cvtsd2si, nRes)
  1190. : context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRes);
  1191. nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
  1192. Operand nLong = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, nRes);
  1193. if (op.RegisterSize == RegisterSize.Int32)
  1194. {
  1195. nLong = context.ConvertI64ToI32(nLong);
  1196. }
  1197. Operand dRes = context.BitwiseExclusiveOr(nIntOrLong2, nLong);
  1198. dRes = context.Add(dRes, nIntOrLong);
  1199. SetIntOrZR(context, op.Rd, dRes);
  1200. }
  1201. }
  1202. private static Operand EmitVectorLongExtract(ArmEmitterContext context, int reg, int index, int size)
  1203. {
  1204. OperandType type = size == 3 ? OperandType.I64 : OperandType.I32;
  1205. return context.VectorExtract(type, GetVec(reg), index);
  1206. }
  1207. }
  1208. }