| .. |
|
ACryptoHelper.cs
|
d021d5dfa9
Add AESD, AESE, AESIMC, AESMC instructions; add 4 simple Tests (closed box). (#365)
|
7 anni fa |
|
AInst.cs
|
9670c096e4
Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now)
|
8 anni fa |
|
AInstEmitAlu.cs
|
c99b2884e4
Remove broken adds/cmn with condition check optimization (#218)
|
8 anni fa |
|
AInstEmitAluHelper.cs
|
708761963e
Fix corner cases of ADCS and SBFM
|
8 anni fa |
|
AInstEmitBfm.cs
|
708761963e
Fix corner cases of ADCS and SBFM
|
8 anni fa |
|
AInstEmitCcmp.cs
|
62b827f474
Split main project into core,graphics and chocolarm4 subproject (#29)
|
8 anni fa |
|
AInstEmitCsel.cs
|
950011c90f
Added initial support for function names from symbol table on the cpu with tracing, fix wrong ImageEnd on executables with MOD0, fix issue on the CPU on input elimination for instruction with more than one register store
|
8 anni fa |
|
AInstEmitException.cs
|
65105c2a3b
Implement SvcGetThreadContext3
|
8 anni fa |
|
AInstEmitFlow.cs
|
6d65e53664
Remove cold methods from the CPU cache (#224)
|
7 anni fa |
|
AInstEmitHash.cs
|
8f6387128a
Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
|
8 anni fa |
|
AInstEmitMemory.cs
|
4731c7545d
Fix mistake on astc conversion, make some static methods that shouldn't be public private, remove old commmented out code
|
8 anni fa |
|
AInstEmitMemoryEx.cs
|
b8133c1997
Thread scheduler rewrite (#393)
|
7 anni fa |
|
AInstEmitMemoryHelper.cs
|
c393cdf8e3
More flexible memory manager (#307)
|
7 anni fa |
|
AInstEmitMove.cs
|
62b827f474
Split main project into core,graphics and chocolarm4 subproject (#29)
|
8 anni fa |
|
AInstEmitMul.cs
|
62b827f474
Split main project into core,graphics and chocolarm4 subproject (#29)
|
8 anni fa |
|
AInstEmitSimdArithmetic.cs
|
0b52ee6627
Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)
|
7 anni fa |
|
AInstEmitSimdCmp.cs
|
0b52ee6627
Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)
|
7 anni fa |
|
AInstEmitSimdCrypto.cs
|
d021d5dfa9
Add AESD, AESE, AESIMC, AESMC instructions; add 4 simple Tests (closed box). (#365)
|
7 anni fa |
|
AInstEmitSimdCvt.cs
|
0b52ee6627
Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)
|
7 anni fa |
|
AInstEmitSimdHash.cs
|
34100051e4
Add SHA256H, SHA256H2, SHA256SU0, SHA256SU1 instructions; add 4 Tests (closed box). (#352)
|
7 anni fa |
|
AInstEmitSimdHelper.cs
|
0b52ee6627
Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)
|
7 anni fa |
|
AInstEmitSimdLogical.cs
|
0b52ee6627
Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)
|
7 anni fa |
|
AInstEmitSimdMemory.cs
|
514218ab98
Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225)
|
8 anni fa |
|
AInstEmitSimdMove.cs
|
0b52ee6627
Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)
|
7 anni fa |
|
AInstEmitSimdShift.cs
|
c7387be0d2
Fix/Add 1+12 [Saturating] [Rounded] Shift Right Narrow (imm.) Instructions; add 14 Tests. Add 6 Tests for PR#405. Add 2 Tests for PR#412. (#409)
|
7 anni fa |
|
AInstEmitSystem.cs
|
2ed24af756
Add pl:u stub, use higher precision on CNTPCT_EL0 register tick count
|
8 anni fa |
|
AInstEmitter.cs
|
62b827f474
Split main project into core,graphics and chocolarm4 subproject (#29)
|
8 anni fa |
|
AInstInterpreter.cs
|
9670c096e4
Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now)
|
8 anni fa |
|
ASoftFallback.cs
|
a0c78f7920
Fix/Add 10 Shift Right and Mls_Ve Instructions; add 14 Tests. (#407)
|
7 anni fa |
|
ASoftFloat.cs
|
3cf1b6cf77
Fix silly copy/paste error on float variant of the FMINNM instruction
|
7 anni fa |
|
AVectorHelper.cs
|
0b52ee6627
Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)
|
7 anni fa |
gdkchan