| .. |
|
CpuTest.cs
|
9d7627af64
Add multi-level function table (#2228)
|
há 4 anos atrás |
|
CpuTest32.cs
|
9d7627af64
Add multi-level function table (#2228)
|
há 4 anos atrás |
|
CpuTestAlu.cs
|
d87c5375f1
Implement a custom value generator for the Tests of the CLS and CLZ instructions (Base: 32, 64 bits. Simd: 8, 16, 32 bits). (#696)
|
há 6 anos atrás |
|
CpuTestAlu32.cs
|
fb0939f9b6
Add SSAT, SSAT16, USAT and USAT16 ARM32 instructions (#954)
|
há 6 anos atrás |
|
CpuTestAluBinary.cs
|
d7044b10a2
Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328)
|
há 5 anos atrás |
|
CpuTestAluBinary32.cs
|
d7044b10a2
Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328)
|
há 5 anos atrás |
|
CpuTestAluImm.cs
|
1e7ea76f14
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
|
há 7 anos atrás |
|
CpuTestAluRs.cs
|
a731ab3a2a
Add a new JIT compiler for CPU code (#693)
|
há 6 anos atrás |
|
CpuTestAluRs32.cs
|
b1b6f294f2
Add most of the A32 instruction set to ARMeilleure (#897)
|
há 6 anos atrás |
|
CpuTestAluRx.cs
|
1e7ea76f14
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
|
há 7 anos atrás |
|
CpuTestBf32.cs
|
b1b6f294f2
Add most of the A32 instruction set to ARMeilleure (#897)
|
há 6 anos atrás |
|
CpuTestBfm.cs
|
1e7ea76f14
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
|
há 7 anos atrás |
|
CpuTestCcmpImm.cs
|
1e7ea76f14
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
|
há 7 anos atrás |
|
CpuTestCcmpReg.cs
|
1e7ea76f14
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
|
há 7 anos atrás |
|
CpuTestCsel.cs
|
1e7ea76f14
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
|
há 7 anos atrás |
|
CpuTestMisc.cs
|
a804db6eed
Add Fmax/minv_V & S/Ushl_S Inst.s with Tests. Fix Maxps/d & Minps/d d… (#1335)
|
há 5 anos atrás |
|
CpuTestMisc32.cs
|
e36e97c64d
CPU: This PR fixes Fpscr, among other things. (#1433)
|
há 5 anos atrás |
|
CpuTestMov.cs
|
d87c5375f1
Implement a custom value generator for the Tests of the CLS and CLZ instructions (Base: 32, 64 bits. Simd: 8, 16, 32 bits). (#696)
|
há 6 anos atrás |
|
CpuTestMul.cs
|
1e7ea76f14
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
|
há 7 anos atrás |
|
CpuTestMul32.cs
|
fb0939f9b6
Add SSAT, SSAT16, USAT and USAT16 ARM32 instructions (#954)
|
há 6 anos atrás |
|
CpuTestSimd.cs
|
c3e0c41da3
CPU (A64): Add Fmaxnmp & Fminnmp Scalar Inst.s, Fast & Slow Paths; with Tests. (#1894)
|
há 5 anos atrás |
|
CpuTestSimd32.cs
|
9bda7b4699
Implement VCNT instruction (#1963)
|
há 5 anos atrás |
|
CpuTestSimdCrypto.cs
|
a731ab3a2a
Add a new JIT compiler for CPU code (#693)
|
há 6 anos atrás |
|
CpuTestSimdCrypto32.cs
|
dd433c1296
Implement AESMC, AESIMC, AESE, AESD and VEOR AArch32 instructions (#982)
|
há 6 anos atrás |
|
CpuTestSimdCvt.cs
|
0915731a9d
Implemented fast paths for: (#846)
|
há 6 anos atrás |
|
CpuTestSimdCvt32.cs
|
8a33e884f8
Fix Vnmls_S fast path (F64: losing input d value). Fix Vnmla_S & Vnmls_S slow paths (using fused inst.s). Fix Vfma_V slow path not using StandardFPSCRValue(). (#1775)
|
há 5 anos atrás |
|
CpuTestSimdExt.cs
|
a731ab3a2a
Add a new JIT compiler for CPU code (#693)
|
há 6 anos atrás |
|
CpuTestSimdFcond.cs
|
a731ab3a2a
Add a new JIT compiler for CPU code (#693)
|
há 6 anos atrás |
|
CpuTestSimdFmov.cs
|
a731ab3a2a
Add a new JIT compiler for CPU code (#693)
|
há 6 anos atrás |
|
CpuTestSimdImm.cs
|
a731ab3a2a
Add a new JIT compiler for CPU code (#693)
|
há 6 anos atrás |
|
CpuTestSimdIns.cs
|
a731ab3a2a
Add a new JIT compiler for CPU code (#693)
|
há 6 anos atrás |
|
CpuTestSimdLogical32.cs
|
ab9d4b862d
Implement VORN (register) Arm32 instruction (#2396)
|
há 4 anos atrás |
|
CpuTestSimdMemory32.cs
|
e36e97c64d
CPU: This PR fixes Fpscr, among other things. (#1433)
|
há 5 anos atrás |
|
CpuTestSimdMov32.cs
|
9a49f8aec9
Fix VMVN (immediate), Add VPMIN, VPMAX, VMVN (register) (#1303)
|
há 5 anos atrás |
|
CpuTestSimdReg.cs
|
430ba6da65
CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)
|
há 5 anos atrás |
|
CpuTestSimdReg32.cs
|
430ba6da65
CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)
|
há 5 anos atrás |
|
CpuTestSimdRegElem.cs
|
4bd1ad16f9
Add Sqdmulh_Ve & Sqrdmulh_Ve Inst.s with Tests. (#2139)
|
há 5 anos atrás |
|
CpuTestSimdRegElem32.cs
|
c26f3774bd
Implement VMULL, VMLSL, VRSHR, VQRSHRN, VQRSHRUN AArch32 instructions + other fixes (#977)
|
há 6 anos atrás |
|
CpuTestSimdRegElemF.cs
|
a731ab3a2a
Add a new JIT compiler for CPU code (#693)
|
há 6 anos atrás |
|
CpuTestSimdShImm.cs
|
2cb8bd7006
CPU (A64): Add Scvtf_S_Fixed & Ucvtf_S_Fixed with Tests. (#1492)
|
há 5 anos atrás |
|
CpuTestSimdShImm32.cs
|
e36e97c64d
CPU: This PR fixes Fpscr, among other things. (#1433)
|
há 5 anos atrás |
|
CpuTestSimdTbl.cs
|
16869402bf
Add Tbx Inst. (fast & slow paths), with Tests. (#782)
|
há 6 anos atrás |
|
CpuTestSystem.cs
|
7c111a3567
Add Mrs & Msr (Nzcv) Inst., with Tests. (#819)
|
há 6 anos atrás |
gdkchan
ab9d4b862d
Implement VORN (register) Arm32 instruction (#2396)