Arm32Register.cs 1.8 KB

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  1. using System;
  2. using System.Collections.Generic;
  3. using System.Text;
  4. namespace Ryujinx.Tests.Unicorn.Native
  5. {
  6. public enum Arm32Register
  7. {
  8. INVALID = 0,
  9. APSR,
  10. APSR_NZCV,
  11. CPSR,
  12. FPEXC,
  13. FPINST,
  14. FPSCR,
  15. FPSCR_NZCV,
  16. FPSID,
  17. ITSTATE,
  18. LR,
  19. PC,
  20. SP,
  21. SPSR,
  22. D0,
  23. D1,
  24. D2,
  25. D3,
  26. D4,
  27. D5,
  28. D6,
  29. D7,
  30. D8,
  31. D9,
  32. D10,
  33. D11,
  34. D12,
  35. D13,
  36. D14,
  37. D15,
  38. D16,
  39. D17,
  40. D18,
  41. D19,
  42. D20,
  43. D21,
  44. D22,
  45. D23,
  46. D24,
  47. D25,
  48. D26,
  49. D27,
  50. D28,
  51. D29,
  52. D30,
  53. D31,
  54. FPINST2,
  55. MVFR0,
  56. MVFR1,
  57. MVFR2,
  58. Q0,
  59. Q1,
  60. Q2,
  61. Q3,
  62. Q4,
  63. Q5,
  64. Q6,
  65. Q7,
  66. Q8,
  67. Q9,
  68. Q10,
  69. Q11,
  70. Q12,
  71. Q13,
  72. Q14,
  73. Q15,
  74. R0,
  75. R1,
  76. R2,
  77. R3,
  78. R4,
  79. R5,
  80. R6,
  81. R7,
  82. R8,
  83. R9,
  84. R10,
  85. R11,
  86. R12,
  87. S0,
  88. S1,
  89. S2,
  90. S3,
  91. S4,
  92. S5,
  93. S6,
  94. S7,
  95. S8,
  96. S9,
  97. S10,
  98. S11,
  99. S12,
  100. S13,
  101. S14,
  102. S15,
  103. S16,
  104. S17,
  105. S18,
  106. S19,
  107. S20,
  108. S21,
  109. S22,
  110. S23,
  111. S24,
  112. S25,
  113. S26,
  114. S27,
  115. S28,
  116. S29,
  117. S30,
  118. S31,
  119. C1_C0_2,
  120. C13_C0_2,
  121. C13_C0_3,
  122. IPSR,
  123. MSP,
  124. PSP,
  125. CONTROL,
  126. ENDING,
  127. // Alias registers.
  128. R13 = SP,
  129. R14 = LR,
  130. R15 = PC,
  131. SB = R9,
  132. SL = R10,
  133. FP = R11,
  134. IP = R12,
  135. }
  136. }