alancnet/ryujinx

Auteur	SHA1 Message	Date
gdkchan	8e119a1e96 Implement PLD and SUB (imm16) on T32, plus UADD8, SADD8, USUB8 and SSUB8 on both A32 and T32 (#3693)	il y a 3 ans
LDj3SNuD	e36e97c64d CPU: This PR fixes Fpscr, among other things. (#1433)	il y a 5 ans
gdkchan	fb0939f9b6 Add SSAT, SSAT16, USAT and USAT16 ARM32 instructions (#954)	il y a 6 ans
gdkchan	a731ab3a2a Add a new JIT compiler for CPU code (#693)	il y a 6 ans