 LDj3SNuD
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814f75142e
Fpsr and Fpcr freed. (#3701)
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3 år sedan |
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LDj3SNuD
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b9f1ff3c77
Implemented in IR the managed methods of the ShlReg region of the SoftFallback class. (#3700)
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3 år sedan |
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LDj3SNuD
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7baa08dcb4
Implemented in IR the managed methods of the Saturating region ... (#3665)
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3 år sedan |
 gdkchan
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f7ef6364b7
Implement CPU FCVT Half <-> Double conversion variants (#3439)
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3 år sedan |
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gdkchan
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0c87bf9ea4
Refactor CPU interface to allow the implementation of other CPU emulators (#3362)
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3 år sedan |
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gdkchan
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92d166ecb7
Enable CPU JIT cache invalidation (#2965)
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4 år sedan |
 FICTURE7
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9d7627af64
Add multi-level function table (#2228)
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4 år sedan |
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FICTURE7
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89791ba68d
Add inlined on translation call counting (#2190)
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5 år sedan |
 mageven
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9bda7b4699
Implement VCNT instruction (#1963)
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5 år sedan |
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LDj3SNuD
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430ba6da65
CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)
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5 år sedan |
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gdkchan
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61634dd415
Clear JIT cache on exit (#1518)
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5 år sedan |
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LDj3SNuD
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567ea726e1
Add support for guest Fz (Fpcr) mode through host Ftz and Daz (Mxcsr) modes (fast paths). (#1630)
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5 år sedan |
 riperiperi
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b4d8d893a4
Memory Read/Write Tracking using Region Handles (#1272)
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5 år sedan |
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LDj3SNuD
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e36e97c64d
CPU: This PR fixes Fpscr, among other things. (#1433)
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5 år sedan |
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gdkchan
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9878fc2d3c
Implement inline memory load/store exclusive and ordered (#1413)
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5 år sedan |
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LDj3SNuD
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5e724cf24e
Add Profiled Persistent Translation Cache. (#769)
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5 år sedan |
