Cronologia Commit

Autore SHA1 Messaggio Data
  gdkchan 741773910d Add SMAXP, SMINP, UMAX, UMAXP, UMIN and UMINP cpu instructions (#200) 7 anni fa
  LDj3SNuD c228cf320d Add Rbit_V instruction. Add 8 tests (Rbit_V; Rev16_V, Rev32_V, Rev64_V). Improve CountSetBits8() algorithm. (#212) 7 anni fa
  LDj3SNuD 53934e8872 Add Saba_V, Sabal_V, Sabd_V, Sabdl_V, Uaba_V, Uabal_V; Update Uabd_V, Uabdl_V. Add 16 tests. (#204) 7 anni fa
  gdkchan bc26aa558a Add support for the FMLA (by element/scalar) instruction (#187) 7 anni fa
  LDj3SNuD 8f6387128a Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183) 7 anni fa
  gdkchan 37a6e84fd4 Add REV16/32 (vector) instructions and fix REV64 7 anni fa
  Rygnus 0bec9d8439 Add opcodes SQXTUN_S and SQXTUN_V (#184) 7 anni fa
  LDj3SNuD 3bdd109f45 Add Cmeq_S, Cmge_S, Cmgt_S, Cmhi_S, Cmhs_S, Cmle_S, Cmlt_S (Reg, Zero) & Cmtst_S compare instructions. Add 22 compare tests (Scalar, Vector). Add Eor_V, Not_V tests. (#171) 7 anni fa
  gdkchan b747b23607 Add the FADDP (scalar) instruction 7 anni fa
  Lordmau5 46dc89f8dd Implement Fabs_V (#146) 7 anni fa
  gdkchan 9670c096e4 Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now) 8 anni fa
  gdkchan 7ac5f40532 Add scalar variants of FCVTZS/FCVTZU, fix a issue on Ryushader 8 anni fa
  LDj3SNuD 7cda630aba Add Sqxtn_S, Sqxtn_V, Uqxtn_S, Uqxtn_V instructions and Tests (6). (#110) 8 anni fa
  LDj3SNuD 2f1250ab04 Update AOpCodeTable.cs (#108) 8 anni fa
  LDj3SNuD a5ad1e9a06 Add Cls_V, Clz_V, Orn_V instructions. Add 18 Tests: And_V, Bic_V, Bif_V, Bit_V, Bsl_V, Cls_V, Clz_V, Orn_V, Orr_V. (#104) 8 anni fa
  LDj3SNuD 302c1d2861 Fix Addp_S in AOpCodeTable. Add 5 Tests: ADDP (scalar), ADDP (vector), ADDV. (#96) 8 anni fa
  LDj3SNuD 2ccd995cb2 Add ADDHN{2}, RADDHN{2}, SUBHN{2}, RSUBHN{2} (vector) instructions. Add 8 Tests. (#92) 8 anni fa
  MS-DOS1999 76a5972378 Fix Fmin/max and add vector version, add and modifying fmin/max tests (#89) 8 anni fa
  LDj3SNuD 8b75080639 Add ABS (scalar & vector), ADD (scalar), NEG (scalar) instructions. (#88) 8 anni fa
  LDj3SNuD 262b5b8054 Add TRN1 & TRN2 (vector) instructions. Add 4 simple tests (4S, 8B). (#77) 8 anni fa
  LDj3SNuD 7acd0e0122 Add FMUL (scalar, by element) instruction; add FRECPE, FRECPS (scalar & vector) instructions. Add 5 simple tests. (#74) 8 anni fa
  gdkchan 36d9130592 Add FMLS (vector) instruction 8 anni fa
  gdkchan f15b1c76a1 Add FRSQRTS and FCM* instructions 8 anni fa
  Merry 39f20d8d1a Implement Frsqrte_S (#72) 8 anni fa
  gdkchan 45c078d782 Add Faddp (vector) instruction 8 anni fa
  gdkchan a20d6b34ab Add PRFM (unscaled) instruction 8 anni fa
  gdkchan 7fe12ad169 Add FNEG (vector) instruction 8 anni fa
  gdkchan 53e2d34905 Enable all ld/st (single structure) instructions 8 anni fa
  gdkchan 76ac31add6 Add BIT instruction 8 anni fa
  gdkchan 19b8344568 Add UABD instruction 8 anni fa