 LDj3SNuD
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00d4f44bbb
Add Sse Opt. for S/Uaddl_V, S/Uhadd_V, S/Uhsub_V, S/Umlal_V, S/Umlsl_V, S/Urhadd_V, S/Usubl_V Inst.; and for S/Urshr_V, S/Ursra_V Inst.. (#480)
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7 سال پیش |
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LDj3SNuD
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e674b37710
Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. (full FP emu.). Add 4 FP Tests. (#468)
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7 سال پیش |
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LDj3SNuD
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894459fcd7
Add Fmls_Se, Fmulx_Se/Ve, Smov_S Inst.; Opt. Clz/Clz_V, Cnt_V, Shl_V, S/Ushr_V, S/Usra_V Inst.; Add 11 Tests. Some fixes. (#449)
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7 سال پیش |
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LDj3SNuD
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bba9bf97d0
Add 9+7 fast/slow FP inst. impls.; add 14 FP Tests. (#437)
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7 سال پیش |
 gdkchan
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0b52ee6627
Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)
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7 سال پیش |
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gdkchan
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54ed9096bd
Add FMAXP and FMINP (Vector) instructions on the CPU (#412)
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7 سال پیش |
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LDj3SNuD
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c7387be0d2
Fix/Add 1+12 [Saturating] [Rounded] Shift Right Narrow (imm.) Instructions; add 14 Tests. Add 6 Tests for PR#405. Add 2 Tests for PR#412. (#409)
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7 سال پیش |
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LDj3SNuD
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a0c78f7920
Fix/Add 10 Shift Right and Mls_Ve Instructions; add 14 Tests. (#407)
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7 سال پیش |
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LDj3SNuD
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42e4e02a64
Add Fcvtns_S, Fcvtns_V, Fcvtnu_S, Fcvtnu_V (AOpCodeSimd) FP & Umlal_V, Umlsl_V, Saddl_V, Ssubl_V, Usubl_V instructions; add 8 FP & 16 S/Umlal_V, S/Umlsl_V, S/Uaddl_V, S/Usubl_V Tests. (#390)
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7 سال پیش |
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LDj3SNuD
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68300368d7
Add SHADD, SHSUB, UHSUB, SRHADD, URHADD, instructions; add 12 Tests. (#380)
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7 سال پیش |
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gdkchan
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55374ebba0
Zero out bits 63:32 of scalar float operations with SSE intrinsics (#273)
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7 سال پیش |
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LDj3SNuD
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4518c52c65
Add Sadalp_V, Saddlp_V, Uadalp_V, Uaddlp_V instructions; add 8 Tests. (#340)
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7 سال پیش |
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LDj3SNuD
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02a6fdcd13
Add Sqdmulh_S, Sqdmulh_V, Sqrdmulh_S, Sqrdmulh_V instructions; add 6 Tests. Now all saturating methods are on ASoftFallback. (#334)
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7 سال پیش |
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gdkchan
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221270db90
More accurate impl of FMINNM/FMAXNM, add vector variants (#296)
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7 سال پیش |
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LDj3SNuD
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5f34353dce
Add SQADD, UQADD, SQSUB, UQSUB, SUQADD, USQADD, SQABS, SQNEG (Scalar, Vector) instructions; add 24 Tests. Most saturation instructions now on ASoftFallback. (#314)
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7 سال پیش |
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LDj3SNuD
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fa5545aab8
Implement Ssubw_V and Usubw_V instructions. (#287)
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7 سال پیش |
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LDj3SNuD
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063fae50fe
Fix EmitHighNarrow(), EmitSaturatingNarrowOp() when Rd == Rn || Rd == Rm (& Part != 0). Optimization of EmitVectorTranspose(), EmitVectorUnzip(), EmitVectorZip() algorithms (reduction of the number of operations and their complexity). Add 12 Tests about Trn1/2, Uzp1/2, Zip1/2 (V) instructions. (#268)
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7 سال پیش |
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LDj3SNuD
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be31f5b46d
Improve CountLeadingZeros() algorithm, nits. (#219)
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7 سال پیش |
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gdkchan
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514218ab98
Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225)
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7 سال پیش |
 Merry
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0f8f40486d
ChocolArm64: More accurate implementation of Frecpe & Frecps (#228)
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7 سال پیش |
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gdkchan
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741773910d
Add SMAXP, SMINP, UMAX, UMAXP, UMIN and UMINP cpu instructions (#200)
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7 سال پیش |
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LDj3SNuD
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c228cf320d
Add Rbit_V instruction. Add 8 tests (Rbit_V; Rev16_V, Rev32_V, Rev64_V). Improve CountSetBits8() algorithm. (#212)
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7 سال پیش |
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LDj3SNuD
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53934e8872
Add Saba_V, Sabal_V, Sabd_V, Sabdl_V, Uaba_V, Uabal_V; Update Uabd_V, Uabdl_V. Add 16 tests. (#204)
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7 سال پیش |
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gdkchan
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bc26aa558a
Add support for the FMLA (by element/scalar) instruction (#187)
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7 سال پیش |
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LDj3SNuD
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c818093528
Add Sqxtun_S, Sqxtun_V with 3 tests. (#188)
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7 سال پیش |
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LDj3SNuD
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8f6387128a
Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
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7 سال پیش |
 Rygnus
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0bec9d8439
Add opcodes SQXTUN_S and SQXTUN_V (#184)
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7 سال پیش |
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gdkchan
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b747b23607
Add the FADDP (scalar) instruction
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7 سال پیش |
 Lordmau5
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46dc89f8dd
Implement Fabs_V (#146)
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7 سال پیش |
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gdkchan
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f9f111bc85
Add intrinsics support (#121)
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8 سال پیش |
