 merry
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df70442c46
InstEmitMemoryEx: Barrier after write on ordered store (#3193)
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%!s(int64=4) %!d(string=hai) anos |
 gdkchan
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f0824fde9f
Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015)
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%!s(int64=4) %!d(string=hai) anos |
 FICTURE7
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22b2cb39af
Reduce JIT GC allocations (#2515)
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%!s(int64=4) %!d(string=hai) anos |
 mageven
|
c19cfca183
Implement PRFM (register variant) as NOP (#1956)
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%!s(int64=5) %!d(string=hai) anos |
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gdkchan
|
9878fc2d3c
Implement inline memory load/store exclusive and ordered (#1413)
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%!s(int64=5) %!d(string=hai) anos |
 LDj3SNuD
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5e724cf24e
Add Profiled Persistent Translation Cache. (#769)
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%!s(int64=5) %!d(string=hai) anos |
 riperiperi
|
b1b6f294f2
Add most of the A32 instruction set to ARMeilleure (#897)
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%!s(int64=6) %!d(string=hai) anos |
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gdkchan
|
a731ab3a2a
Add a new JIT compiler for CPU code (#693)
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%!s(int64=6) %!d(string=hai) anos |
