 FICTURE7
|
f2a7b300c4
Fix type mismatch in `BitwiseAnd` simplification (#2571)
|
il y a 4 ans |
|
FICTURE7
|
22b2cb39af
Reduce JIT GC allocations (#2515)
|
il y a 4 ans |
|
FICTURE7
|
9d7627af64
Add multi-level function table (#2228)
|
il y a 5 ans |
 riperiperi
|
54ea2285f0
POWER - Performance Optimizations With Extensive Ramifications (#2286)
|
il y a 5 ans |
 gdkchan
|
fb65f392d1
Improve accuracy of reciprocal step instructions (#2305)
|
il y a 5 ans |
|
FICTURE7
|
65ac00833a
Use branch instead of tailcall for recursive calls (#2282)
|
il y a 5 ans |
|
FICTURE7
|
0181068016
Add `BIC/ORR Vd.T, #imm` fast path (#2279)
|
il y a 5 ans |
|
gdkchan
|
e318022b89
Fold constant offsets and group constant addresses (#2285)
|
il y a 5 ans |
 LDj3SNuD
|
57ea3f93a3
PPTC meets ExeFS Patching. (#1865)
|
il y a 5 ans |
|
FICTURE7
|
89791ba68d
Add inlined on translation call counting (#2190)
|
il y a 5 ans |
|
LDj3SNuD
|
90163087a0
PPTC vs. giant ExeFS. (#2168)
|
il y a 5 ans |
|
FICTURE7
|
98ed81e4cd
Improve `StoreToContext` emission (#2155)
|
il y a 5 ans |
 mageven
|
69f8722e79
Fix inconsistencies in progress reporting (#2129)
|
il y a 5 ans |
|
mageven
|
ca5d8e58dd
Add progress reporting to PTC and Shader Cache (#2057)
|
il y a 5 ans |
|
LDj3SNuD
|
bcbf240d2e
PPTC: Fix unwanted propagation of a relocatable constant in a specific case. (#1990)
|
il y a 5 ans |
|
mageven
|
9bda7b4699
Implement VCNT instruction (#1963)
|
il y a 5 ans |
|
LDj3SNuD
|
dc0adb533d
PPTC & Pool Enhancements. (#1968)
|
il y a 5 ans |
|
FICTURE7
|
1586880114
Turn Copy into Fill in HybridAllocator (#2010)
|
il y a 5 ans |
|
gdkchan
|
9d82d27df2
Fix memory tracking performance regression (#2026)
|
il y a 5 ans |
|
gdkchan
|
715b605e95
Validate CPU virtual addresses on access (#1987)
|
il y a 5 ans |
 sharmander
|
40797a1283
Optimization | Modify Add (Integer) Instruction to use LEA instead. (#1971)
|
il y a 5 ans |
|
gdkchan
|
dcce407071
Lower precision of estimate instruction results to match Arm behavior (#1943)
|
il y a 5 ans |
|
mageven
|
c19cfca183
Implement PRFM (register variant) as NOP (#1956)
|
il y a 5 ans |
|
FICTURE7
|
ddf1105bcb
Add VCLZ.* fast path (#1917)
|
il y a 5 ans |
|
LDj3SNuD
|
68f6b79fd3
Add a simple Pools Limiter. (#1830)
|
il y a 5 ans |
|
LDj3SNuD
|
430ba6da65
CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)
|
il y a 5 ans |
 Ac_K
|
5b9c876155
Hotfix for #1814
|
il y a 5 ans |
|
LDj3SNuD
|
2502f1f07f
Free up memory allocated by Pools during any PPTC translations at boot time. (#1814)
|
il y a 5 ans |
|
LDj3SNuD
|
8a33e884f8
Fix Vnmls_S fast path (F64: losing input d value). Fix Vnmla_S & Vnmls_S slow paths (using fused inst.s). Fix Vfma_V slow path not using StandardFPSCRValue(). (#1775)
|
il y a 5 ans |
|
LDj3SNuD
|
b5c215111d
PPTC Follow-up. (#1712)
|
il y a 5 ans |
