 LDj3SNuD
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4bd1ad16f9
Add Sqdmulh_Ve & Sqrdmulh_Ve Inst.s with Tests. (#2139)
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il y a 5 ans |
 gdkchan
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a731ab3a2a
Add a new JIT compiler for CPU code (#693)
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il y a 6 ans |
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LDj3SNuD
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10c74182ba
Implement the remaining tests for Simd and Fp instructions of data processing type. Small opts. for Fmov_Ftoi/1 & Fmov_Itof/1 Insts. (#709)
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il y a 6 ans |
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LDj3SNuD
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8f7fcede7f
Add Smlal_Ve, Smlsl_Ve, Smull_Ve, Umlal_Ve, Umlsl_Ve, Umull_Ve Inst.; add Tests. Add Sse Opt. for Trn1/2_V and Uzp1/2_V Inst. Nits. (#566)
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il y a 7 ans |
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LDj3SNuD
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1e7ea76f14
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
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il y a 7 ans |
 Alex Barney
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9cb57fb4bb
Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484)
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il y a 7 ans |
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LDj3SNuD
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894459fcd7
Add Fmls_Se, Fmulx_Se/Ve, Smov_S Inst.; Opt. Clz/Clz_V, Cnt_V, Shl_V, S/Ushr_V, S/Usra_V Inst.; Add 11 Tests. Some fixes. (#449)
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il y a 7 ans |
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LDj3SNuD
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a0c78f7920
Fix/Add 10 Shift Right and Mls_Ve Instructions; add 14 Tests. (#407)
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il y a 7 ans |
