 LDj3SNuD
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e674b37710
Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. (full FP emu.). Add 4 FP Tests. (#468)
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7 years ago |
 gdkchan
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0b52ee6627
Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)
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7 years ago |
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LDj3SNuD
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42e4e02a64
Add Fcvtns_S, Fcvtns_V, Fcvtnu_S, Fcvtnu_V (AOpCodeSimd) FP & Umlal_V, Umlsl_V, Saddl_V, Ssubl_V, Usubl_V instructions; add 8 FP & 16 S/Umlal_V, S/Umlsl_V, S/Uaddl_V, S/Usubl_V Tests. (#390)
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7 years ago |
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gdkchan
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514218ab98
Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225)
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7 years ago |
 Merry
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b233ae964f
AInstEmitSimdCvt: Half-precision to single-precision conversion (#235)
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7 years ago |
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gdkchan
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7ac5f40532
Add scalar variants of FCVTZS/FCVTZU, fix a issue on Ryushader
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8 years ago |
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gdkchan
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f9f111bc85
Add intrinsics support (#121)
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8 years ago |
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gdkchan
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59d1b2ad83
Add MUL (vector by element), fix FCVTN, make svcs use MakeError too
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8 years ago |
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gdkchan
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0e343a748d
Add FCVTL and FCVTN instruction (no Half support yet), stub SvcClearEvent
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8 years ago |
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gdkchan
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3936c93448
Map heap on heap base region, fix for thread start on homebrew, add FCVTMU and FCVTPU (general) instructions, fix FMOV (higher 64 bits) encodings, improve emit code for FCVT* (general) instructions
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8 years ago |
 emmauss
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62b827f474
Split main project into core,graphics and chocolarm4 subproject (#29)
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8 years ago |
