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@@ -161,6 +161,7 @@ namespace Ryujinx.Core.OsHle.Svc
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switch (InfoType)
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switch (InfoType)
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{
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{
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+ case 0: ThreadState.X1 = AllowedCpuIdBitmask(); break;
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case 2: ThreadState.X1 = GetMapRegionBaseAddr(); break;
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case 2: ThreadState.X1 = GetMapRegionBaseAddr(); break;
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case 3: ThreadState.X1 = GetMapRegionSize(); break;
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case 3: ThreadState.X1 = GetMapRegionSize(); break;
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case 4: ThreadState.X1 = GetHeapRegionBaseAddr(); break;
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case 4: ThreadState.X1 = GetHeapRegionBaseAddr(); break;
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@@ -179,6 +180,11 @@ namespace Ryujinx.Core.OsHle.Svc
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ThreadState.X0 = (int)SvcResult.Success;
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ThreadState.X0 = (int)SvcResult.Success;
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}
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}
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+
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+ private ulong AllowedCpuIdBitmask()
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+ {
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+ return 0xF; //Mephisto value.
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+ }
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private ulong GetMapRegionBaseAddr()
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private ulong GetMapRegionBaseAddr()
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{
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{
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@@ -230,4 +236,4 @@ namespace Ryujinx.Core.OsHle.Svc
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return AMemoryMgr.AddrSize - GetAddrSpaceBaseAddr();
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return AMemoryMgr.AddrSize - GetAddrSpaceBaseAddr();
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}
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}
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}
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}
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-}
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+}
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