CPU: Implement VRINTX.F32 | VRINTX.F64 (#1776)

* Start implementation

* Draft

* Updated opcode.

Needs verification.

* Clean up code.

* Update implementation and tests.

* Update implemenation + tests

* Get RM from FPSCR + Do not use emit/addintrinsic

* Remove "fast" path, as recommended by gdk.

* Variable DELETED.

* Update ARMeilleure/Decoders/OpCodeTable.cs

Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>

* Update ARMeilleure/Instructions/InstEmitSimdCvt32.cs

Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>

* Update ARMeilleure/Instructions/InstEmitSimdCvt32.cs

Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>

* Update ARMeilleure/Instructions/InstEmitSimdCvt32.cs

Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>

* Move method

* stringing things together :)

Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>

ARMeilleure/Decoders/OpCodeTable.cs

@@ -912,6 +912,7 @@ namespace ARMeilleure.Decoders
             SetA32("111100111x11xx00xxxx000<<xx0xxxx", InstName.Vrev,     InstEmit32.Vrev,     OpCode32SimdRev.Create);
             SetA32("111111101x1110xxxxxx101x01x0xxxx", InstName.Vrint,    InstEmit32.Vrint_RM, OpCode32SimdS.Create);
             SetA32("<<<<11101x110110xxxx101x11x0xxxx", InstName.Vrint,    InstEmit32.Vrint_Z,  OpCode32SimdS.Create);
+            SetA32("<<<<11101x110111xxxx101x01x0xxxx", InstName.Vrintx,   InstEmit32.Vrintx_S, OpCode32SimdS.Create);
             SetA32("1111001x1x>>>xxxxxxx0010>xx1xxxx", InstName.Vrshr,    InstEmit32.Vrshr,    OpCode32SimdShImm.Create);
             SetA32("111100111x111011xxxx010x1xx0xxxx", InstName.Vrsqrte,  InstEmit32.Vrsqrte,  OpCode32SimdSqrte.Create);
             SetA32("111100100x10xxxxxxxx1111xxx1xxxx", InstName.Vrsqrts,  InstEmit32.Vrsqrts,  OpCode32SimdReg.Create);

ARMeilleure/Instructions/InstEmitSimdCvt32.cs

@@ -342,6 +342,21 @@ namespace ARMeilleure.Instructions
             }
         }
 
+        // VRINTX (floating-point).
+        public static void Vrintx_S(ArmEmitterContext context)
+        {
+            OpCode32SimdS op = (OpCode32SimdS)context.CurrOp;
+
+            bool doubleSize = (op.Size & 1) == 1;
+            string methodName = doubleSize ? nameof(SoftFallback.Round) : nameof(SoftFallback.RoundF);
+
+            EmitScalarUnaryOpF32(context, (op1) =>
+            {
+                MethodInfo info = typeof(SoftFallback).GetMethod(methodName);
+                return context.Call(info, op1);
+            });
+        }
+
         private static Operand EmitFPConvert(ArmEmitterContext context, Operand value, OperandType type, bool signed)
         {
             Debug.Assert(value.Type == OperandType.I32 || value.Type == OperandType.I64);

ARMeilleure/Instructions/InstName.cs

@@ -608,6 +608,7 @@ namespace ARMeilleure.Instructions
         Vqshrn,
         Vrev,
         Vrint,
+        Vrintx,
         Vrshr,
         Vsel,
         Vshl,

Ryujinx.Tests/Cpu/CpuTestSimdCvt32.cs

@@ -2,6 +2,7 @@
 
 using ARMeilleure.State;
 using NUnit.Framework;
+using System;
 using System.Collections.Generic;
 
 namespace Ryujinx.Tests.Cpu
@@ -215,6 +216,42 @@ namespace Ryujinx.Tests.Cpu
 
             CompareAgainstUnicorn();
         }
+
+        [Test, Pairwise, Description("VRINTX.F<size> <Sd>, <Sm>")]
+        public void Vrintx_S([Values(0u, 1u)] uint rd,
+                             [Values(0u, 1u)] uint rm,
+                             [Values(2u, 3u)] uint size,
+                             [ValueSource(nameof(_1D_F_))] ulong s0,
+                             [ValueSource(nameof(_1D_F_))] ulong s1,
+                             [ValueSource(nameof(_1D_F_))] ulong s2,
+                             [Values(RMode.Rn, RMode.Rm, RMode.Rp)] RMode rMode)
+        {
+            uint opcode = 0xEB70A40;
+            V128 v0, v1, v2;
+            if (size == 2)
+            {
+                opcode |= ((rm & 0x1e) >> 1) | ((rm & 0x1) << 5);
+                opcode |= ((rd & 0x1e) >> 11) | ((rm & 0x1) << 22);
+                v0 = MakeVectorE0E1((uint)BitConverter.SingleToInt32Bits(s0), (uint)BitConverter.SingleToInt32Bits(s0));
+                v1 = MakeVectorE0E1((uint)BitConverter.SingleToInt32Bits(s1), (uint)BitConverter.SingleToInt32Bits(s0));
+                v2 = MakeVectorE0E1((uint)BitConverter.SingleToInt32Bits(s2), (uint)BitConverter.SingleToInt32Bits(s1));
+            }
+            else
+            {
+                opcode |= ((rm & 0xf) << 0) | ((rd & 0x10) << 1);
+                opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
+                v0 = MakeVectorE0E1((uint)BitConverter.DoubleToInt64Bits(s0), (uint)BitConverter.DoubleToInt64Bits(s0));
+                v1 = MakeVectorE0E1((uint)BitConverter.DoubleToInt64Bits(s1), (uint)BitConverter.DoubleToInt64Bits(s0));
+                v2 = MakeVectorE0E1((uint)BitConverter.DoubleToInt64Bits(s2), (uint)BitConverter.DoubleToInt64Bits(s1));
+            }
+
+            opcode |= ((size & 3) << 8);
+            
+            int fpscr = (int)rMode << (int)Fpcr.RMode;
+            SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, fpscr: fpscr);
+
+            CompareAgainstUnicorn();
+        }
 #endif
     }
 }