CPU: This PR fixes Fpscr, among other things. (#1433)

* CPU: This PR fixes Fpscr, among other things.

* Add Fpscr.Qc = 1 if sat. for Vqrshrn & Vqrshrun.

* Fix Vcmp & Vcmpe opcode table.

* Revert "Fix Vcmp & Vcmpe opcode table."

This reverts commit c117d9410d693185ff5f8ee8e457ffbfb2027dd5.

* Address PR feedbacks.

ARMeilleure/Instructions/InstEmitFlowHelper.cs

@@ -242,7 +242,7 @@ namespace ARMeilleure.Instructions
         private static void EmitNativeCallWithGuestAddress(ArmEmitterContext context, Operand funcAddr, Operand guestAddress, bool isJump)
         {
             Operand nativeContextPtr = context.LoadArgument(OperandType.I64, 0);
-            context.Store(context.Add(nativeContextPtr, Const(NativeContext.GetCallAddressOffset())), guestAddress);
+            context.Store(context.Add(nativeContextPtr, Const((long)NativeContext.GetCallAddressOffset())), guestAddress);
 
             EmitNativeCall(context, nativeContextPtr, funcAddr, isJump);
         }

ARMeilleure/Instructions/InstEmitSimdCmp.cs

@@ -538,9 +538,12 @@ namespace ARMeilleure.Instructions
 
                     context.BranchIfFalse(lblNaN, isOrdered);
 
-                    Operand cf = context.AddIntrinsicInt(Intrinsic.X86Comissge, n, m);
-                    Operand zf = context.AddIntrinsicInt(Intrinsic.X86Comisseq, n, m);
-                    Operand nf = context.AddIntrinsicInt(Intrinsic.X86Comisslt, n, m);
+                    Operand nCopy = context.Copy(n);
+                    Operand mCopy = cmpWithZero ? context.VectorZero() : context.Copy(m);
+
+                    Operand cf = context.AddIntrinsicInt(Intrinsic.X86Comissge, nCopy, mCopy);
+                    Operand zf = context.AddIntrinsicInt(Intrinsic.X86Comisseq, nCopy, mCopy);
+                    Operand nf = context.AddIntrinsicInt(Intrinsic.X86Comisslt, nCopy, mCopy);
 
                     SetFlag(context, PState.VFlag, Const(0));
                     SetFlag(context, PState.CFlag, cf);
@@ -555,9 +558,12 @@ namespace ARMeilleure.Instructions
 
                     context.BranchIfFalse(lblNaN, isOrdered);
 
-                    Operand cf = context.AddIntrinsicInt(Intrinsic.X86Comisdge, n, m);
-                    Operand zf = context.AddIntrinsicInt(Intrinsic.X86Comisdeq, n, m);
-                    Operand nf = context.AddIntrinsicInt(Intrinsic.X86Comisdlt, n, m);
+                    Operand nCopy = context.Copy(n);
+                    Operand mCopy = cmpWithZero ? context.VectorZero() : context.Copy(m);
+
+                    Operand cf = context.AddIntrinsicInt(Intrinsic.X86Comisdge, nCopy, mCopy);
+                    Operand zf = context.AddIntrinsicInt(Intrinsic.X86Comisdeq, nCopy, mCopy);
+                    Operand nf = context.AddIntrinsicInt(Intrinsic.X86Comisdlt, nCopy, mCopy);
 
                     SetFlag(context, PState.VFlag, Const(0));
                     SetFlag(context, PState.CFlag, cf);

ARMeilleure/Instructions/InstEmitSimdCmp32.cs

@@ -307,7 +307,10 @@ namespace ARMeilleure.Instructions
                     Operand zf = context.AddIntrinsicInt(Intrinsic.X86Comisseq, n, m);
                     Operand nf = context.AddIntrinsicInt(Intrinsic.X86Comisslt, n, m);
 
-                    EmitSetFPSCRFlags(context, nf, zf, cf, Const(0));
+                    SetFpFlag(context, FPState.VFlag, Const(0));
+                    SetFpFlag(context, FPState.CFlag, cf);
+                    SetFpFlag(context, FPState.ZFlag, zf);
+                    SetFpFlag(context, FPState.NFlag, nf);
                 }
                 else
                 {
@@ -321,14 +324,20 @@ namespace ARMeilleure.Instructions
                     Operand zf = context.AddIntrinsicInt(Intrinsic.X86Comisdeq, n, m);
                     Operand nf = context.AddIntrinsicInt(Intrinsic.X86Comisdlt, n, m);
 
-                    EmitSetFPSCRFlags(context, nf, zf, cf, Const(0));
+                    SetFpFlag(context, FPState.VFlag, Const(0));
+                    SetFpFlag(context, FPState.CFlag, cf);
+                    SetFpFlag(context, FPState.ZFlag, zf);
+                    SetFpFlag(context, FPState.NFlag, nf);
                 }
 
                 context.Branch(lblEnd);
 
                 context.MarkLabel(lblNaN);
 
-                EmitSetFPSCRFlags(context, Const(3));
+                SetFpFlag(context, FPState.VFlag, Const(1));
+                SetFpFlag(context, FPState.CFlag, Const(1));
+                SetFpFlag(context, FPState.ZFlag, Const(0));
+                SetFpFlag(context, FPState.NFlag, Const(0));
 
                 context.MarkLabel(lblEnd);
             }
@@ -354,11 +363,11 @@ namespace ARMeilleure.Instructions
 
                 Operand nzcv = context.Call(info, ne, me, Const(signalNaNs));
 
-                EmitSetFPSCRFlags(context, nzcv);
+                EmitSetFpscrNzcv(context, nzcv);
             }
         }
 
-        private static void EmitSetFPSCRFlags(ArmEmitterContext context, Operand nzcv)
+        private static void EmitSetFpscrNzcv(ArmEmitterContext context, Operand nzcv)
         {
             Operand Extract(Operand value, int bit)
             {
@@ -378,14 +387,6 @@ namespace ARMeilleure.Instructions
             SetFpFlag(context, FPState.NFlag, Extract(nzcv, 3));
         }
 
-        private static void EmitSetFPSCRFlags(ArmEmitterContext context, Operand n, Operand z, Operand c, Operand v)
-        {
-            SetFpFlag(context, FPState.VFlag, v);
-            SetFpFlag(context, FPState.CFlag, c);
-            SetFpFlag(context, FPState.ZFlag, z);
-            SetFpFlag(context, FPState.NFlag, n);
-        }
-
         private static void EmitSse2OrAvxCmpOpF32(ArmEmitterContext context, CmpCondition cond, bool zero)
         {
             OpCode32Simd op = (OpCode32Simd)context.CurrOp;

ARMeilleure/Instructions/InstEmitSimdShift32.cs

@@ -289,7 +289,7 @@ namespace ARMeilleure.Instructions
 
             context.BranchIfFalse(lblNoSat, context.BitwiseOr(gt, lt));
 
-            // TODO: Set QC (to 1) on FPSCR here.
+            context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc)));
 
             context.MarkLabel(lblNoSat);
 

ARMeilleure/Instructions/InstEmitSystem32.cs

@@ -186,14 +186,12 @@ namespace ARMeilleure.Instructions
                 return;
             }
 
-            MethodInfo info;
-
             switch (op.Sreg)
             {
                 case 0b0000: // FPSID
                     throw new NotImplementedException("Supervisor Only");
                 case 0b0001: // FPSCR
-                    info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetFpscr)); break;
+                    EmitGetFpscr(context); return;
                 case 0b0101: // MVFR2
                     throw new NotImplementedException("MVFR2");
                 case 0b0110: // MVFR1
@@ -205,22 +203,18 @@ namespace ARMeilleure.Instructions
                 default:
                     throw new NotImplementedException($"Unknown VMRS 0x{op.RawOpCode:X8} at 0x{op.Address:X16}.");
             }
-
-            SetIntA32(context, op.Rt, context.Call(info));
         }
 
         public static void Vmsr(ArmEmitterContext context)
         {
             OpCode32SimdSpecial op = (OpCode32SimdSpecial)context.CurrOp;
 
-            MethodInfo info;
-
             switch (op.Sreg)
             {
                 case 0b0000: // FPSID
                     throw new NotImplementedException("Supervisor Only");
                 case 0b0001: // FPSCR
-                    info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpscr)); break;
+                    EmitSetFpscr(context); return;
                 case 0b0101: // MVFR2
                     throw new NotImplementedException("MVFR2");
                 case 0b0110: // MVFR1
@@ -232,8 +226,6 @@ namespace ARMeilleure.Instructions
                 default:
                     throw new NotImplementedException($"Unknown VMSR 0x{op.RawOpCode:X8} at 0x{op.Address:X16}.");
             }
-
-            context.Call(info, GetIntA32(context, op.Rt));
         }
 
         private static void EmitSetNzcv(ArmEmitterContext context, Operand t)
@@ -255,5 +247,47 @@ namespace ARMeilleure.Instructions
             SetFlag(context, PState.ZFlag, z);
             SetFlag(context, PState.NFlag, n);
         }
+
+        private static void EmitGetFpscr(ArmEmitterContext context)
+        {
+            OpCode32SimdSpecial op = (OpCode32SimdSpecial)context.CurrOp;
+
+            Operand vSh = context.ShiftLeft(GetFpFlag(FPState.VFlag), Const((int)FPState.VFlag));
+            Operand cSh = context.ShiftLeft(GetFpFlag(FPState.CFlag), Const((int)FPState.CFlag));
+            Operand zSh = context.ShiftLeft(GetFpFlag(FPState.ZFlag), Const((int)FPState.ZFlag));
+            Operand nSh = context.ShiftLeft(GetFpFlag(FPState.NFlag), Const((int)FPState.NFlag));
+
+            Operand nzcvSh = context.BitwiseOr(context.BitwiseOr(nSh, zSh), context.BitwiseOr(cSh, vSh));
+
+            Operand fpscr = context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetFpscr)));
+
+            SetIntA32(context, op.Rt, context.BitwiseOr(nzcvSh, fpscr));
+        }
+
+        private static void EmitSetFpscr(ArmEmitterContext context)
+        {
+            OpCode32SimdSpecial op = (OpCode32SimdSpecial)context.CurrOp;
+
+            Operand t = GetIntA32(context, op.Rt);
+
+            Operand v = context.ShiftRightUI(t, Const((int)FPState.VFlag));
+            v = context.BitwiseAnd(v, Const(1));
+
+            Operand c = context.ShiftRightUI(t, Const((int)FPState.CFlag));
+            c = context.BitwiseAnd(c, Const(1));
+
+            Operand z = context.ShiftRightUI(t, Const((int)FPState.ZFlag));
+            z = context.BitwiseAnd(z, Const(1));
+
+            Operand n = context.ShiftRightUI(t, Const((int)FPState.NFlag));
+            n = context.BitwiseAnd(n, Const(1));
+
+            SetFpFlag(context, FPState.VFlag, v);
+            SetFpFlag(context, FPState.CFlag, c);
+            SetFpFlag(context, FPState.ZFlag, z);
+            SetFpFlag(context, FPState.NFlag, n);
+
+            context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpscr)), t);
+        }
     }
 }

ARMeilleure/Instructions/NativeInterface.cs

@@ -87,14 +87,8 @@ namespace ARMeilleure.Instructions
         {
             var context = GetContext();
 
-            uint result = (uint)(context.Fpsr & FPSR.A32Mask) | (uint)(context.Fpcr & FPCR.A32Mask);
-
-            result |= context.GetFPstateFlag(FPState.NFlag) ? (1u << 31) : 0;
-            result |= context.GetFPstateFlag(FPState.ZFlag) ? (1u << 30) : 0;
-            result |= context.GetFPstateFlag(FPState.CFlag) ? (1u << 29) : 0;
-            result |= context.GetFPstateFlag(FPState.VFlag) ? (1u << 28) : 0;
-
-            return result;
+            return (uint)(context.Fpsr & FPSR.A32Mask & ~FPSR.Nzcv) |
+                   (uint)(context.Fpcr & FPCR.A32Mask);
         }
 
         public static ulong GetTpidrEl0()
@@ -142,17 +136,17 @@ namespace ARMeilleure.Instructions
             GetContext().Fpsr = (FPSR)value;
         }
 
-        public static void SetFpscr(uint value)
+        public static void SetFpsrQc()
         {
-            var context = GetContext();
+            GetContext().Fpsr |= FPSR.Qc;
+        }
 
-            context.SetFPstateFlag(FPState.NFlag, (value & (1u << 31)) != 0);
-            context.SetFPstateFlag(FPState.ZFlag, (value & (1u << 30)) != 0);
-            context.SetFPstateFlag(FPState.CFlag, (value & (1u << 29)) != 0);
-            context.SetFPstateFlag(FPState.VFlag, (value & (1u << 28)) != 0);
+        public static void SetFpscr(uint fpscr)
+        {
+            var context = GetContext();
 
-            context.Fpsr = FPSR.A32Mask & (FPSR)value;
-            context.Fpcr = FPCR.A32Mask & (FPCR)value;
+            context.Fpsr = FPSR.A32Mask & (FPSR)fpscr;
+            context.Fpcr = FPCR.A32Mask & (FPCR)fpscr;
         }
 
         public static void SetTpidrEl0(ulong value)

ARMeilleure/State/FPCR.cs

@@ -5,12 +5,12 @@ namespace ARMeilleure.State
     [Flags]
     public enum FPCR : uint
     {
-        Ufe = 1 << 11,
-        Fz  = 1 << 24,
-        Dn  = 1 << 25,
-        Ahp = 1 << 26,
+        Ufe = 1u << 11,
+        Fz  = 1u << 24,
+        Dn  = 1u << 25,
+        Ahp = 1u << 26,
 
-        A32Mask = 0x07ffff00
+        A32Mask = 0x07FF9F00u
     }
 
     public static class FPCRExtensions

ARMeilleure/State/FPSR.cs

@@ -5,9 +5,11 @@ namespace ARMeilleure.State
     [Flags]
     public enum FPSR : uint
     {
-        Ufc = 1 << 3,
-        Qc  = 1 << 27,
+        Ufc = 1u << 3,
+        Qc  = 1u << 27,
 
-        A32Mask = 0xf800000f
+        Nzcv = (1u << 31) | (1u << 30) | (1u << 29) | (1u << 28),
+
+        A32Mask = 0xF800009Fu
     }
 }

ARMeilleure/State/FPState.cs

@@ -1,10 +1,5 @@
-using System;
-using System.Collections.Generic;
-using System.Text;
-
-namespace ARMeilleure.State
+namespace ARMeilleure.State
 {
-    [Flags]
     public enum FPState
     {
         VFlag = 28,

ARMeilleure/State/PState.cs

@@ -1,8 +1,5 @@
-using System;
-
 namespace ARMeilleure.State
 {
-    [Flags]
     public enum PState
     {
         TFlag = 5,

ARMeilleure/Translation/Delegates.cs

@@ -126,6 +126,7 @@ namespace ARMeilleure.Translation
             SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpcr)));
             SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpscr))); // A32 only.
             SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsr)));
+            SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc))); // A32 only.
             SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetTpidrEl0)));
             SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetTpidrEl032))); // A32 only.
             SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SupervisorCall)));

Ryujinx.HLE/HOS/Kernel/SupervisorCall/Syscall.cs

@@ -9,7 +9,6 @@ using Ryujinx.HLE.HOS.Kernel.Memory;
 using Ryujinx.HLE.HOS.Kernel.Process;
 using Ryujinx.HLE.HOS.Kernel.Threading;
 using System;
-using System.Collections.Generic;
 using System.Threading;
 
 namespace Ryujinx.HLE.HOS.Kernel.SupervisorCall
@@ -2131,10 +2130,10 @@ namespace Ryujinx.HLE.HOS.Kernel.SupervisorCall
 
         private static int GetPsr(ARMeilleure.State.ExecutionContext context)
         {
-            return (context.GetPstateFlag(ARMeilleure.State.PState.NFlag) ? (1 << 31) : 0) |
-                   (context.GetPstateFlag(ARMeilleure.State.PState.ZFlag) ? (1 << 30) : 0) |
-                   (context.GetPstateFlag(ARMeilleure.State.PState.CFlag) ? (1 << 29) : 0) |
-                   (context.GetPstateFlag(ARMeilleure.State.PState.VFlag) ? (1 << 28) : 0);
+            return (context.GetPstateFlag(ARMeilleure.State.PState.NFlag) ? (1 << (int)ARMeilleure.State.PState.NFlag) : 0) |
+                   (context.GetPstateFlag(ARMeilleure.State.PState.ZFlag) ? (1 << (int)ARMeilleure.State.PState.ZFlag) : 0) |
+                   (context.GetPstateFlag(ARMeilleure.State.PState.CFlag) ? (1 << (int)ARMeilleure.State.PState.CFlag) : 0) |
+                   (context.GetPstateFlag(ARMeilleure.State.PState.VFlag) ? (1 << (int)ARMeilleure.State.PState.VFlag) : 0);
         }
 
         // Thread synchronization

Ryujinx.Tests/Cpu/CpuTest.cs

@@ -121,11 +121,10 @@ namespace Ryujinx.Tests.Cpu
                                   int   fpcr     = 0,
                                   int   fpsr     = 0)
         {
-            _context.SetX(0, x0);
-            _context.SetX(1, x1);
-            _context.SetX(2, x2);
-            _context.SetX(3, x3);
-
+            _context.SetX(0,  x0);
+            _context.SetX(1,  x1);
+            _context.SetX(2,  x2);
+            _context.SetX(3,  x3);
             _context.SetX(31, x31);
 
             _context.SetV(0,  v0);
@@ -151,8 +150,7 @@ namespace Ryujinx.Tests.Cpu
                 _unicornEmu.X[1] = x1;
                 _unicornEmu.X[2] = x2;
                 _unicornEmu.X[3] = x3;
-
-                _unicornEmu.SP = x31;
+                _unicornEmu.SP   = x31;
 
                 _unicornEmu.Q[0]  = V128ToSimdValue(v0);
                 _unicornEmu.Q[1]  = V128ToSimdValue(v1);
@@ -207,7 +205,7 @@ namespace Ryujinx.Tests.Cpu
         {
             if (Ignore_FpcrFz_FpcrDn)
             {
-                fpcr &= ~((int)FPCR.Fz | (int)FPCR.Dn);
+                fpcr &= ~((1 << (int)Fpcr.Fz) | (1 << (int)Fpcr.Dn));
             }
 
             Opcode(opcode);
@@ -360,7 +358,6 @@ namespace Ryujinx.Tests.Cpu
             Assert.That(_context.GetX(28), Is.EqualTo(_unicornEmu.X[28]));
             Assert.That(_context.GetX(29), Is.EqualTo(_unicornEmu.X[29]));
             Assert.That(_context.GetX(30), Is.EqualTo(_unicornEmu.X[30]));
-
             Assert.That(_context.GetX(31), Is.EqualTo(_unicornEmu.SP), "X31");
 
             if (fpTolerances == FpTolerances.None)
@@ -403,9 +400,6 @@ namespace Ryujinx.Tests.Cpu
             Assert.That(V128ToSimdValue(_context.GetV(30)), Is.EqualTo(_unicornEmu.Q[30]), "V30");
             Assert.That(V128ToSimdValue(_context.GetV(31)), Is.EqualTo(_unicornEmu.Q[31]), "V31");
 
-            Assert.That((int)_context.Fpcr,                 Is.EqualTo(_unicornEmu.Fpcr),                 "Fpcr");
-            Assert.That((int)_context.Fpsr & (int)fpsrMask, Is.EqualTo(_unicornEmu.Fpsr & (int)fpsrMask), "Fpsr");
-
             Assert.Multiple(() =>
             {
                 Assert.That(_context.GetPstateFlag(PState.VFlag), Is.EqualTo(_unicornEmu.OverflowFlag), "VFlag");
@@ -414,6 +408,9 @@ namespace Ryujinx.Tests.Cpu
                 Assert.That(_context.GetPstateFlag(PState.NFlag), Is.EqualTo(_unicornEmu.NegativeFlag), "NFlag");
             });
 
+            Assert.That((int)_context.Fpcr,                 Is.EqualTo(_unicornEmu.Fpcr),                 "Fpcr");
+            Assert.That((int)_context.Fpsr & (int)fpsrMask, Is.EqualTo(_unicornEmu.Fpsr & (int)fpsrMask), "Fpsr");
+
             if (_usingMemory)
             {
                 byte[] mem = _memory.GetSpan(DataBaseAddress, (int)Size).ToArray();

Ryujinx.Tests/Cpu/CpuTest32.cs

@@ -12,10 +12,11 @@ namespace Ryujinx.Tests.Cpu
     [TestFixture]
     public class CpuTest32
     {
-        private uint _currAddress;
-        private ulong _size;
+        protected const uint Size = 0x1000;
+        protected const uint CodeBaseAddress = 0x1000;
+        protected const uint DataBaseAddress = CodeBaseAddress + Size;
 
-        private uint _entryPoint;
+        private uint _currAddress;
 
         private MemoryBlock _ram;
 
@@ -28,7 +29,7 @@ namespace Ryujinx.Tests.Cpu
         private static bool _unicornAvailable;
         private UnicornAArch32 _unicornEmu;
 
-        private bool usingMemory;
+        private bool _usingMemory;
 
         static CpuTest32()
         {
@@ -43,14 +44,11 @@ namespace Ryujinx.Tests.Cpu
         [SetUp]
         public void Setup()
         {
-            _currAddress = 0x1000;
-            _size        = 0x1000;
+            _currAddress = CodeBaseAddress;
 
-            _entryPoint = _currAddress;
-
-            _ram = new MemoryBlock(_size * 2);
-            _memory = new MemoryManager(_ram, 1UL << 16);
-            _memory.Map(_currAddress, 0, _size * 2);
+            _ram = new MemoryBlock(Size * 2);
+            _memory = new MemoryManager(_ram, 1ul << 16);
+            _memory.Map(CodeBaseAddress, 0, Size * 2);
 
             _context = CpuContext.CreateExecutionContext();
             _context.IsAarch32 = true;
@@ -60,9 +58,9 @@ namespace Ryujinx.Tests.Cpu
             if (_unicornAvailable)
             {
                 _unicornEmu = new UnicornAArch32();
-                _unicornEmu.MemoryMap(_currAddress, _size, MemoryPermission.READ | MemoryPermission.EXEC);
-                _unicornEmu.MemoryMap(_currAddress + _size, _size, MemoryPermission.READ | MemoryPermission.WRITE);
-                _unicornEmu.PC = _entryPoint;
+                _unicornEmu.MemoryMap(CodeBaseAddress, Size, MemoryPermission.READ | MemoryPermission.EXEC);
+                _unicornEmu.MemoryMap(DataBaseAddress, Size, MemoryPermission.READ | MemoryPermission.WRITE);
+                _unicornEmu.PC = CodeBaseAddress;
             }
         }
 
@@ -77,6 +75,8 @@ namespace Ryujinx.Tests.Cpu
             _context    = null;
             _cpuContext = null;
             _unicornEmu = null;
+
+            _usingMemory = false;
         }
 
         protected void Reset()
@@ -98,6 +98,7 @@ namespace Ryujinx.Tests.Cpu
         }
 
         protected ExecutionContext GetContext() => _context;
+
         protected void SetContext(uint r0 = 0,
                                   uint r1 = 0,
                                   uint r2 = 0,
@@ -111,6 +112,7 @@ namespace Ryujinx.Tests.Cpu
                                   V128 v5 = default,
                                   V128 v14 = default,
                                   V128 v15 = default,
+                                  bool saturation = false,
                                   bool overflow = false,
                                   bool carry = false,
                                   bool zero = false,
@@ -121,8 +123,7 @@ namespace Ryujinx.Tests.Cpu
             _context.SetX(1, r1);
             _context.SetX(2, r2);
             _context.SetX(3, r3);
-
-            _context.SetX(0xd, sp);
+            _context.SetX(13, sp);
 
             _context.SetV(0, v0);
             _context.SetV(1, v1);
@@ -133,13 +134,13 @@ namespace Ryujinx.Tests.Cpu
             _context.SetV(14, v14);
             _context.SetV(15, v15);
 
+            _context.SetPstateFlag(PState.QFlag, saturation);
             _context.SetPstateFlag(PState.VFlag, overflow);
             _context.SetPstateFlag(PState.CFlag, carry);
             _context.SetPstateFlag(PState.ZFlag, zero);
             _context.SetPstateFlag(PState.NFlag, negative);
 
-            _context.Fpsr = FPSR.A32Mask & (FPSR)fpscr;
-            _context.Fpcr = FPCR.A32Mask & (FPCR)fpscr;
+            SetFpscr((uint)fpscr);
 
             if (_unicornAvailable)
             {
@@ -147,7 +148,6 @@ namespace Ryujinx.Tests.Cpu
                 _unicornEmu.R[1] = r1;
                 _unicornEmu.R[2] = r2;
                 _unicornEmu.R[3] = r3;
-
                 _unicornEmu.SP = sp;
 
                 _unicornEmu.Q[0] = V128ToSimdValue(v0);
@@ -159,6 +159,7 @@ namespace Ryujinx.Tests.Cpu
                 _unicornEmu.Q[14] = V128ToSimdValue(v14);
                 _unicornEmu.Q[15] = V128ToSimdValue(v15);
 
+                _unicornEmu.QFlag = saturation;
                 _unicornEmu.OverflowFlag = overflow;
                 _unicornEmu.CarryFlag = carry;
                 _unicornEmu.ZeroFlag = zero;
@@ -170,11 +171,11 @@ namespace Ryujinx.Tests.Cpu
 
         protected void ExecuteOpcodes(bool runUnicorn = true)
         {
-            _cpuContext.Execute(_context, _entryPoint);
+            _cpuContext.Execute(_context, CodeBaseAddress);
 
             if (_unicornAvailable && runUnicorn)
             {
-                _unicornEmu.RunForCount((ulong)(_currAddress - _entryPoint - 4) / 4);
+                _unicornEmu.RunForCount((_currAddress - CodeBaseAddress - 4) / 4);
             }
         }
 
@@ -192,36 +193,32 @@ namespace Ryujinx.Tests.Cpu
                                                 V128 v5 = default,
                                                 V128 v14 = default,
                                                 V128 v15 = default,
+                                                bool saturation = false,
                                                 bool overflow = false,
                                                 bool carry = false,
                                                 bool zero = false,
                                                 bool negative = false,
                                                 int fpscr = 0,
-                                                bool copyFpFlags = false,
                                                 bool runUnicorn = true)
         {
             Opcode(opcode);
-            if (copyFpFlags)
-            {
-                Opcode(0xeef1fa10);
-            }
-            Opcode(0xe12fff1e); // BX LR
-            SetContext(r0, r1, r2, r3, sp, v0, v1, v2, v3, v4, v5, v14, v15, overflow, carry, zero, negative, fpscr);
+            Opcode(0xE12FFF1E); // BX LR
+            SetContext(r0, r1, r2, r3, sp, v0, v1, v2, v3, v4, v5, v14, v15, saturation, overflow, carry, zero, negative, fpscr);
             ExecuteOpcodes(runUnicorn);
 
             return GetContext();
         }
 
-        protected void SetWorkingMemory(byte[] data)
+        protected void SetWorkingMemory(uint offset, byte[] data)
         {
-            _memory.Write(0x2000, data);
+            _memory.Write(DataBaseAddress + offset, data);
 
             if (_unicornAvailable)
             {
-                _unicornEmu.MemoryWrite((ulong)(0x2000), data);
+                _unicornEmu.MemoryWrite(DataBaseAddress + offset, data);
             }
 
-            usingMemory = true; // When true, CompareAgainstUnicorn checks the working memory for equality too.
+            _usingMemory = true; // When true, CompareAgainstUnicorn checks the working memory for equality too.
         }
 
         /// <summary>Rounding Mode control field.</summary>
@@ -272,8 +269,8 @@ namespace Ryujinx.Tests.Cpu
             /// <summary>Cumulative saturation bit.</summary>
             Qc = 1 << 27,
 
-            /// <summary>NZCV flags</summary>
-            Nzcv = (1 << 28) | (1 << 29) | (1 << 30) | (1 << 31)
+            /// <summary>NZCV flags.</summary>
+            Nzcv = (1 << 31) | (1 << 30) | (1 << 29) | (1 << 28)
         }
 
         [Flags]
@@ -311,10 +308,10 @@ namespace Ryujinx.Tests.Cpu
                 ManageFpSkips(fpSkips);
             }
 
-            Assert.That(_context.GetX(0), Is.EqualTo(_unicornEmu.R[0]));
-            Assert.That(_context.GetX(1), Is.EqualTo(_unicornEmu.R[1]));
-            Assert.That(_context.GetX(2), Is.EqualTo(_unicornEmu.R[2]));
-            Assert.That(_context.GetX(3), Is.EqualTo(_unicornEmu.R[3]));
+            Assert.That(_context.GetX(0), Is.EqualTo(_unicornEmu.R[0]), "R0");
+            Assert.That(_context.GetX(1), Is.EqualTo(_unicornEmu.R[1]), "R1");
+            Assert.That(_context.GetX(2), Is.EqualTo(_unicornEmu.R[2]), "R2");
+            Assert.That(_context.GetX(3), Is.EqualTo(_unicornEmu.R[3]), "R3");
             Assert.That(_context.GetX(4), Is.EqualTo(_unicornEmu.R[4]));
             Assert.That(_context.GetX(5), Is.EqualTo(_unicornEmu.R[5]));
             Assert.That(_context.GetX(6), Is.EqualTo(_unicornEmu.R[6]));
@@ -324,22 +321,22 @@ namespace Ryujinx.Tests.Cpu
             Assert.That(_context.GetX(10), Is.EqualTo(_unicornEmu.R[10]));
             Assert.That(_context.GetX(11), Is.EqualTo(_unicornEmu.R[11]));
             Assert.That(_context.GetX(12), Is.EqualTo(_unicornEmu.R[12]));
-            Assert.That(_context.GetX(13), Is.EqualTo(_unicornEmu.R[13]));
+            Assert.That(_context.GetX(13), Is.EqualTo(_unicornEmu.SP), "SP");
             Assert.That(_context.GetX(14), Is.EqualTo(_unicornEmu.R[14]));
 
             if (fpTolerances == FpTolerances.None)
             {
-                Assert.That(V128ToSimdValue(_context.GetV(0)), Is.EqualTo(_unicornEmu.Q[0]));
+                Assert.That(V128ToSimdValue(_context.GetV(0)), Is.EqualTo(_unicornEmu.Q[0]), "V0");
             }
             else
             {
                 ManageFpTolerances(fpTolerances);
             }
-            Assert.That(V128ToSimdValue(_context.GetV(1)), Is.EqualTo(_unicornEmu.Q[1]));
-            Assert.That(V128ToSimdValue(_context.GetV(2)), Is.EqualTo(_unicornEmu.Q[2]));
-            Assert.That(V128ToSimdValue(_context.GetV(3)), Is.EqualTo(_unicornEmu.Q[3]));
-            Assert.That(V128ToSimdValue(_context.GetV(4)), Is.EqualTo(_unicornEmu.Q[4]));
-            Assert.That(V128ToSimdValue(_context.GetV(5)), Is.EqualTo(_unicornEmu.Q[5]));
+            Assert.That(V128ToSimdValue(_context.GetV(1)), Is.EqualTo(_unicornEmu.Q[1]), "V1");
+            Assert.That(V128ToSimdValue(_context.GetV(2)), Is.EqualTo(_unicornEmu.Q[2]), "V2");
+            Assert.That(V128ToSimdValue(_context.GetV(3)), Is.EqualTo(_unicornEmu.Q[3]), "V3");
+            Assert.That(V128ToSimdValue(_context.GetV(4)), Is.EqualTo(_unicornEmu.Q[4]), "V4");
+            Assert.That(V128ToSimdValue(_context.GetV(5)), Is.EqualTo(_unicornEmu.Q[5]), "V5");
             Assert.That(V128ToSimdValue(_context.GetV(6)), Is.EqualTo(_unicornEmu.Q[6]));
             Assert.That(V128ToSimdValue(_context.GetV(7)), Is.EqualTo(_unicornEmu.Q[7]));
             Assert.That(V128ToSimdValue(_context.GetV(8)), Is.EqualTo(_unicornEmu.Q[8]));
@@ -348,26 +345,26 @@ namespace Ryujinx.Tests.Cpu
             Assert.That(V128ToSimdValue(_context.GetV(11)), Is.EqualTo(_unicornEmu.Q[11]));
             Assert.That(V128ToSimdValue(_context.GetV(12)), Is.EqualTo(_unicornEmu.Q[12]));
             Assert.That(V128ToSimdValue(_context.GetV(13)), Is.EqualTo(_unicornEmu.Q[13]));
-            Assert.That(V128ToSimdValue(_context.GetV(14)), Is.EqualTo(_unicornEmu.Q[14]));
-            Assert.That(V128ToSimdValue(_context.GetV(15)), Is.EqualTo(_unicornEmu.Q[15]));
+            Assert.That(V128ToSimdValue(_context.GetV(14)), Is.EqualTo(_unicornEmu.Q[14]), "V14");
+            Assert.That(V128ToSimdValue(_context.GetV(15)), Is.EqualTo(_unicornEmu.Q[15]), "V15");
 
-            Assert.That((int)_context.Fpcr | ((int)_context.Fpsr & (int)fpsrMask), Is.EqualTo(_unicornEmu.Fpscr));
+            Assert.Multiple(() =>
+            {
+                Assert.That(_context.GetPstateFlag(PState.QFlag), Is.EqualTo(_unicornEmu.QFlag), "QFlag");
+                Assert.That(_context.GetPstateFlag(PState.VFlag), Is.EqualTo(_unicornEmu.OverflowFlag), "VFlag");
+                Assert.That(_context.GetPstateFlag(PState.CFlag), Is.EqualTo(_unicornEmu.CarryFlag), "CFlag");
+                Assert.That(_context.GetPstateFlag(PState.ZFlag), Is.EqualTo(_unicornEmu.ZeroFlag), "ZFlag");
+                Assert.That(_context.GetPstateFlag(PState.NFlag), Is.EqualTo(_unicornEmu.NegativeFlag), "NFlag");
+            });
 
-            Assert.That(_context.GetPstateFlag(PState.QFlag), Is.EqualTo(_unicornEmu.QFlag));
-            Assert.That(_context.GetPstateFlag(PState.VFlag), Is.EqualTo(_unicornEmu.OverflowFlag));
-            Assert.That(_context.GetPstateFlag(PState.CFlag), Is.EqualTo(_unicornEmu.CarryFlag));
-            Assert.That(_context.GetPstateFlag(PState.ZFlag), Is.EqualTo(_unicornEmu.ZeroFlag));
-            Assert.That(_context.GetPstateFlag(PState.NFlag), Is.EqualTo(_unicornEmu.NegativeFlag));
+            Assert.That((int)GetFpscr() & (int)fpsrMask, Is.EqualTo(_unicornEmu.Fpscr & (int)fpsrMask), "Fpscr");
 
-            if (usingMemory)
+            if (_usingMemory)
             {
-                ReadOnlySpan<byte> meilleureMem = _memory.GetSpan(0x2000, (int)_size);
-                byte[] unicornMem = _unicornEmu.MemoryRead(0x2000, _size);
+                byte[] mem = _memory.GetSpan(DataBaseAddress, (int)Size).ToArray();
+                byte[] unicornMem = _unicornEmu.MemoryRead(DataBaseAddress, Size);
 
-                for (int i = 0; i < (int)_size; i++)
-                {
-                    Assert.AreEqual(meilleureMem[i], unicornMem[i]);
-                }
+                Assert.That(mem, Is.EqualTo(unicornMem), "Data");
             }
         }
 
@@ -417,14 +414,17 @@ namespace Ryujinx.Tests.Cpu
                     if (IsNormalOrSubnormalS(_unicornEmu.Q[0].AsFloat()) &&
                         IsNormalOrSubnormalS(_context.GetV(0).As<float>()))
                     {
-                        Assert.That(_context.GetV(0).Extract<float>(0),
-                            Is.EqualTo(_unicornEmu.Q[0].GetFloat(0)).Within(1).Ulps);
-                        Assert.That(_context.GetV(0).Extract<float>(1),
-                            Is.EqualTo(_unicornEmu.Q[0].GetFloat(1)).Within(1).Ulps);
-                        Assert.That(_context.GetV(0).Extract<float>(2),
-                            Is.EqualTo(_unicornEmu.Q[0].GetFloat(2)).Within(1).Ulps);
-                        Assert.That(_context.GetV(0).Extract<float>(3),
-                            Is.EqualTo(_unicornEmu.Q[0].GetFloat(3)).Within(1).Ulps);
+                        Assert.Multiple(() =>
+                        {
+                            Assert.That(_context.GetV(0).Extract<float>(0),
+                                Is.EqualTo(_unicornEmu.Q[0].GetFloat(0)).Within(1).Ulps, "V0[0]");
+                            Assert.That(_context.GetV(0).Extract<float>(1),
+                                Is.EqualTo(_unicornEmu.Q[0].GetFloat(1)).Within(1).Ulps, "V0[1]");
+                            Assert.That(_context.GetV(0).Extract<float>(2),
+                                Is.EqualTo(_unicornEmu.Q[0].GetFloat(2)).Within(1).Ulps, "V0[2]");
+                            Assert.That(_context.GetV(0).Extract<float>(3),
+                                Is.EqualTo(_unicornEmu.Q[0].GetFloat(3)).Within(1).Ulps, "V0[3]");
+                        });
 
                         Console.WriteLine(fpTolerances);
                     }
@@ -439,10 +439,13 @@ namespace Ryujinx.Tests.Cpu
                     if (IsNormalOrSubnormalD(_unicornEmu.Q[0].AsDouble()) &&
                         IsNormalOrSubnormalD(_context.GetV(0).As<double>()))
                     {
-                        Assert.That(_context.GetV(0).Extract<double>(0),
-                            Is.EqualTo(_unicornEmu.Q[0].GetDouble(0)).Within(1).Ulps);
-                        Assert.That(_context.GetV(0).Extract<double>(1),
-                            Is.EqualTo(_unicornEmu.Q[0].GetDouble(1)).Within(1).Ulps);
+                        Assert.Multiple(() =>
+                        {
+                            Assert.That(_context.GetV(0).Extract<double>(0),
+                                Is.EqualTo(_unicornEmu.Q[0].GetDouble(0)).Within(1).Ulps, "V0[0]");
+                            Assert.That(_context.GetV(0).Extract<double>(1),
+                                Is.EqualTo(_unicornEmu.Q[0].GetDouble(1)).Within(1).Ulps, "V0[1]");
+                        });
 
                         Console.WriteLine(fpTolerances);
                     }
@@ -532,5 +535,28 @@ namespace Ryujinx.Tests.Cpu
 
             return rnd & 0x800FFFFFFFFFFFFFul;
         }
+
+        private uint GetFpscr()
+        {
+            uint fpscr = (uint)(_context.Fpsr & FPSR.A32Mask & ~FPSR.Nzcv) | (uint)(_context.Fpcr & FPCR.A32Mask);
+
+            fpscr |= _context.GetFPstateFlag(FPState.NFlag) ? (1u << (int)FPState.NFlag) : 0;
+            fpscr |= _context.GetFPstateFlag(FPState.ZFlag) ? (1u << (int)FPState.ZFlag) : 0;
+            fpscr |= _context.GetFPstateFlag(FPState.CFlag) ? (1u << (int)FPState.CFlag) : 0;
+            fpscr |= _context.GetFPstateFlag(FPState.VFlag) ? (1u << (int)FPState.VFlag) : 0;
+
+            return fpscr;
+        }
+
+        private void SetFpscr(uint fpscr)
+        {
+            _context.Fpsr = FPSR.A32Mask & (FPSR)fpscr;
+            _context.Fpcr = FPCR.A32Mask & (FPCR)fpscr;
+
+            _context.SetFPstateFlag(FPState.NFlag, (fpscr & (1u << (int)FPState.NFlag)) != 0);
+            _context.SetFPstateFlag(FPState.ZFlag, (fpscr & (1u << (int)FPState.ZFlag)) != 0);
+            _context.SetFPstateFlag(FPState.CFlag, (fpscr & (1u << (int)FPState.CFlag)) != 0);
+            _context.SetFPstateFlag(FPState.VFlag, (fpscr & (1u << (int)FPState.VFlag)) != 0);
+        }
     }
 }

Ryujinx.Tests/Cpu/CpuTestMisc32.cs

@@ -0,0 +1,113 @@
+#define Misc32
+
+using ARMeilleure.State;
+
+using NUnit.Framework;
+
+using System.Collections.Generic;
+
+namespace Ryujinx.Tests.Cpu
+{
+    [Category("Misc32")]
+    public sealed class CpuTestMisc32 : CpuTest32
+    {
+#if Misc32
+
+#region "ValueSource (Types)"
+        private static IEnumerable<ulong> _1S_F_()
+        {
+            yield return 0x00000000FF7FFFFFul; // -Max Normal    (float.MinValue)
+            yield return 0x0000000080800000ul; // -Min Normal
+            yield return 0x00000000807FFFFFul; // -Max Subnormal
+            yield return 0x0000000080000001ul; // -Min Subnormal (-float.Epsilon)
+            yield return 0x000000007F7FFFFFul; // +Max Normal    (float.MaxValue)
+            yield return 0x0000000000800000ul; // +Min Normal
+            yield return 0x00000000007FFFFFul; // +Max Subnormal
+            yield return 0x0000000000000001ul; // +Min Subnormal (float.Epsilon)
+
+            if (!NoZeros)
+            {
+                yield return 0x0000000080000000ul; // -Zero
+                yield return 0x0000000000000000ul; // +Zero
+            }
+
+            if (!NoInfs)
+            {
+                yield return 0x00000000FF800000ul; // -Infinity
+                yield return 0x000000007F800000ul; // +Infinity
+            }
+
+            if (!NoNaNs)
+            {
+                yield return 0x00000000FFC00000ul; // -QNaN (all zeros payload) (float.NaN)
+                yield return 0x00000000FFBFFFFFul; // -SNaN (all ones  payload)
+                yield return 0x000000007FC00000ul; // +QNaN (all zeros payload) (-float.NaN) (DefaultNaN)
+                yield return 0x000000007FBFFFFFul; // +SNaN (all ones  payload)
+            }
+
+            for (int cnt = 1; cnt <= RndCnt; cnt++)
+            {
+                ulong grbg = TestContext.CurrentContext.Random.NextUInt();
+                ulong rnd1 = GenNormalS();
+                ulong rnd2 = GenSubnormalS();
+
+                yield return (grbg << 32) | rnd1;
+                yield return (grbg << 32) | rnd2;
+            }
+        }
+#endregion
+
+        private const int RndCnt = 2;
+
+        private static readonly bool NoZeros = false;
+        private static readonly bool NoInfs  = false;
+        private static readonly bool NoNaNs  = false;
+
+        [Test, Pairwise]
+        public void Vmsr_Vcmp_Vmrs([ValueSource("_1S_F_")] ulong a,
+                                   [ValueSource("_1S_F_")] ulong b,
+                                   [Values] bool mode1,
+                                   [Values] bool mode2,
+                                   [Values] bool mode3)
+        {
+            V128 v4 = MakeVectorE0(a);
+            V128 v5 = MakeVectorE0(b);
+
+            uint r0 = mode1
+                ? TestContext.CurrentContext.Random.NextUInt(0xf) << 28
+                : TestContext.CurrentContext.Random.NextUInt();
+
+            bool v = mode3 ? TestContext.CurrentContext.Random.NextBool() : false;
+            bool c = mode3 ? TestContext.CurrentContext.Random.NextBool() : false;
+            bool z = mode3 ? TestContext.CurrentContext.Random.NextBool() : false;
+            bool n = mode3 ? TestContext.CurrentContext.Random.NextBool() : false;
+
+            int fpscr = mode1
+                ? (int)TestContext.CurrentContext.Random.NextUInt()
+                : (int)TestContext.CurrentContext.Random.NextUInt(0xf) << 28;
+
+            SetContext(r0: r0, v4: v4, v5: v5, overflow: v, carry: c, zero: z, negative: n, fpscr: fpscr);
+
+            if (mode1)
+            {
+                Opcode(0xEEE10A10); // VMSR FPSCR, R0
+            }
+            Opcode(0xEEB48A4A); // VCMP.F32 S16, S20
+            if (mode2)
+            {
+                Opcode(0xEEF10A10); // VMRS R0, FPSCR
+                Opcode(0xE200020F); // AND R0, #0xF0000000 // R0 &= "Fpsr.Nzcv".
+            }
+            if (mode3)
+            {
+                Opcode(0xEEF1FA10); // VMRS APSR_NZCV, FPSCR
+            }
+            Opcode(0xE12FFF1E); // BX LR
+
+            ExecuteOpcodes();
+
+            CompareAgainstUnicorn(fpsrMask: Fpsr.Nzcv);
+        }
+#endif
+    }
+}

Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs

@@ -44,7 +44,7 @@ namespace Ryujinx.Tests.Cpu
                                 [Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset)
         {
             var data = GenerateVectorSequence(0x1000);
-            SetWorkingMemory(data);
+            SetWorkingMemory(0, data);
 
             uint opcode = 0xf4a00000u; // VLD1.8 {D0[0]}, [R0], R0
 
@@ -74,7 +74,7 @@ namespace Ryujinx.Tests.Cpu
                              [Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset)
         {
             var data = GenerateVectorSequence(0x1000);
-            SetWorkingMemory(data);
+            SetWorkingMemory(0, data);
 
             uint opcode = 0xf4a00c00u; // VLD1.8 {D0[0]}, [R0], R0
 
@@ -100,7 +100,7 @@ namespace Ryujinx.Tests.Cpu
                               [Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset)
         {
             var data = GenerateVectorSequence(0x1000);
-            SetWorkingMemory(data);
+            SetWorkingMemory(0, data);
 
             uint opcode = 0xf4200000u; // VLD4.8 {D0, D1, D2, D3}, [R0], R0
 
@@ -124,7 +124,7 @@ namespace Ryujinx.Tests.Cpu
                                 [Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset)
         {
             var data = GenerateVectorSequence(0x1000);
-            SetWorkingMemory(data);
+            SetWorkingMemory(0, data);
 
             (V128 vec1, V128 vec2, V128 vec3, V128 vec4) = GenerateTestVectors();
 
@@ -155,7 +155,7 @@ namespace Ryujinx.Tests.Cpu
                               [Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset)
         {
             var data = GenerateVectorSequence(0x1000);
-            SetWorkingMemory(data);
+            SetWorkingMemory(0, data);
 
             (V128 vec1, V128 vec2, V128 vec3, V128 vec4) = GenerateTestVectors();
             
@@ -179,7 +179,7 @@ namespace Ryujinx.Tests.Cpu
                          [Values] bool single)
         {
             var data = GenerateVectorSequence(0x1000);
-            SetWorkingMemory(data);
+            SetWorkingMemory(0, data);
 
             uint opcode = 0xec100a00u; // VST4.8 {D0, D1, D2, D3}, [R0], R0
 
@@ -226,7 +226,7 @@ namespace Ryujinx.Tests.Cpu
                          [Values] bool sub)
         {
             var data = GenerateVectorSequence(0x1000);
-            SetWorkingMemory(data);
+            SetWorkingMemory(0, data);
 
             uint opcode = 0xed900a00u; // VLDR.32 S0, [R0, #0]
             opcode |= ((size & 3) << 8) | ((rn & 15) << 16);
@@ -261,7 +261,7 @@ namespace Ryujinx.Tests.Cpu
                 [Values] bool sub)
         {
             var data = GenerateVectorSequence(0x1000);
-            SetWorkingMemory(data);
+            SetWorkingMemory(0, data);
 
             uint opcode = 0xed800a00u; // VSTR.32 S0, [R0, #0]
             opcode |= ((size & 3) << 8) | ((rn & 15) << 16);

Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs

@@ -286,16 +286,11 @@ namespace Ryujinx.Tests.Cpu
             V128 v1 = MakeVectorE0(a);
             V128 v2 = MakeVectorE0(b);
 
-            bool v = TestContext.CurrentContext.Random.NextBool();
-            bool c = TestContext.CurrentContext.Random.NextBool();
-            bool z = TestContext.CurrentContext.Random.NextBool();
-            bool n = TestContext.CurrentContext.Random.NextBool();
-
             int fpscr = (int)(TestContext.CurrentContext.Random.NextUInt(0xf) << 28);
 
-            SingleOpcode(opcode, v1: v1, v2: v2, overflow: v, carry: c, zero: z, negative: n, fpscr: fpscr, copyFpFlags: true);
+            SingleOpcode(opcode, v1: v1, v2: v2, fpscr: fpscr);
 
-            CompareAgainstUnicorn();
+            CompareAgainstUnicorn(fpsrMask: Fpsr.Nzcv);
         }
 
         [Test, Pairwise, Description("VMLSL.<type><size> <Vd>, <Vn>, <Vm>")]

Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs

@@ -173,7 +173,7 @@ namespace Ryujinx.Tests.Cpu
         public void Vshl_Imm([Values(0u)] uint rd,
                              [Values(2u, 0u)] uint rm,
                              [Values(0u, 1u, 2u, 3u)] uint size,
-                             [Random(RndCnt), Values(0u)] uint shiftImm,
+                             [Random(RndCntShiftImm)] [Values(0u)] uint shiftImm,
                              [Random(RndCnt)] ulong z,
                              [Random(RndCnt)] ulong a,
                              [Random(RndCnt)] ulong b,
@@ -207,7 +207,7 @@ namespace Ryujinx.Tests.Cpu
         public void Vshrn_Imm([Values(0u, 1u)] uint rd,
                               [Values(2u, 0u)] uint rm,
                               [Values(0u, 1u, 2u)] uint size,
-                              [Random(RndCnt), Values(0u)] uint shiftImm,
+                              [Random(RndCntShiftImm)] [Values(0u)] uint shiftImm,
                               [Random(RndCnt)] ulong z,
                               [Random(RndCnt)] ulong a,
                               [Random(RndCnt)] ulong b)
@@ -234,7 +234,7 @@ namespace Ryujinx.Tests.Cpu
         public void Vqrshrn_Imm([Values(0u, 1u)] uint rd,
                                 [Values(2u, 0u)] uint rm,
                                 [Values(0u, 1u, 2u)] uint size,
-                                [Random(RndCnt), Values(0u)] uint shiftImm,
+                                [Random(RndCntShiftImm)] [Values(0u)] uint shiftImm,
                                 [Random(RndCnt)] ulong z,
                                 [Random(RndCnt)] ulong a,
                                 [Random(RndCnt)] ulong b,
@@ -258,16 +258,18 @@ namespace Ryujinx.Tests.Cpu
             V128 v1 = MakeVectorE0E1(a, z);
             V128 v2 = MakeVectorE0E1(b, z);
 
-            SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
+            int fpscr = (int)TestContext.CurrentContext.Random.NextUInt() & (int)Fpsr.Qc;
 
-            CompareAgainstUnicorn();
+            SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, fpscr: fpscr);
+
+            CompareAgainstUnicorn(fpsrMask: Fpsr.Qc);
         }
 
         [Test, Pairwise, Description("VQRSHRUN.<type><size> <Vd>, <Vm>, #<imm>")]
         public void Vqrshrun_Imm([Values(0u, 1u)] uint rd,
                                  [Values(2u, 0u)] uint rm,
                                  [Values(0u, 1u, 2u)] uint size,
-                                 [Random(RndCnt), Values(0u)] uint shiftImm,
+                                 [Random(RndCntShiftImm)] [Values(0u)] uint shiftImm,
                                  [Random(RndCnt)] ulong z,
                                  [Random(RndCnt)] ulong a,
                                  [Random(RndCnt)] ulong b)
@@ -285,9 +287,11 @@ namespace Ryujinx.Tests.Cpu
             V128 v1 = MakeVectorE0E1(a, z);
             V128 v2 = MakeVectorE0E1(b, z);
 
-            SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
+            int fpscr = (int)TestContext.CurrentContext.Random.NextUInt() & (int)Fpsr.Qc;
 
-            CompareAgainstUnicorn();
+            SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, fpscr: fpscr);
+
+            CompareAgainstUnicorn(fpsrMask: Fpsr.Qc);
         }
 #endif
     }