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@@ -318,12 +318,26 @@ namespace ChocolArm64.Instructions
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public static void Movi_V(ILEmitterCtx context)
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{
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- EmitVectorImmUnaryOp(context, () => { });
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+ if (Optimizations.UseSse2)
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+ {
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+ EmitMoviMvni(context, not: false);
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+ }
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+ else
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+ {
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+ EmitVectorImmUnaryOp(context, () => { });
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+ }
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}
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public static void Mvni_V(ILEmitterCtx context)
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{
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- EmitVectorImmUnaryOp(context, () => context.Emit(OpCodes.Not));
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+ if (Optimizations.UseSse2)
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+ {
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+ EmitMoviMvni(context, not: true);
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+ }
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+ else
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+ {
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+ EmitVectorImmUnaryOp(context, () => context.Emit(OpCodes.Not));
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+ }
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}
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public static void Smov_S(ILEmitterCtx context)
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@@ -480,6 +494,38 @@ namespace ChocolArm64.Instructions
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}
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}
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+ private static void EmitMoviMvni(ILEmitterCtx context, bool not)
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+ {
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+ OpCodeSimdImm64 op = (OpCodeSimdImm64)context.CurrOp;
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+
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+ Type[] typesSav = new Type[] { UIntTypesPerSizeLog2[op.Size] };
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+
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+ long imm = op.Imm;
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+
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+ if (not)
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+ {
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+ imm = ~imm;
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+ }
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+
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+ if (op.Size < 3)
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+ {
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+ context.EmitLdc_I4((int)imm);
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+ }
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+ else
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+ {
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+ context.EmitLdc_I8(imm);
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+ }
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+
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+ context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetAllVector128), typesSav));
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+
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+ context.EmitStvec(op.Rd);
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+
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+ if (op.RegisterSize == RegisterSize.Simd64)
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+ {
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+ EmitVectorZeroUpper(context, op.Rd);
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+ }
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+ }
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+
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private static void EmitVectorTranspose(ILEmitterCtx context, int part)
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{
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OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
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