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@@ -1,7 +1,6 @@
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using Ryujinx.Graphics.Shader.Decoders;
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using Ryujinx.Graphics.Shader.Decoders;
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using Ryujinx.Graphics.Shader.IntermediateRepresentation;
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using Ryujinx.Graphics.Shader.IntermediateRepresentation;
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using Ryujinx.Graphics.Shader.Translation;
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using Ryujinx.Graphics.Shader.Translation;
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-
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using static Ryujinx.Graphics.Shader.Instructions.InstEmitAluHelper;
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using static Ryujinx.Graphics.Shader.Instructions.InstEmitAluHelper;
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using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
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using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
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using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
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using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
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@@ -50,5 +49,68 @@ namespace Ryujinx.Graphics.Shader.Instructions
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context.Copy(Register(op.DestPred, RegisterType.Predicate), p0Res);
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context.Copy(Register(op.DestPred, RegisterType.Predicate), p0Res);
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context.Copy(Register(op.DestPredInv, RegisterType.Predicate), p1Res);
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context.Copy(Register(op.DestPredInv, RegisterType.Predicate), p1Res);
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}
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}
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+
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+ public static void P2rC(EmitterContext context)
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+ {
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+ InstP2rC op = context.GetOp<InstP2rC>();
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+
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+ Operand srcA = GetSrcReg(context, op.SrcA);
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+ Operand dest = GetSrcReg(context, op.Dest);
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+ Operand mask = GetSrcCbuf(context, op.CbufSlot, op.CbufOffset);
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+
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+ EmitP2r(context, srcA, dest, mask, op.ByteSel, op.Ccpr);
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+ }
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+
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+ public static void P2rI(EmitterContext context)
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+ {
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+ InstP2rI op = context.GetOp<InstP2rI>();
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+
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+ Operand srcA = GetSrcReg(context, op.SrcA);
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+ Operand dest = GetSrcReg(context, op.Dest);
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+ Operand mask = GetSrcImm(context, op.Imm20);
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+
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+ EmitP2r(context, srcA, dest, mask, op.ByteSel, op.Ccpr);
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+ }
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+
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+ public static void P2rR(EmitterContext context)
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+ {
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+ InstP2rR op = context.GetOp<InstP2rR>();
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+
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+ Operand srcA = GetSrcReg(context, op.SrcA);
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+ Operand dest = GetSrcReg(context, op.Dest);
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+ Operand mask = GetSrcReg(context, op.SrcB);
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+
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+ EmitP2r(context, srcA, dest, mask, op.ByteSel, op.Ccpr);
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+ }
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+
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+ private static void EmitP2r(
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+ EmitterContext context,
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+ Operand srcA,
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+ Operand dest,
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+ Operand mask,
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+ ByteSel byteSel,
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+ bool ccpr)
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+ {
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+ int count = ccpr ? RegisterConsts.FlagsCount : RegisterConsts.PredsCount;
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+ int shift = (int)byteSel * 8;
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+ mask = context.BitwiseAnd(mask, Const(0xff));
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+
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+ Operand insert = Const(0);
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+ for (int i = 0; i < count; i++)
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+ {
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+ Operand condition = ccpr
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+ ? Register(i, RegisterType.Flag)
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+ : Register(i, RegisterType.Predicate);
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+
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+ Operand bit = context.ConditionalSelect(condition, Const(1 << (i + shift)), Const(0));
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+ insert = context.BitwiseOr(insert, bit);
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+ }
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+
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+ Operand maskShifted = context.ShiftLeft(mask, Const(shift));
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+ Operand masked = context.BitwiseAnd(srcA, context.BitwiseNot(maskShifted));
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+ Operand res = context.BitwiseOr(masked, context.BitwiseAnd(insert, maskShifted));
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+
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+ context.Copy(dest, res);
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+ }
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}
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}
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}
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}
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